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[/] [natalius_8bit_risc/] [trunk/] [processor_core/] [shiftbyte.v] - Blame information for rev 5

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1 5 fabioandre
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: 
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// Engineer: 
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// 
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// Create Date:    19:22:46 05/02/2012 
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// Design Name: 
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// Module Name:    shifter 
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// Project Name: 
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// Target Devices: 
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// Tool versions: 
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// Description: 
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//
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// Dependencies: 
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//
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// Revision: 
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// Revision 0.01 - File Created
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// Additional Comments: 
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//
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//////////////////////////////////////////////////////////////////////////////////
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module shiftbyte(
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    input [7:0] din,
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    output reg [7:0] dshift,
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    input [2:0] sh
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    );
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        always@*
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                case (sh)
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                        0: dshift <= {din[6:0], 0};
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                        1: dshift <= {din[6:0], din[7]};
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                        2: dshift <= {0, din[7:1]};
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                        3: dshift <= {din[0], din[7:1]};
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                        4: dshift <= din;
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                        5: dshift <= {din[6:0], 1};
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                        6: dshift <= {1, din[7:1]};
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                        default: dshift <= din;
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                endcase
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endmodule

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