1 |
2 |
zero_gravi |
-- #################################################################################################
|
2 |
71 |
zero_gravi |
-- # << NEORV32 - CPU Operations Control Unit >> #
|
3 |
2 |
zero_gravi |
-- # ********************************************************************************************* #
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4 |
71 |
zero_gravi |
-- # CPU operations are controlled by several "engines" (modules). These engines operate in #
|
5 |
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-- # parallel to implement a simple pipeline: #
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6 |
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-- # + Fetch engine: Fetches 32-bit chunks of instruction words #
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7 |
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-- # + Issue engine: Decodes compressed instructions, aligns and queues instruction words #
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8 |
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-- # + Execute engine: Multi-cycle execution of instructions (generate control signals) #
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9 |
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-- # + Trap engine: Handles interrupts and exceptions #
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10 |
72 |
zero_gravi |
-- # + CSR module: Read/write access to control and status registers #
|
11 |
71 |
zero_gravi |
-- # + Debug module: CPU debug mode handling (on-chip debugger) #
|
12 |
72 |
zero_gravi |
-- # + Trigger module: Hardware-assisted breakpoints (on-chip debugger) #
|
13 |
73 |
zero_gravi |
-- # #
|
14 |
|
|
-- # NOTE: If <dedicated_reset_c> = true then <def_rst_val_c> evaluates to '-'. Registers that #
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15 |
|
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-- # reset to <def_rst_val_c> do NOT actually have a real reset by default and have to be #
|
16 |
|
|
-- # explicitly initialized by software! This is only used for "uncritical" registers. Many #
|
17 |
|
|
-- # of them will be initialized by the default crt0 start-up code. #
|
18 |
2 |
zero_gravi |
-- # ********************************************************************************************* #
|
19 |
|
|
-- # BSD 3-Clause License #
|
20 |
|
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-- # #
|
21 |
70 |
zero_gravi |
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
|
22 |
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zero_gravi |
-- # #
|
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|
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
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-- # permitted provided that the following conditions are met: #
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-- # #
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26 |
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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27 |
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-- # conditions and the following disclaimer. #
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-- # #
|
29 |
|
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
30 |
|
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-- # conditions and the following disclaimer in the documentation and/or other materials #
|
31 |
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-- # provided with the distribution. #
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-- # #
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33 |
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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35 |
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-- # permission. #
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-- # #
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37 |
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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38 |
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
39 |
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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40 |
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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41 |
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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42 |
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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44 |
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
45 |
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
46 |
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
48 |
|
|
-- #################################################################################################
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49 |
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|
50 |
|
|
library ieee;
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51 |
|
|
use ieee.std_logic_1164.all;
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52 |
|
|
use ieee.numeric_std.all;
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53 |
|
|
|
54 |
|
|
library neorv32;
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55 |
|
|
use neorv32.neorv32_package.all;
|
56 |
|
|
|
57 |
|
|
entity neorv32_cpu_control is
|
58 |
|
|
generic (
|
59 |
|
|
-- General --
|
60 |
62 |
zero_gravi |
HW_THREAD_ID : natural; -- hardware thread id (32-bit)
|
61 |
|
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
|
62 |
|
|
CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode start address
|
63 |
2 |
zero_gravi |
-- RISC-V CPU Extensions --
|
64 |
62 |
zero_gravi |
CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
|
65 |
66 |
zero_gravi |
CPU_EXTENSION_RISCV_B : boolean; -- implement bit-manipulation extension?
|
66 |
62 |
zero_gravi |
CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
|
67 |
|
|
CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension?
|
68 |
66 |
zero_gravi |
CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
|
69 |
62 |
zero_gravi |
CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension?
|
70 |
|
|
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
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71 |
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|
CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
|
72 |
66 |
zero_gravi |
CPU_EXTENSION_RISCV_Zicntr : boolean; -- implement base counters?
|
73 |
|
|
CPU_EXTENSION_RISCV_Zihpm : boolean; -- implement hardware performance monitors?
|
74 |
62 |
zero_gravi |
CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
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75 |
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|
CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
|
76 |
72 |
zero_gravi |
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
|
77 |
62 |
zero_gravi |
CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
|
78 |
72 |
zero_gravi |
-- Tuning Options --
|
79 |
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FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
|
80 |
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FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
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81 |
62 |
zero_gravi |
CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
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82 |
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CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2
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83 |
15 |
zero_gravi |
-- Physical memory protection (PMP) --
|
84 |
73 |
zero_gravi |
PMP_NUM_REGIONS : natural; -- number of regions (0..16)
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85 |
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PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
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86 |
42 |
zero_gravi |
-- Hardware Performance Monitors (HPM) --
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87 |
62 |
zero_gravi |
HPM_NUM_CNTS : natural; -- number of implemented HPM counters (0..29)
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88 |
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HPM_CNT_WIDTH : natural -- total size of HPM counters (0..64)
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89 |
2 |
zero_gravi |
);
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90 |
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port (
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91 |
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|
-- global control --
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92 |
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clk_i : in std_ulogic; -- global clock, rising edge
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93 |
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rstn_i : in std_ulogic; -- global reset, low-active, async
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94 |
|
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ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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95 |
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-- status input --
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96 |
61 |
zero_gravi |
alu_idone_i : in std_ulogic; -- ALU iterative operation done
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97 |
12 |
zero_gravi |
bus_i_wait_i : in std_ulogic; -- wait for bus
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98 |
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bus_d_wait_i : in std_ulogic; -- wait for bus
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99 |
57 |
zero_gravi |
excl_state_i : in std_ulogic; -- atomic/exclusive access lock status
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100 |
2 |
zero_gravi |
-- data input --
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101 |
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instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
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102 |
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
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103 |
36 |
zero_gravi |
alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
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104 |
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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105 |
2 |
zero_gravi |
-- data output --
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106 |
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imm_o : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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107 |
6 |
zero_gravi |
fetch_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
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108 |
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curr_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
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109 |
68 |
zero_gravi |
next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to next instruction)
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110 |
2 |
zero_gravi |
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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111 |
52 |
zero_gravi |
-- FPU interface --
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112 |
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fpu_flags_i : in std_ulogic_vector(04 downto 0); -- exception flags
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113 |
59 |
zero_gravi |
-- debug mode (halt) request --
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114 |
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db_halt_req_i : in std_ulogic;
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115 |
14 |
zero_gravi |
-- interrupts (risc-v compliant) --
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116 |
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msw_irq_i : in std_ulogic; -- machine software interrupt
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117 |
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mext_irq_i : in std_ulogic; -- machine external interrupt
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118 |
2 |
zero_gravi |
mtime_irq_i : in std_ulogic; -- machine timer interrupt
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119 |
14 |
zero_gravi |
-- fast interrupts (custom) --
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120 |
48 |
zero_gravi |
firq_i : in std_ulogic_vector(15 downto 0);
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121 |
11 |
zero_gravi |
-- system time input from MTIME --
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122 |
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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123 |
15 |
zero_gravi |
-- physical memory protection --
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124 |
23 |
zero_gravi |
pmp_addr_o : out pmp_addr_if_t; -- addresses
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125 |
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pmp_ctrl_o : out pmp_ctrl_if_t; -- configs
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126 |
2 |
zero_gravi |
-- bus access exceptions --
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127 |
66 |
zero_gravi |
mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
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128 |
2 |
zero_gravi |
ma_instr_i : in std_ulogic; -- misaligned instruction address
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129 |
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ma_load_i : in std_ulogic; -- misaligned load data address
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130 |
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ma_store_i : in std_ulogic; -- misaligned store data address
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131 |
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be_instr_i : in std_ulogic; -- bus error on instruction access
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132 |
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be_load_i : in std_ulogic; -- bus error on load data access
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133 |
12 |
zero_gravi |
be_store_i : in std_ulogic -- bus error on store data access
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134 |
2 |
zero_gravi |
);
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135 |
|
|
end neorv32_cpu_control;
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136 |
|
|
|
137 |
|
|
architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
|
138 |
|
|
|
139 |
56 |
zero_gravi |
-- CPU core counter ([m]cycle, [m]instret) width - high/low parts --
|
140 |
|
|
constant cpu_cnt_lo_width_c : natural := natural(cond_sel_int_f(boolean(CPU_CNT_WIDTH < 32), CPU_CNT_WIDTH, 32));
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141 |
|
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constant cpu_cnt_hi_width_c : natural := natural(cond_sel_int_f(boolean(CPU_CNT_WIDTH > 32), CPU_CNT_WIDTH-32, 0));
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142 |
|
|
|
143 |
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-- HPM counter width - high/low parts --
|
144 |
|
|
constant hpm_cnt_lo_width_c : natural := natural(cond_sel_int_f(boolean(HPM_CNT_WIDTH < 32), HPM_CNT_WIDTH, 32));
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145 |
|
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constant hpm_cnt_hi_width_c : natural := natural(cond_sel_int_f(boolean(HPM_CNT_WIDTH > 32), HPM_CNT_WIDTH-32, 0));
|
146 |
|
|
|
147 |
57 |
zero_gravi |
-- instruction fetch engine --
|
148 |
|
|
type fetch_engine_state_t is (IFETCH_REQUEST, IFETCH_ISSUE);
|
149 |
6 |
zero_gravi |
type fetch_engine_t is record
|
150 |
31 |
zero_gravi |
state : fetch_engine_state_t;
|
151 |
|
|
state_nxt : fetch_engine_state_t;
|
152 |
42 |
zero_gravi |
state_prev : fetch_engine_state_t;
|
153 |
57 |
zero_gravi |
restart : std_ulogic;
|
154 |
|
|
restart_nxt : std_ulogic;
|
155 |
74 |
zero_gravi |
align : std_ulogic;
|
156 |
|
|
align_nxt : std_ulogic;
|
157 |
31 |
zero_gravi |
pc : std_ulogic_vector(data_width_c-1 downto 0);
|
158 |
|
|
pc_nxt : std_ulogic_vector(data_width_c-1 downto 0);
|
159 |
|
|
reset : std_ulogic;
|
160 |
74 |
zero_gravi |
bus_if : std_ulogic;
|
161 |
6 |
zero_gravi |
end record;
|
162 |
|
|
signal fetch_engine : fetch_engine_t;
|
163 |
2 |
zero_gravi |
|
164 |
61 |
zero_gravi |
-- instruction prefetch buffer (FIFO) interface --
|
165 |
74 |
zero_gravi |
type ipb_data_t is array (0 to 1) of std_ulogic_vector((2+16)-1 downto 0); -- status (bus_error, align_error) + 16-bit instruction
|
166 |
6 |
zero_gravi |
type ipb_t is record
|
167 |
74 |
zero_gravi |
wdata : ipb_data_t;
|
168 |
|
|
we : std_ulogic_vector(1 downto 0); -- trigger write
|
169 |
|
|
free : std_ulogic_vector(1 downto 0); -- free entry available?
|
170 |
|
|
rdata : ipb_data_t;
|
171 |
|
|
re : std_ulogic_vector(1 downto 0); -- read enable
|
172 |
|
|
avail : std_ulogic_vector(1 downto 0); -- data available?
|
173 |
6 |
zero_gravi |
end record;
|
174 |
|
|
signal ipb : ipb_t;
|
175 |
2 |
zero_gravi |
|
176 |
57 |
zero_gravi |
-- instruction issue engine --
|
177 |
31 |
zero_gravi |
type issue_engine_t is record
|
178 |
74 |
zero_gravi |
align : std_ulogic;
|
179 |
|
|
align_set : std_ulogic;
|
180 |
|
|
align_clr : std_ulogic;
|
181 |
|
|
ci_i16 : std_ulogic_vector(15 downto 0);
|
182 |
|
|
ci_i32 : std_ulogic_vector(31 downto 0);
|
183 |
|
|
ci_ill : std_ulogic;
|
184 |
|
|
data : std_ulogic_vector((4+32)-1 downto 0); -- 4-bit status + 32-bit instruction
|
185 |
|
|
valid : std_ulogic_vector(1 downto 0); -- data word is valid when != 0
|
186 |
31 |
zero_gravi |
end record;
|
187 |
|
|
signal issue_engine : issue_engine_t;
|
188 |
|
|
|
189 |
44 |
zero_gravi |
-- instruction decoding helper logic --
|
190 |
|
|
type decode_aux_t is record
|
191 |
73 |
zero_gravi |
is_a_lr : std_ulogic;
|
192 |
|
|
is_a_sc : std_ulogic;
|
193 |
|
|
is_f_op : std_ulogic;
|
194 |
|
|
is_m_mul : std_ulogic;
|
195 |
|
|
is_m_div : std_ulogic;
|
196 |
|
|
is_b_imm : std_ulogic;
|
197 |
|
|
is_b_reg : std_ulogic;
|
198 |
|
|
rs1_zero : std_ulogic;
|
199 |
|
|
rd_zero : std_ulogic;
|
200 |
44 |
zero_gravi |
end record;
|
201 |
|
|
signal decode_aux : decode_aux_t;
|
202 |
|
|
|
203 |
6 |
zero_gravi |
-- instruction execution engine --
|
204 |
73 |
zero_gravi |
type execute_engine_state_t is (DISPATCH, TRAP_ENTER, TRAP_EXIT, TRAP_EXECUTE, EXECUTE, ALU_WAIT,
|
205 |
74 |
zero_gravi |
BRANCH, BRANCHED, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, SYSTEM);
|
206 |
6 |
zero_gravi |
type execute_engine_t is record
|
207 |
|
|
state : execute_engine_state_t;
|
208 |
|
|
state_nxt : execute_engine_state_t;
|
209 |
42 |
zero_gravi |
state_prev : execute_engine_state_t;
|
210 |
39 |
zero_gravi |
--
|
211 |
6 |
zero_gravi |
i_reg : std_ulogic_vector(31 downto 0);
|
212 |
|
|
i_reg_nxt : std_ulogic_vector(31 downto 0);
|
213 |
33 |
zero_gravi |
i_reg_last : std_ulogic_vector(31 downto 0); -- last executed instruction
|
214 |
39 |
zero_gravi |
--
|
215 |
6 |
zero_gravi |
is_ci : std_ulogic; -- current instruction is de-compressed instruction
|
216 |
|
|
is_ci_nxt : std_ulogic;
|
217 |
66 |
zero_gravi |
is_ici : std_ulogic; -- current instruction is illegal de-compressed instruction
|
218 |
|
|
is_ici_nxt : std_ulogic;
|
219 |
39 |
zero_gravi |
--
|
220 |
57 |
zero_gravi |
branch_taken : std_ulogic; -- branch condition fulfilled
|
221 |
6 |
zero_gravi |
pc : std_ulogic_vector(data_width_c-1 downto 0); -- actual PC, corresponding to current executed instruction
|
222 |
49 |
zero_gravi |
pc_mux_sel : std_ulogic; -- source select for PC update
|
223 |
39 |
zero_gravi |
pc_we : std_ulogic; -- PC update enabled
|
224 |
6 |
zero_gravi |
next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next PC, corresponding to next instruction to be executed
|
225 |
49 |
zero_gravi |
next_pc_inc : std_ulogic_vector(data_width_c-1 downto 0); -- increment to get next PC
|
226 |
73 |
zero_gravi |
pc_last : std_ulogic_vector(data_width_c-1 downto 0); -- PC of last executed instruction
|
227 |
39 |
zero_gravi |
--
|
228 |
11 |
zero_gravi |
sleep : std_ulogic; -- CPU in sleep mode
|
229 |
39 |
zero_gravi |
sleep_nxt : std_ulogic;
|
230 |
49 |
zero_gravi |
branched : std_ulogic; -- instruction fetch was reset
|
231 |
|
|
branched_nxt : std_ulogic;
|
232 |
6 |
zero_gravi |
end record;
|
233 |
|
|
signal execute_engine : execute_engine_t;
|
234 |
2 |
zero_gravi |
|
235 |
6 |
zero_gravi |
-- trap controller --
|
236 |
|
|
type trap_ctrl_t is record
|
237 |
73 |
zero_gravi |
exc_buf : std_ulogic_vector(exc_width_c-1 downto 0);
|
238 |
6 |
zero_gravi |
exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer
|
239 |
73 |
zero_gravi |
irq_buf : std_ulogic_vector(irq_width_c-1 downto 0);
|
240 |
6 |
zero_gravi |
irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
|
241 |
59 |
zero_gravi |
cause : std_ulogic_vector(6 downto 0); -- trap ID for mcause CSR
|
242 |
|
|
cause_nxt : std_ulogic_vector(6 downto 0);
|
243 |
|
|
db_irq_fire : std_ulogic; -- set if there is a valid IRQ source in the "enter debug mode" trap buffer
|
244 |
63 |
zero_gravi |
db_irq_en : std_ulogic; -- set if IRQs are allowed in debug mode
|
245 |
6 |
zero_gravi |
--
|
246 |
|
|
env_start : std_ulogic; -- start trap handler env
|
247 |
|
|
env_start_ack : std_ulogic; -- start of trap handler acknowledged
|
248 |
|
|
env_end : std_ulogic; -- end trap handler env
|
249 |
|
|
--
|
250 |
|
|
instr_be : std_ulogic; -- instruction fetch bus error
|
251 |
|
|
instr_ma : std_ulogic; -- instruction fetch misaligned address
|
252 |
|
|
instr_il : std_ulogic; -- illegal instruction
|
253 |
71 |
zero_gravi |
env_call : std_ulogic; -- ecall instruction
|
254 |
|
|
break_point : std_ulogic; -- ebreak instruction
|
255 |
6 |
zero_gravi |
end record;
|
256 |
|
|
signal trap_ctrl : trap_ctrl_t;
|
257 |
|
|
|
258 |
40 |
zero_gravi |
-- CPU main control bus --
|
259 |
6 |
zero_gravi |
signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
|
260 |
2 |
zero_gravi |
|
261 |
6 |
zero_gravi |
-- RISC-V control and status registers (CSRs) --
|
262 |
73 |
zero_gravi |
type pmpcfg_t is array (0 to 15) of std_ulogic_vector(7 downto 0);
|
263 |
|
|
type pmpaddr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2);
|
264 |
42 |
zero_gravi |
type mhpmevent_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
|
265 |
73 |
zero_gravi |
type mhpmevent_rd_t is array (0 to 28) of std_ulogic_vector(data_width_c-1 downto 0);
|
266 |
|
|
type mhpmcnt_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(data_width_c-1 downto 0);
|
267 |
|
|
type mhpmcnt_nxt_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(data_width_c downto 0);
|
268 |
61 |
zero_gravi |
type mhpmcnt_ovfl_t is array (0 to HPM_NUM_CNTS-1) of std_ulogic_vector(0 downto 0);
|
269 |
73 |
zero_gravi |
type mhpmcnt_rd_t is array (0 to 29) of std_ulogic_vector(data_width_c-1 downto 0);
|
270 |
6 |
zero_gravi |
type csr_t is record
|
271 |
42 |
zero_gravi |
addr : std_ulogic_vector(11 downto 0); -- csr address
|
272 |
|
|
we : std_ulogic; -- csr write enable
|
273 |
|
|
we_nxt : std_ulogic;
|
274 |
74 |
zero_gravi |
re : std_ulogic; -- csr read enable
|
275 |
|
|
re_nxt : std_ulogic;
|
276 |
42 |
zero_gravi |
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
|
277 |
|
|
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
278 |
29 |
zero_gravi |
--
|
279 |
42 |
zero_gravi |
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
|
280 |
|
|
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W)
|
281 |
73 |
zero_gravi |
mstatus_mpp : std_ulogic; -- mstatus.MPP: machine previous privilege mode
|
282 |
|
|
mstatus_tw : std_ulogic; -- mstatus.TW: do not allow user mode to execute WFI instruction when set
|
283 |
29 |
zero_gravi |
--
|
284 |
42 |
zero_gravi |
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
|
285 |
|
|
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
|
286 |
|
|
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
|
287 |
48 |
zero_gravi |
mie_firqe : std_ulogic_vector(15 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
|
288 |
29 |
zero_gravi |
--
|
289 |
73 |
zero_gravi |
mip_firq_nclr : std_ulogic_vector(15 downto 0); -- clear pending FIRQ (active-low)
|
290 |
69 |
zero_gravi |
--
|
291 |
42 |
zero_gravi |
mcounteren_cy : std_ulogic; -- mcounteren.cy: allow cycle[h] access from user-mode
|
292 |
|
|
mcounteren_tm : std_ulogic; -- mcounteren.tm: allow time[h] access from user-mode
|
293 |
|
|
mcounteren_ir : std_ulogic; -- mcounteren.ir: allow instret[h] access from user-mode
|
294 |
29 |
zero_gravi |
--
|
295 |
42 |
zero_gravi |
mcountinhibit_cy : std_ulogic; -- mcounterinhibit.cy: enable auto-increment for [m]cycle[h]
|
296 |
|
|
mcountinhibit_ir : std_ulogic; -- mcounterinhibit.ir: enable auto-increment for [m]instret[h]
|
297 |
|
|
mcountinhibit_hpm : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); -- mcounterinhibit.hpm3: enable auto-increment for mhpmcounterx[h]
|
298 |
40 |
zero_gravi |
--
|
299 |
73 |
zero_gravi |
privilege : std_ulogic; -- current privilege mode
|
300 |
|
|
privilege_eff : std_ulogic; -- current *effective* privilege mode
|
301 |
41 |
zero_gravi |
--
|
302 |
42 |
zero_gravi |
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
|
303 |
49 |
zero_gravi |
mcause : std_ulogic_vector(5 downto 0); -- mcause: machine trap cause (R/W)
|
304 |
42 |
zero_gravi |
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00
|
305 |
49 |
zero_gravi |
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or instruction (R/W)
|
306 |
42 |
zero_gravi |
--
|
307 |
|
|
mhpmevent : mhpmevent_t; -- mhpmevent*: machine performance-monitoring event selector (R/W)
|
308 |
73 |
zero_gravi |
mhpmevent_rd : mhpmevent_rd_t; -- read data
|
309 |
42 |
zero_gravi |
--
|
310 |
|
|
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
|
311 |
56 |
zero_gravi |
--
|
312 |
73 |
zero_gravi |
mcycle : std_ulogic_vector(data_width_c-1 downto 0); -- mcycle (R/W)
|
313 |
|
|
mcycle_nxt : std_ulogic_vector(data_width_c downto 0);
|
314 |
61 |
zero_gravi |
mcycle_ovfl : std_ulogic_vector(00 downto 0); -- counter low-to-high-word overflow
|
315 |
73 |
zero_gravi |
mcycleh : std_ulogic_vector(data_width_c-1 downto 0); -- mcycleh (R/W)
|
316 |
|
|
minstret : std_ulogic_vector(data_width_c-1 downto 0); -- minstret (R/W)
|
317 |
|
|
minstret_nxt : std_ulogic_vector(data_width_c downto 0);
|
318 |
61 |
zero_gravi |
minstret_ovfl : std_ulogic_vector(00 downto 0); -- counter low-to-high-word overflow
|
319 |
73 |
zero_gravi |
minstreth : std_ulogic_vector(data_width_c-1 downto 0); -- minstreth (R/W)
|
320 |
42 |
zero_gravi |
--
|
321 |
|
|
mhpmcounter : mhpmcnt_t; -- mhpmcounter* (R/W), plus carry bit
|
322 |
61 |
zero_gravi |
mhpmcounter_nxt : mhpmcnt_nxt_t;
|
323 |
|
|
mhpmcounter_ovfl : mhpmcnt_ovfl_t; -- counter low-to-high-word overflow
|
324 |
|
|
mhpmcounterh : mhpmcnt_t; -- mhpmcounter*h (R/W)
|
325 |
42 |
zero_gravi |
mhpmcounter_rd : mhpmcnt_rd_t; -- mhpmcounter* (R/W): actual read data
|
326 |
61 |
zero_gravi |
mhpmcounterh_rd : mhpmcnt_rd_t; -- mhpmcounter*h (R/W): actual read data
|
327 |
42 |
zero_gravi |
--
|
328 |
73 |
zero_gravi |
pmpcfg : pmpcfg_t; -- physical memory protection - configuration registers
|
329 |
|
|
pmpaddr : pmpaddr_t; -- physical memory protection - address registers (bits 33:2 of PHYSICAL address)
|
330 |
52 |
zero_gravi |
--
|
331 |
|
|
frm : std_ulogic_vector(02 downto 0); -- frm (R/W): FPU rounding mode
|
332 |
|
|
fflags : std_ulogic_vector(04 downto 0); -- fflags (R/W): FPU exception flags
|
333 |
59 |
zero_gravi |
--
|
334 |
|
|
dcsr_ebreakm : std_ulogic; -- dcsr.ebreakm (R/W): behavior of ebreak instruction on m-mode
|
335 |
|
|
dcsr_ebreaku : std_ulogic; -- dcsr.ebreaku (R/W): behavior of ebreak instruction on u-mode
|
336 |
|
|
dcsr_step : std_ulogic; -- dcsr.step (R/W): single-step mode
|
337 |
73 |
zero_gravi |
dcsr_prv : std_ulogic; -- dcsr.prv (R/W): current privilege level when entering debug mode
|
338 |
59 |
zero_gravi |
dcsr_cause : std_ulogic_vector(02 downto 0); -- dcsr.cause (R/-): why was debug mode entered
|
339 |
|
|
dcsr_rd : std_ulogic_vector(data_width_c-1 downto 0); -- dcsr (R/(W)): debug mode control and status register
|
340 |
|
|
dpc : std_ulogic_vector(data_width_c-1 downto 0); -- dpc (R/W): debug mode program counter
|
341 |
|
|
dscratch0 : std_ulogic_vector(data_width_c-1 downto 0); -- dscratch0 (R/W): debug mode scratch register 0
|
342 |
72 |
zero_gravi |
--
|
343 |
|
|
tdata1_exe : std_ulogic; -- enable (match) trigger
|
344 |
|
|
tdata1_rd : std_ulogic_vector(data_width_c-1 downto 0); -- tdata1 (R/(W)): trigger register read-back
|
345 |
|
|
tdata2 : std_ulogic_vector(data_width_c-1 downto 0); -- tdata2 (R/W): address-match register
|
346 |
6 |
zero_gravi |
end record;
|
347 |
|
|
signal csr : csr_t;
|
348 |
2 |
zero_gravi |
|
349 |
59 |
zero_gravi |
-- debug mode controller --
|
350 |
|
|
type debug_ctrl_state_t is (DEBUG_OFFLINE, DEBUG_PENDING, DEBUG_ONLINE, DEBUG_EXIT);
|
351 |
|
|
type debug_ctrl_t is record
|
352 |
|
|
state : debug_ctrl_state_t;
|
353 |
|
|
-- decoded state --
|
354 |
|
|
running : std_ulogic; -- debug mode active
|
355 |
|
|
pending : std_ulogic; -- waiting to start debug mode
|
356 |
|
|
-- entering triggers --
|
357 |
72 |
zero_gravi |
trig_hw : std_ulogic; -- hardware trigger
|
358 |
59 |
zero_gravi |
trig_break : std_ulogic; -- ebreak instruction
|
359 |
|
|
trig_halt : std_ulogic; -- external request
|
360 |
|
|
trig_step : std_ulogic; -- single-stepping mode
|
361 |
|
|
-- leave debug mode --
|
362 |
|
|
dret : std_ulogic; -- executed DRET instruction
|
363 |
|
|
-- misc --
|
364 |
64 |
zero_gravi |
ext_halt_req : std_ulogic;
|
365 |
59 |
zero_gravi |
end record;
|
366 |
|
|
signal debug_ctrl : debug_ctrl_t;
|
367 |
|
|
|
368 |
42 |
zero_gravi |
-- (hpm) counter events --
|
369 |
68 |
zero_gravi |
signal cnt_event : std_ulogic_vector(hpmcnt_event_size_c-1 downto 0);
|
370 |
|
|
signal hpmcnt_trigger : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0);
|
371 |
42 |
zero_gravi |
|
372 |
6 |
zero_gravi |
-- illegal instruction check --
|
373 |
74 |
zero_gravi |
signal illegal_cmd : std_ulogic;
|
374 |
|
|
signal illegal_reg : std_ulogic; -- illegal register (>x15) - E-extension
|
375 |
2 |
zero_gravi |
|
376 |
15 |
zero_gravi |
-- access (privilege) check --
|
377 |
|
|
signal csr_acc_valid : std_ulogic; -- valid CSR access (implemented and valid access rights)
|
378 |
|
|
|
379 |
72 |
zero_gravi |
-- hardware trigger module --
|
380 |
|
|
signal hw_trigger_fire : std_ulogic;
|
381 |
|
|
|
382 |
2 |
zero_gravi |
begin
|
383 |
|
|
|
384 |
6 |
zero_gravi |
-- ****************************************************************************************************************************
|
385 |
56 |
zero_gravi |
-- Instruction Fetch (always fetch 32-bit-aligned 32-bit chunks of data)
|
386 |
6 |
zero_gravi |
-- ****************************************************************************************************************************
|
387 |
|
|
|
388 |
|
|
-- Fetch Engine FSM Sync ------------------------------------------------------------------
|
389 |
|
|
-- -------------------------------------------------------------------------------------------
|
390 |
31 |
zero_gravi |
fetch_engine_fsm_sync: process(rstn_i, clk_i)
|
391 |
6 |
zero_gravi |
begin
|
392 |
|
|
if (rstn_i = '0') then
|
393 |
57 |
zero_gravi |
fetch_engine.state <= IFETCH_REQUEST;
|
394 |
|
|
fetch_engine.state_prev <= IFETCH_REQUEST;
|
395 |
|
|
fetch_engine.restart <= '1';
|
396 |
74 |
zero_gravi |
fetch_engine.align <= '0'; -- always start at aligned address after reset
|
397 |
56 |
zero_gravi |
fetch_engine.pc <= (others => def_rst_val_c);
|
398 |
6 |
zero_gravi |
elsif rising_edge(clk_i) then
|
399 |
57 |
zero_gravi |
fetch_engine.state <= fetch_engine.state_nxt;
|
400 |
|
|
fetch_engine.state_prev <= fetch_engine.state;
|
401 |
69 |
zero_gravi |
fetch_engine.restart <= fetch_engine.restart_nxt or fetch_engine.reset;
|
402 |
74 |
zero_gravi |
fetch_engine.align <= fetch_engine.align_nxt and bool_to_ulogic_f(CPU_EXTENSION_RISCV_C);
|
403 |
73 |
zero_gravi |
fetch_engine.pc <= fetch_engine.pc_nxt;
|
404 |
6 |
zero_gravi |
end if;
|
405 |
|
|
end process fetch_engine_fsm_sync;
|
406 |
|
|
|
407 |
12 |
zero_gravi |
-- PC output --
|
408 |
31 |
zero_gravi |
fetch_pc_o <= fetch_engine.pc(data_width_c-1 downto 1) & '0'; -- half-word aligned
|
409 |
6 |
zero_gravi |
|
410 |
12 |
zero_gravi |
|
411 |
6 |
zero_gravi |
-- Fetch Engine FSM Comb ------------------------------------------------------------------
|
412 |
|
|
-- -------------------------------------------------------------------------------------------
|
413 |
31 |
zero_gravi |
fetch_engine_fsm_comb: process(fetch_engine, execute_engine, ipb, instr_i, bus_i_wait_i, be_instr_i, ma_instr_i)
|
414 |
6 |
zero_gravi |
begin
|
415 |
|
|
-- arbiter defaults --
|
416 |
74 |
zero_gravi |
fetch_engine.bus_if <= '0';
|
417 |
31 |
zero_gravi |
fetch_engine.state_nxt <= fetch_engine.state;
|
418 |
|
|
fetch_engine.pc_nxt <= fetch_engine.pc;
|
419 |
69 |
zero_gravi |
fetch_engine.restart_nxt <= fetch_engine.restart;
|
420 |
74 |
zero_gravi |
fetch_engine.align_nxt <= fetch_engine.align;
|
421 |
6 |
zero_gravi |
|
422 |
69 |
zero_gravi |
-- instruction prefetch buffer defaults --
|
423 |
74 |
zero_gravi |
ipb.we <= "00";
|
424 |
|
|
ipb.wdata(0) <= be_instr_i & ma_instr_i & instr_i(15 downto 00);
|
425 |
|
|
ipb.wdata(1) <= be_instr_i & ma_instr_i & instr_i(31 downto 16);
|
426 |
6 |
zero_gravi |
|
427 |
|
|
-- state machine --
|
428 |
74 |
zero_gravi |
if (fetch_engine.state = IFETCH_REQUEST) then -- REQUEST: request new 32-bit-aligned instruction word
|
429 |
71 |
zero_gravi |
-- ------------------------------------------------------------
|
430 |
73 |
zero_gravi |
if (fetch_engine.restart = '1') then -- reset request
|
431 |
74 |
zero_gravi |
fetch_engine.pc_nxt <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
|
432 |
|
|
fetch_engine.align_nxt <= execute_engine.pc(1);
|
433 |
|
|
elsif (ipb.free = "11") then -- free entries in both buffers
|
434 |
|
|
fetch_engine.bus_if <= '1'; -- instruction fetch request
|
435 |
71 |
zero_gravi |
fetch_engine.state_nxt <= IFETCH_ISSUE;
|
436 |
|
|
end if;
|
437 |
74 |
zero_gravi |
fetch_engine.restart_nxt <= '0'; -- restart done
|
438 |
6 |
zero_gravi |
|
439 |
74 |
zero_gravi |
else -- ISSUE: store instruction data to prefetch buffer
|
440 |
71 |
zero_gravi |
-- ------------------------------------------------------------
|
441 |
|
|
if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
|
442 |
|
|
fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
|
443 |
74 |
zero_gravi |
fetch_engine.align_nxt <= '0';
|
444 |
57 |
zero_gravi |
fetch_engine.state_nxt <= IFETCH_REQUEST;
|
445 |
74 |
zero_gravi |
if (fetch_engine.restart = '0') then -- write to IPB if not being reset
|
446 |
|
|
ipb.we(0) <= not fetch_engine.align; -- not start at unaligned address
|
447 |
|
|
ipb.we(1) <= '1';
|
448 |
|
|
end if;
|
449 |
71 |
zero_gravi |
end if;
|
450 |
6 |
zero_gravi |
|
451 |
71 |
zero_gravi |
end if;
|
452 |
6 |
zero_gravi |
end process fetch_engine_fsm_comb;
|
453 |
|
|
|
454 |
|
|
|
455 |
|
|
-- ****************************************************************************************************************************
|
456 |
|
|
-- Instruction Prefetch Buffer
|
457 |
|
|
-- ****************************************************************************************************************************
|
458 |
|
|
|
459 |
20 |
zero_gravi |
-- Instruction Prefetch Buffer (FIFO) -----------------------------------------------------
|
460 |
6 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
461 |
74 |
zero_gravi |
prefetch_buffer:
|
462 |
|
|
for i in 0 to 1 generate -- high half-word and low half-word
|
463 |
|
|
prefetch_buffer_inst: neorv32_fifo
|
464 |
|
|
generic map (
|
465 |
|
|
FIFO_DEPTH => CPU_IPB_ENTRIES, -- number of fifo entries; has to be a power of two; min 1
|
466 |
|
|
FIFO_WIDTH => ipb.wdata(i)'length, -- size of data elements in fifo
|
467 |
|
|
FIFO_RSYNC => false, -- we NEED to read data asynchronously
|
468 |
|
|
FIFO_SAFE => false -- no safe access required (ensured by FIFO-external control)
|
469 |
|
|
)
|
470 |
|
|
port map (
|
471 |
|
|
-- control --
|
472 |
|
|
clk_i => clk_i, -- clock, rising edge
|
473 |
|
|
rstn_i => '1', -- async reset, low-active
|
474 |
|
|
clear_i => fetch_engine.restart, -- sync reset, high-active
|
475 |
|
|
level_o => open,
|
476 |
|
|
half_o => open,
|
477 |
|
|
-- write port --
|
478 |
|
|
wdata_i => ipb.wdata(i), -- write data
|
479 |
|
|
we_i => ipb.we(i), -- write enable
|
480 |
|
|
free_o => ipb.free(i), -- at least one entry is free when set
|
481 |
|
|
-- read port --
|
482 |
|
|
re_i => ipb.re(i), -- read enable
|
483 |
|
|
rdata_o => ipb.rdata(i), -- read data
|
484 |
|
|
avail_o => ipb.avail(i) -- data available when set
|
485 |
|
|
);
|
486 |
|
|
end generate;
|
487 |
20 |
zero_gravi |
|
488 |
56 |
zero_gravi |
|
489 |
6 |
zero_gravi |
-- ****************************************************************************************************************************
|
490 |
74 |
zero_gravi |
-- Instruction Issue (decompress 16-bit instructions and assemble 32-bit instruction word)
|
491 |
31 |
zero_gravi |
-- ****************************************************************************************************************************
|
492 |
|
|
|
493 |
|
|
-- Issue Engine FSM Sync ------------------------------------------------------------------
|
494 |
|
|
-- -------------------------------------------------------------------------------------------
|
495 |
|
|
issue_engine_fsm_sync: process(rstn_i, clk_i)
|
496 |
|
|
begin
|
497 |
74 |
zero_gravi |
if (rstn_i = '0') then
|
498 |
|
|
issue_engine.align <= '0'; -- always start aligned after reset
|
499 |
31 |
zero_gravi |
elsif rising_edge(clk_i) then
|
500 |
74 |
zero_gravi |
if (CPU_EXTENSION_RISCV_C = true) then
|
501 |
|
|
if (fetch_engine.restart = '1') then
|
502 |
|
|
issue_engine.align <= execute_engine.pc(1); -- branch to unaligned address?
|
503 |
|
|
elsif (execute_engine.state = DISPATCH) then
|
504 |
|
|
issue_engine.align <= (issue_engine.align and (not issue_engine.align_clr)) or issue_engine.align_set;
|
505 |
31 |
zero_gravi |
end if;
|
506 |
|
|
else
|
507 |
74 |
zero_gravi |
issue_engine.align <= '0'; -- always aligned
|
508 |
31 |
zero_gravi |
end if;
|
509 |
|
|
end if;
|
510 |
|
|
end process issue_engine_fsm_sync;
|
511 |
|
|
|
512 |
|
|
|
513 |
|
|
-- Issue Engine FSM Comb ------------------------------------------------------------------
|
514 |
|
|
-- -------------------------------------------------------------------------------------------
|
515 |
74 |
zero_gravi |
issue_engine_fsm_comb: process(issue_engine.align, ipb)
|
516 |
31 |
zero_gravi |
begin
|
517 |
74 |
zero_gravi |
-- defaults --
|
518 |
|
|
issue_engine.align_set <= '0';
|
519 |
|
|
issue_engine.align_clr <= '0';
|
520 |
|
|
issue_engine.valid <= "00";
|
521 |
31 |
zero_gravi |
|
522 |
74 |
zero_gravi |
-- start with LOW half-word --
|
523 |
|
|
if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then
|
524 |
|
|
if (CPU_EXTENSION_RISCV_C = true) and (ipb.rdata(0)(1 downto 0) /= "11") then -- compressed
|
525 |
|
|
issue_engine.align_set <= ipb.avail(0); -- start of next instruction word is not 32-bit aligned
|
526 |
|
|
issue_engine.valid(0) <= ipb.avail(0);
|
527 |
|
|
issue_engine.data <= issue_engine.ci_ill & ipb.rdata(0)(17 downto 16) & '1' & issue_engine.ci_i32;
|
528 |
|
|
else -- aligned uncompressed
|
529 |
|
|
issue_engine.valid <= (others => (ipb.avail(0) and ipb.avail(1)));
|
530 |
|
|
issue_engine.data <= '0' & (ipb.rdata(1)(17 downto 16) or ipb.rdata(0)(17 downto 16)) &
|
531 |
|
|
'0' & (ipb.rdata(1)(15 downto 00) & ipb.rdata(0)(15 downto 00));
|
532 |
71 |
zero_gravi |
end if;
|
533 |
74 |
zero_gravi |
-- start with HIGH half-word --
|
534 |
|
|
else
|
535 |
|
|
if (CPU_EXTENSION_RISCV_C = true) and (ipb.rdata(1)(1 downto 0) /= "11") then -- compressed
|
536 |
|
|
issue_engine.align_clr <= ipb.avail(1); -- start of next instruction word is 32-bit aligned again
|
537 |
|
|
issue_engine.valid(1) <= ipb.avail(1);
|
538 |
|
|
issue_engine.data <= issue_engine.ci_ill & ipb.rdata(1)(17 downto 16) & '1' & issue_engine.ci_i32;
|
539 |
|
|
else -- unaligned uncompressed
|
540 |
|
|
issue_engine.valid <= (others => (ipb.avail(0) and ipb.avail(1)));
|
541 |
|
|
issue_engine.data <= '0' & (ipb.rdata(0)(17 downto 16) or ipb.rdata(1)(17 downto 16)) &
|
542 |
|
|
'0' & (ipb.rdata(0)(15 downto 00) & ipb.rdata(1)(15 downto 00));
|
543 |
71 |
zero_gravi |
end if;
|
544 |
|
|
end if;
|
545 |
31 |
zero_gravi |
end process issue_engine_fsm_comb;
|
546 |
|
|
|
547 |
74 |
zero_gravi |
-- update IPB FIFOs (read-for-next)? --
|
548 |
|
|
ipb.re <= issue_engine.valid when (execute_engine.state = DISPATCH) else "00";
|
549 |
31 |
zero_gravi |
|
550 |
|
|
|
551 |
74 |
zero_gravi |
-- Compressed Instructions Decoding -------------------------------------------------------
|
552 |
31 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
553 |
|
|
neorv32_cpu_decompressor_inst_true:
|
554 |
|
|
if (CPU_EXTENSION_RISCV_C = true) generate
|
555 |
|
|
neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor
|
556 |
73 |
zero_gravi |
generic map (
|
557 |
74 |
zero_gravi |
FPU_ENABLE => CPU_EXTENSION_RISCV_Zfinx -- floating-point instructions enabled
|
558 |
73 |
zero_gravi |
)
|
559 |
31 |
zero_gravi |
port map (
|
560 |
|
|
-- instruction input --
|
561 |
74 |
zero_gravi |
ci_instr16_i => issue_engine.ci_i16, -- compressed instruction input
|
562 |
31 |
zero_gravi |
-- instruction output --
|
563 |
74 |
zero_gravi |
ci_illegal_o => issue_engine.ci_ill, -- illegal compressed instruction
|
564 |
|
|
ci_instr32_o => issue_engine.ci_i32 -- 32-bit decompressed instruction
|
565 |
31 |
zero_gravi |
);
|
566 |
|
|
end generate;
|
567 |
|
|
|
568 |
|
|
neorv32_cpu_decompressor_inst_false:
|
569 |
|
|
if (CPU_EXTENSION_RISCV_C = false) generate
|
570 |
74 |
zero_gravi |
issue_engine.ci_i32 <= (others => '0');
|
571 |
|
|
issue_engine.ci_ill <= '0';
|
572 |
31 |
zero_gravi |
end generate;
|
573 |
|
|
|
574 |
74 |
zero_gravi |
-- 16-bit instructions: half-word select --
|
575 |
|
|
issue_engine.ci_i16 <= ipb.rdata(0)(15 downto 0) when (issue_engine.align = '0') else ipb.rdata(1)(15 downto 0);
|
576 |
31 |
zero_gravi |
|
577 |
74 |
zero_gravi |
|
578 |
31 |
zero_gravi |
-- ****************************************************************************************************************************
|
579 |
6 |
zero_gravi |
-- Instruction Execution
|
580 |
|
|
-- ****************************************************************************************************************************
|
581 |
|
|
|
582 |
2 |
zero_gravi |
-- Immediate Generator --------------------------------------------------------------------
|
583 |
|
|
-- -------------------------------------------------------------------------------------------
|
584 |
73 |
zero_gravi |
imm_gen: process(clk_i)
|
585 |
37 |
zero_gravi |
variable opcode_v : std_ulogic_vector(6 downto 0);
|
586 |
2 |
zero_gravi |
begin
|
587 |
73 |
zero_gravi |
if rising_edge(clk_i) then
|
588 |
|
|
-- default: I-immediate: ALU-immediate, loads, jump-and-link with register
|
589 |
68 |
zero_gravi |
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
590 |
|
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
591 |
|
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
592 |
|
|
imm_o(00) <= execute_engine.i_reg(20);
|
593 |
|
|
|
594 |
|
|
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
|
595 |
|
|
case opcode_v is -- save some bits here, the two LSBs are always "11" for rv32
|
596 |
|
|
when opcode_store_c => -- S-immediate: store
|
597 |
|
|
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
598 |
|
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
599 |
|
|
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
|
600 |
|
|
imm_o(00) <= execute_engine.i_reg(07);
|
601 |
|
|
when opcode_branch_c => -- B-immediate: conditional branches
|
602 |
|
|
imm_o(31 downto 12) <= (others => execute_engine.i_reg(31)); -- sign extension
|
603 |
|
|
imm_o(11) <= execute_engine.i_reg(07);
|
604 |
|
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
605 |
|
|
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
|
606 |
|
|
imm_o(00) <= '0';
|
607 |
|
|
when opcode_lui_c | opcode_auipc_c => -- U-immediate: lui, auipc
|
608 |
|
|
imm_o(31 downto 20) <= execute_engine.i_reg(31 downto 20);
|
609 |
|
|
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
|
610 |
|
|
imm_o(11 downto 00) <= (others => '0');
|
611 |
|
|
when opcode_jal_c => -- J-immediate: unconditional jumps
|
612 |
|
|
imm_o(31 downto 20) <= (others => execute_engine.i_reg(31)); -- sign extension
|
613 |
|
|
imm_o(19 downto 12) <= execute_engine.i_reg(19 downto 12);
|
614 |
|
|
imm_o(11) <= execute_engine.i_reg(20);
|
615 |
|
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
616 |
|
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
617 |
|
|
imm_o(00) <= '0';
|
618 |
|
|
when opcode_atomic_c => -- atomic memory access and everything else
|
619 |
|
|
if (CPU_EXTENSION_RISCV_A = true) then
|
620 |
|
|
imm_o <= (others => '0'); -- effective address is addr = reg + 0 = reg
|
621 |
|
|
else
|
622 |
|
|
NULL; -- use default
|
623 |
|
|
end if;
|
624 |
|
|
when others => -- I-immediate
|
625 |
|
|
NULL; -- use default
|
626 |
|
|
end case;
|
627 |
2 |
zero_gravi |
end if;
|
628 |
|
|
end process imm_gen;
|
629 |
|
|
|
630 |
|
|
|
631 |
|
|
-- Branch Condition Check -----------------------------------------------------------------
|
632 |
|
|
-- -------------------------------------------------------------------------------------------
|
633 |
6 |
zero_gravi |
branch_check: process(execute_engine.i_reg, cmp_i)
|
634 |
2 |
zero_gravi |
begin
|
635 |
6 |
zero_gravi |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
636 |
2 |
zero_gravi |
when funct3_beq_c => -- branch if equal
|
637 |
47 |
zero_gravi |
execute_engine.branch_taken <= cmp_i(cmp_equal_c);
|
638 |
2 |
zero_gravi |
when funct3_bne_c => -- branch if not equal
|
639 |
47 |
zero_gravi |
execute_engine.branch_taken <= not cmp_i(cmp_equal_c);
|
640 |
2 |
zero_gravi |
when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned)
|
641 |
47 |
zero_gravi |
execute_engine.branch_taken <= cmp_i(cmp_less_c);
|
642 |
71 |
zero_gravi |
when others => -- branch if greater or equal (signed/unsigned), invalid funct3 are checked by illegal instr. logic
|
643 |
47 |
zero_gravi |
execute_engine.branch_taken <= not cmp_i(cmp_less_c);
|
644 |
2 |
zero_gravi |
end case;
|
645 |
|
|
end process branch_check;
|
646 |
|
|
|
647 |
|
|
|
648 |
6 |
zero_gravi |
-- Execute Engine FSM Sync ----------------------------------------------------------------
|
649 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
650 |
56 |
zero_gravi |
execute_engine_fsm_sync: process(rstn_i, clk_i)
|
651 |
2 |
zero_gravi |
begin
|
652 |
|
|
if (rstn_i = '0') then
|
653 |
73 |
zero_gravi |
-- no dedicated reset required --
|
654 |
74 |
zero_gravi |
execute_engine.state_prev <= BRANCHED; -- actual reset value is not relevant
|
655 |
56 |
zero_gravi |
execute_engine.i_reg <= (others => def_rst_val_c);
|
656 |
|
|
execute_engine.is_ci <= def_rst_val_c;
|
657 |
66 |
zero_gravi |
execute_engine.is_ici <= def_rst_val_c;
|
658 |
56 |
zero_gravi |
execute_engine.i_reg_last <= (others => def_rst_val_c);
|
659 |
|
|
execute_engine.next_pc <= (others => def_rst_val_c);
|
660 |
|
|
ctrl <= (others => def_rst_val_c);
|
661 |
73 |
zero_gravi |
-- registers that DO require a specific RESET state --
|
662 |
72 |
zero_gravi |
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 2) & "00"; -- 32-bit aligned!
|
663 |
73 |
zero_gravi |
execute_engine.pc_last <= CPU_BOOT_ADDR(data_width_c-1 downto 2) & "00";
|
664 |
74 |
zero_gravi |
execute_engine.state <= BRANCHED;
|
665 |
72 |
zero_gravi |
execute_engine.sleep <= '0';
|
666 |
|
|
execute_engine.branched <= '1'; -- reset is a branch from "somewhere"
|
667 |
56 |
zero_gravi |
ctrl(ctrl_bus_rd_c) <= '0';
|
668 |
|
|
ctrl(ctrl_bus_wr_c) <= '0';
|
669 |
2 |
zero_gravi |
elsif rising_edge(clk_i) then
|
670 |
39 |
zero_gravi |
-- PC update --
|
671 |
|
|
if (execute_engine.pc_we = '1') then
|
672 |
49 |
zero_gravi |
if (execute_engine.pc_mux_sel = '0') then
|
673 |
58 |
zero_gravi |
execute_engine.pc <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- normal (linear) increment OR trap enter/exit
|
674 |
49 |
zero_gravi |
else
|
675 |
|
|
execute_engine.pc <= alu_add_i(data_width_c-1 downto 1) & '0'; -- jump/taken_branch
|
676 |
|
|
end if;
|
677 |
39 |
zero_gravi |
end if;
|
678 |
68 |
zero_gravi |
|
679 |
73 |
zero_gravi |
-- execute engine arbiter --
|
680 |
68 |
zero_gravi |
execute_engine.state <= execute_engine.state_nxt;
|
681 |
42 |
zero_gravi |
execute_engine.state_prev <= execute_engine.state;
|
682 |
68 |
zero_gravi |
execute_engine.branched <= execute_engine.branched_nxt;
|
683 |
42 |
zero_gravi |
execute_engine.i_reg <= execute_engine.i_reg_nxt;
|
684 |
|
|
execute_engine.is_ci <= execute_engine.is_ci_nxt;
|
685 |
66 |
zero_gravi |
execute_engine.is_ici <= execute_engine.is_ici_nxt;
|
686 |
59 |
zero_gravi |
|
687 |
74 |
zero_gravi |
-- sleep mode --
|
688 |
|
|
if (CPU_EXTENSION_RISCV_DEBUG = true) and ((debug_ctrl.running = '1') or (csr.dcsr_step = '1')) then
|
689 |
|
|
execute_engine.sleep <= '0'; -- no sleep when in debug mode
|
690 |
|
|
else
|
691 |
|
|
execute_engine.sleep <= execute_engine.sleep_nxt;
|
692 |
|
|
end if;
|
693 |
|
|
|
694 |
66 |
zero_gravi |
-- PC & IR of "last executed" instruction for trap handling --
|
695 |
40 |
zero_gravi |
if (execute_engine.state = EXECUTE) then
|
696 |
73 |
zero_gravi |
execute_engine.pc_last <= execute_engine.pc;
|
697 |
39 |
zero_gravi |
execute_engine.i_reg_last <= execute_engine.i_reg;
|
698 |
|
|
end if;
|
699 |
59 |
zero_gravi |
|
700 |
70 |
zero_gravi |
-- next PC logic --
|
701 |
49 |
zero_gravi |
case execute_engine.state is
|
702 |
68 |
zero_gravi |
when TRAP_ENTER => -- ENTERING trap environment
|
703 |
73 |
zero_gravi |
if (trap_ctrl.cause(5) = '1') and (CPU_EXTENSION_RISCV_DEBUG = true) then -- trap cause: debug mode (re-)entry
|
704 |
|
|
execute_engine.next_pc <= CPU_DEBUG_ADDR; -- debug mode enter; start at "parking loop" <normal_entry>
|
705 |
|
|
elsif (debug_ctrl.running = '1') and (CPU_EXTENSION_RISCV_DEBUG = true) then -- any other exception INSIDE debug mode
|
706 |
|
|
execute_engine.next_pc <= std_ulogic_vector(unsigned(CPU_DEBUG_ADDR) + 4); -- start at "parking loop" <exception_entry>
|
707 |
|
|
else -- normal trapping
|
708 |
74 |
zero_gravi |
execute_engine.next_pc <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- trap enter
|
709 |
59 |
zero_gravi |
end if;
|
710 |
68 |
zero_gravi |
when TRAP_EXIT => -- LEAVING trap environment
|
711 |
59 |
zero_gravi |
if (CPU_EXTENSION_RISCV_DEBUG = false) or (debug_ctrl.running = '0') then -- normal end of trap
|
712 |
|
|
execute_engine.next_pc <= csr.mepc(data_width_c-1 downto 1) & '0'; -- trap exit
|
713 |
|
|
else -- DEBUG MODE exiting
|
714 |
|
|
execute_engine.next_pc <= csr.dpc(data_width_c-1 downto 1) & '0'; -- debug mode exit
|
715 |
|
|
end if;
|
716 |
68 |
zero_gravi |
when EXECUTE => -- NORMAL pc increment
|
717 |
59 |
zero_gravi |
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + unsigned(execute_engine.next_pc_inc)); -- next linear PC
|
718 |
|
|
when others =>
|
719 |
|
|
NULL;
|
720 |
49 |
zero_gravi |
end case;
|
721 |
59 |
zero_gravi |
|
722 |
73 |
zero_gravi |
-- main control bus buffer --
|
723 |
6 |
zero_gravi |
ctrl <= ctrl_nxt;
|
724 |
2 |
zero_gravi |
end if;
|
725 |
6 |
zero_gravi |
end process execute_engine_fsm_sync;
|
726 |
2 |
zero_gravi |
|
727 |
56 |
zero_gravi |
|
728 |
49 |
zero_gravi |
-- PC increment for next linear instruction (+2 for compressed instr., +4 otherwise) --
|
729 |
73 |
zero_gravi |
execute_engine.next_pc_inc(data_width_c-1 downto 4) <= (others => '0');
|
730 |
|
|
execute_engine.next_pc_inc(3 downto 0) <= x"4" when ((execute_engine.is_ci = '0') or (CPU_EXTENSION_RISCV_C = false)) else x"2";
|
731 |
41 |
zero_gravi |
|
732 |
20 |
zero_gravi |
-- PC output --
|
733 |
73 |
zero_gravi |
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- current PC
|
734 |
|
|
next_pc_o <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- next PC
|
735 |
6 |
zero_gravi |
|
736 |
20 |
zero_gravi |
|
737 |
6 |
zero_gravi |
-- CPU Control Bus Output -----------------------------------------------------------------
|
738 |
|
|
-- -------------------------------------------------------------------------------------------
|
739 |
73 |
zero_gravi |
ctrl_output: process(ctrl, fetch_engine, trap_ctrl, execute_engine, csr, debug_ctrl)
|
740 |
2 |
zero_gravi |
begin
|
741 |
36 |
zero_gravi |
-- signals from execute engine --
|
742 |
2 |
zero_gravi |
ctrl_o <= ctrl;
|
743 |
65 |
zero_gravi |
-- prevent commits if illegal instruction --
|
744 |
73 |
zero_gravi |
ctrl_o(ctrl_rf_wb_en_c) <= ctrl(ctrl_rf_wb_en_c) and (not trap_ctrl.exc_buf(exc_iillegal_c));
|
745 |
|
|
ctrl_o(ctrl_bus_rd_c) <= ctrl(ctrl_bus_rd_c) and (not trap_ctrl.exc_buf(exc_iillegal_c));
|
746 |
|
|
ctrl_o(ctrl_bus_wr_c) <= ctrl(ctrl_bus_wr_c) and (not trap_ctrl.exc_buf(exc_iillegal_c));
|
747 |
|
|
-- current effective privilege level --
|
748 |
|
|
ctrl_o(ctrl_priv_mode_c) <= csr.privilege_eff;
|
749 |
36 |
zero_gravi |
-- register addresses --
|
750 |
40 |
zero_gravi |
ctrl_o(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) <= execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c);
|
751 |
|
|
ctrl_o(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) <= execute_engine.i_reg(instr_rs2_msb_c downto instr_rs2_lsb_c);
|
752 |
|
|
ctrl_o(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) <= execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c);
|
753 |
69 |
zero_gravi |
-- instruction fetch request --
|
754 |
74 |
zero_gravi |
ctrl_o(ctrl_bus_if_c) <= fetch_engine.bus_if;
|
755 |
47 |
zero_gravi |
-- memory access size / sign --
|
756 |
|
|
ctrl_o(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
|
757 |
|
|
ctrl_o(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size
|
758 |
36 |
zero_gravi |
-- instruction's function blocks (for co-processors) --
|
759 |
44 |
zero_gravi |
ctrl_o(ctrl_ir_opcode7_6_c downto ctrl_ir_opcode7_0_c) <= execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c);
|
760 |
36 |
zero_gravi |
ctrl_o(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_0_c) <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c);
|
761 |
|
|
ctrl_o(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c) <= execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c);
|
762 |
47 |
zero_gravi |
-- cpu status --
|
763 |
64 |
zero_gravi |
ctrl_o(ctrl_sleep_c) <= execute_engine.sleep; -- cpu is in sleep mode
|
764 |
|
|
ctrl_o(ctrl_trap_c) <= trap_ctrl.env_start_ack; -- cpu is starting a trap handler
|
765 |
|
|
ctrl_o(ctrl_debug_running_c) <= debug_ctrl.running; -- cpu is currently in debug mode
|
766 |
61 |
zero_gravi |
-- FPU rounding mode --
|
767 |
|
|
ctrl_o(ctrl_alu_frm2_c downto ctrl_alu_frm0_c) <= csr.frm;
|
768 |
6 |
zero_gravi |
end process ctrl_output;
|
769 |
2 |
zero_gravi |
|
770 |
|
|
|
771 |
44 |
zero_gravi |
-- Decoding Helper Logic ------------------------------------------------------------------
|
772 |
|
|
-- -------------------------------------------------------------------------------------------
|
773 |
|
|
decode_helper: process(execute_engine)
|
774 |
|
|
begin
|
775 |
|
|
-- defaults --
|
776 |
71 |
zero_gravi |
decode_aux.is_a_lr <= '0';
|
777 |
|
|
decode_aux.is_a_sc <= '0';
|
778 |
|
|
decode_aux.is_f_op <= '0';
|
779 |
|
|
decode_aux.is_m_mul <= '0';
|
780 |
|
|
decode_aux.is_m_div <= '0';
|
781 |
|
|
decode_aux.is_b_imm <= '0';
|
782 |
|
|
decode_aux.is_b_reg <= '0';
|
783 |
|
|
decode_aux.rs1_zero <= '0';
|
784 |
|
|
decode_aux.rd_zero <= '0';
|
785 |
44 |
zero_gravi |
|
786 |
|
|
-- is atomic load-reservate/store-conditional? --
|
787 |
68 |
zero_gravi |
if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') then -- valid atomic sub-opcode
|
788 |
71 |
zero_gravi |
decode_aux.is_a_lr <= not execute_engine.i_reg(instr_funct5_lsb_c);
|
789 |
|
|
decode_aux.is_a_sc <= execute_engine.i_reg(instr_funct5_lsb_c);
|
790 |
44 |
zero_gravi |
end if;
|
791 |
|
|
|
792 |
63 |
zero_gravi |
-- is BITMANIP instruction? --
|
793 |
|
|
-- pretty complex as we have to extract this from the ALU/ALUI instruction space --
|
794 |
73 |
zero_gravi |
if (CPU_EXTENSION_RISCV_B = true) then -- BITMANIP implemented at all?
|
795 |
|
|
-- immediate operation --
|
796 |
|
|
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001") and
|
797 |
|
|
(
|
798 |
|
|
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00000") or -- CLZ
|
799 |
|
|
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00001") or -- CTZ
|
800 |
|
|
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00010") or -- CPOP
|
801 |
|
|
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00100") or -- SEXT.B
|
802 |
|
|
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00101") -- SEXT.H
|
803 |
|
|
)
|
804 |
|
|
) or
|
805 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- RORI
|
806 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00111")) or -- ORCB
|
807 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- REV8
|
808 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BCLRI
|
809 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- BEXTI
|
810 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BINVI
|
811 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) then -- BSETI
|
812 |
|
|
decode_aux.is_b_imm <= '1';
|
813 |
|
|
end if;
|
814 |
|
|
-- register operation --
|
815 |
|
|
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c-1 downto instr_funct3_lsb_c) = "01")) or -- ROR / ROL
|
816 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c) = '1')) or -- MIN[U] / MAX[U]
|
817 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100")) or -- ZEXTH
|
818 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BCLR
|
819 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- BEXT
|
820 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BINV
|
821 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BSET
|
822 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- CLMUL
|
823 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "011")) or -- CLMULH
|
824 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010")) or -- CLMULR
|
825 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100000") and
|
826 |
|
|
(
|
827 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "111") or -- ANDN
|
828 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") or -- ORN
|
829 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100") -- XORN
|
830 |
|
|
)
|
831 |
|
|
) or
|
832 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010000") and
|
833 |
|
|
(
|
834 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010") or -- SH1ADD
|
835 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100") or -- SH2ADD
|
836 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") -- SH3ADD
|
837 |
|
|
)
|
838 |
|
|
) then
|
839 |
|
|
decode_aux.is_b_reg <= '1';
|
840 |
|
|
end if;
|
841 |
63 |
zero_gravi |
end if;
|
842 |
|
|
|
843 |
53 |
zero_gravi |
-- floating-point operations (Zfinx) --
|
844 |
73 |
zero_gravi |
if (CPU_EXTENSION_RISCV_Zfinx = true) then -- FPU implemented at all?
|
845 |
|
|
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+3) = "0000")) or -- FADD.S / FSUB.S
|
846 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00010")) or -- FMUL.S
|
847 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- FCLASS.S
|
848 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00100") and (execute_engine.i_reg(instr_funct3_msb_c) = '0')) or -- FSGNJ[N/X].S
|
849 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_msb_c-1) = "00")) or -- FMIN.S / FMAX.S
|
850 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "10100") and (execute_engine.i_reg(instr_funct3_msb_c) = '0')) or -- FEQ.S / FLT.S / FLE.S
|
851 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11010") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) or -- FCVT.S.W*
|
852 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11000") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) then -- FCVT.W*.S
|
853 |
|
|
decode_aux.is_f_op <= '1';
|
854 |
|
|
end if;
|
855 |
52 |
zero_gravi |
end if;
|
856 |
|
|
|
857 |
61 |
zero_gravi |
-- integer MUL (M/Zmmul) / DIV (M) operation --
|
858 |
73 |
zero_gravi |
if (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then
|
859 |
|
|
if ((CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = true)) and (execute_engine.i_reg(instr_funct3_msb_c) = '0') then
|
860 |
|
|
decode_aux.is_m_mul <= '1';
|
861 |
|
|
end if;
|
862 |
|
|
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_funct3_msb_c) = '1') then
|
863 |
|
|
decode_aux.is_m_div <= '1';
|
864 |
|
|
end if;
|
865 |
61 |
zero_gravi |
end if;
|
866 |
68 |
zero_gravi |
|
867 |
73 |
zero_gravi |
-- register/uimm5 checks --
|
868 |
74 |
zero_gravi |
if (execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
|
869 |
|
|
decode_aux.rs1_zero <= '1';
|
870 |
|
|
else
|
871 |
|
|
decode_aux.rs1_zero <= '0';
|
872 |
|
|
end if;
|
873 |
|
|
if (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") then
|
874 |
|
|
decode_aux.rd_zero <= '1';
|
875 |
|
|
else
|
876 |
|
|
decode_aux.rd_zero <= '0';
|
877 |
|
|
end if;
|
878 |
44 |
zero_gravi |
end process decode_helper;
|
879 |
|
|
|
880 |
74 |
zero_gravi |
-- CSR access address --
|
881 |
|
|
csr.addr <= execute_engine.i_reg(instr_imm12_msb_c downto instr_imm12_lsb_c);
|
882 |
44 |
zero_gravi |
|
883 |
74 |
zero_gravi |
|
884 |
6 |
zero_gravi |
-- Execute Engine FSM Comb ----------------------------------------------------------------
|
885 |
|
|
-- -------------------------------------------------------------------------------------------
|
886 |
74 |
zero_gravi |
execute_engine_fsm_comb: process(execute_engine, debug_ctrl, trap_ctrl, decode_aux, fetch_engine, issue_engine,
|
887 |
65 |
zero_gravi |
csr, ctrl, alu_idone_i, bus_d_wait_i, excl_state_i)
|
888 |
2 |
zero_gravi |
begin
|
889 |
|
|
-- arbiter defaults --
|
890 |
29 |
zero_gravi |
execute_engine.state_nxt <= execute_engine.state;
|
891 |
|
|
execute_engine.i_reg_nxt <= execute_engine.i_reg;
|
892 |
|
|
execute_engine.is_ci_nxt <= execute_engine.is_ci;
|
893 |
66 |
zero_gravi |
execute_engine.is_ici_nxt <= '0';
|
894 |
29 |
zero_gravi |
execute_engine.sleep_nxt <= execute_engine.sleep;
|
895 |
49 |
zero_gravi |
execute_engine.branched_nxt <= execute_engine.branched;
|
896 |
39 |
zero_gravi |
--
|
897 |
49 |
zero_gravi |
execute_engine.pc_mux_sel <= '0';
|
898 |
39 |
zero_gravi |
execute_engine.pc_we <= '0';
|
899 |
2 |
zero_gravi |
|
900 |
6 |
zero_gravi |
-- instruction dispatch --
|
901 |
37 |
zero_gravi |
fetch_engine.reset <= '0';
|
902 |
2 |
zero_gravi |
|
903 |
6 |
zero_gravi |
-- trap environment control --
|
904 |
37 |
zero_gravi |
trap_ctrl.env_start_ack <= '0';
|
905 |
|
|
trap_ctrl.env_end <= '0';
|
906 |
6 |
zero_gravi |
|
907 |
59 |
zero_gravi |
-- leave debug mode --
|
908 |
|
|
debug_ctrl.dret <= '0';
|
909 |
|
|
|
910 |
2 |
zero_gravi |
-- exception trigger --
|
911 |
37 |
zero_gravi |
trap_ctrl.instr_be <= '0';
|
912 |
|
|
trap_ctrl.instr_ma <= '0';
|
913 |
|
|
trap_ctrl.env_call <= '0';
|
914 |
|
|
trap_ctrl.break_point <= '0';
|
915 |
2 |
zero_gravi |
|
916 |
6 |
zero_gravi |
-- CSR access --
|
917 |
37 |
zero_gravi |
csr.we_nxt <= '0';
|
918 |
74 |
zero_gravi |
csr.re_nxt <= '0';
|
919 |
6 |
zero_gravi |
|
920 |
39 |
zero_gravi |
-- CONTROL DEFAULTS --
|
921 |
36 |
zero_gravi |
ctrl_nxt <= (others => '0'); -- default: all off
|
922 |
73 |
zero_gravi |
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_add_c; -- default ALU operation: ADD
|
923 |
|
|
ctrl_nxt(ctrl_rf_mux1_c downto ctrl_rf_mux0_c) <= rf_mux_alu_c; -- default RF input: ALU
|
924 |
47 |
zero_gravi |
-- ALU sign control --
|
925 |
6 |
zero_gravi |
if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops
|
926 |
36 |
zero_gravi |
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation? (SLTIU, SLTU)
|
927 |
2 |
zero_gravi |
else -- branches
|
928 |
36 |
zero_gravi |
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches? (BLTU, BGEU)
|
929 |
2 |
zero_gravi |
end if;
|
930 |
68 |
zero_gravi |
-- atomic store-conditional instruction (evaluate lock status) --
|
931 |
73 |
zero_gravi |
ctrl_nxt(ctrl_bus_ch_lock_c) <= decode_aux.is_a_sc;
|
932 |
2 |
zero_gravi |
|
933 |
|
|
|
934 |
6 |
zero_gravi |
-- state machine --
|
935 |
|
|
case execute_engine.state is
|
936 |
2 |
zero_gravi |
|
937 |
37 |
zero_gravi |
when DISPATCH => -- Get new command from instruction issue engine
|
938 |
25 |
zero_gravi |
-- ------------------------------------------------------------
|
939 |
74 |
zero_gravi |
-- PC & IR update --
|
940 |
49 |
zero_gravi |
execute_engine.pc_mux_sel <= '0'; -- linear next PC
|
941 |
74 |
zero_gravi |
execute_engine.i_reg_nxt <= issue_engine.data(31 downto 0);
|
942 |
|
|
execute_engine.is_ci_nxt <= issue_engine.data(32); -- this is a de-compressed instruction
|
943 |
|
|
execute_engine.is_ici_nxt <= issue_engine.data(35); -- illegal compressed instruction
|
944 |
40 |
zero_gravi |
--
|
945 |
74 |
zero_gravi |
if (issue_engine.valid(0) = '1') or (issue_engine.valid(1) = '1') then -- instruction available?
|
946 |
49 |
zero_gravi |
-- PC update --
|
947 |
|
|
execute_engine.branched_nxt <= '0';
|
948 |
|
|
execute_engine.pc_we <= not execute_engine.branched; -- update PC with linear next_pc if there was no actual branch
|
949 |
40 |
zero_gravi |
-- IR update - exceptions --
|
950 |
74 |
zero_gravi |
trap_ctrl.instr_ma <= issue_engine.data(33) and (not bool_to_ulogic_f(CPU_EXTENSION_RISCV_C)); -- misaligned instruction fetch (if C disabled)
|
951 |
|
|
trap_ctrl.instr_be <= issue_engine.data(34); -- bus access fault during instruction fetch
|
952 |
40 |
zero_gravi |
-- any reason to go to trap state? --
|
953 |
68 |
zero_gravi |
if (execute_engine.sleep = '1') or -- enter sleep state
|
954 |
72 |
zero_gravi |
(trap_ctrl.exc_fire = '1') or -- exception during LAST instruction (e.g. illegal instruction)
|
955 |
61 |
zero_gravi |
(trap_ctrl.env_start = '1') or -- pending trap (IRQ or exception)
|
956 |
74 |
zero_gravi |
((issue_engine.data(33) = '1') and (CPU_EXTENSION_RISCV_C = false)) or -- misaligned instruction fetch address (if C disabled)
|
957 |
|
|
(issue_engine.data(34) = '1') then -- bus access fault during instruction fetch
|
958 |
49 |
zero_gravi |
execute_engine.state_nxt <= TRAP_ENTER;
|
959 |
13 |
zero_gravi |
else
|
960 |
14 |
zero_gravi |
execute_engine.state_nxt <= EXECUTE;
|
961 |
13 |
zero_gravi |
end if;
|
962 |
|
|
end if;
|
963 |
2 |
zero_gravi |
|
964 |
39 |
zero_gravi |
|
965 |
74 |
zero_gravi |
when TRAP_ENTER => -- Start trap environment - get trap vector, stay here for sleep mode
|
966 |
2 |
zero_gravi |
-- ------------------------------------------------------------
|
967 |
34 |
zero_gravi |
if (trap_ctrl.env_start = '1') then -- trap triggered?
|
968 |
61 |
zero_gravi |
trap_ctrl.env_start_ack <= '1';
|
969 |
|
|
execute_engine.state_nxt <= TRAP_EXECUTE;
|
970 |
2 |
zero_gravi |
end if;
|
971 |
|
|
|
972 |
68 |
zero_gravi |
|
973 |
63 |
zero_gravi |
when TRAP_EXIT => -- Return from trap environment - get xEPC
|
974 |
49 |
zero_gravi |
-- ------------------------------------------------------------
|
975 |
|
|
trap_ctrl.env_end <= '1';
|
976 |
|
|
execute_engine.state_nxt <= TRAP_EXECUTE;
|
977 |
39 |
zero_gravi |
|
978 |
68 |
zero_gravi |
|
979 |
74 |
zero_gravi |
when TRAP_EXECUTE => -- Process trap environment
|
980 |
49 |
zero_gravi |
-- ------------------------------------------------------------
|
981 |
74 |
zero_gravi |
execute_engine.pc_mux_sel <= '0'; -- next_PC (or xEPC / trap vector)
|
982 |
49 |
zero_gravi |
fetch_engine.reset <= '1';
|
983 |
|
|
execute_engine.pc_we <= '1';
|
984 |
|
|
execute_engine.sleep_nxt <= '0'; -- disable sleep mode
|
985 |
74 |
zero_gravi |
execute_engine.state_nxt <= BRANCHED;
|
986 |
49 |
zero_gravi |
|
987 |
|
|
|
988 |
60 |
zero_gravi |
when EXECUTE => -- Decode and execute instruction (control has to be here for exactly 1 cycle in any case!)
|
989 |
2 |
zero_gravi |
-- ------------------------------------------------------------
|
990 |
74 |
zero_gravi |
case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is
|
991 |
2 |
zero_gravi |
|
992 |
60 |
zero_gravi |
when opcode_alu_c | opcode_alui_c => -- (register/immediate) ALU operation
|
993 |
2 |
zero_gravi |
-- ------------------------------------------------------------
|
994 |
68 |
zero_gravi |
ctrl_nxt(ctrl_alu_opb_mux_c) <= not execute_engine.i_reg(instr_opcode_msb_c-1); -- use IMM as ALU.OPB for immediate operations
|
995 |
25 |
zero_gravi |
|
996 |
68 |
zero_gravi |
-- ALU core operation --
|
997 |
39 |
zero_gravi |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU.logic operation (re-coding)
|
998 |
68 |
zero_gravi |
when funct3_subadd_c => -- ADD(I)/SUB
|
999 |
|
|
if ((execute_engine.i_reg(instr_opcode_msb_c-1) = '1') and (execute_engine.i_reg(instr_funct7_msb_c-1) = '1')) then -- not an immediate op and funct7.6 set => SUB
|
1000 |
|
|
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_sub_c;
|
1001 |
|
|
else
|
1002 |
|
|
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_add_c;
|
1003 |
|
|
end if;
|
1004 |
|
|
when funct3_slt_c | funct3_sltu_c => -- SLT(I), SLTU(I)
|
1005 |
|
|
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_slt_c;
|
1006 |
|
|
when funct3_xor_c => -- XOR(I)
|
1007 |
|
|
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_xor_c;
|
1008 |
|
|
when funct3_or_c => -- OR(I)
|
1009 |
|
|
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_or_c;
|
1010 |
|
|
when others => -- AND(I), multi-cycle / co-processor operations
|
1011 |
|
|
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_and_c;
|
1012 |
39 |
zero_gravi |
end case;
|
1013 |
|
|
|
1014 |
71 |
zero_gravi |
-- co-processor MULDIV operation (multi-cycle) --
|
1015 |
61 |
zero_gravi |
if ((CPU_EXTENSION_RISCV_M = true) and ((decode_aux.is_m_mul = '1') or (decode_aux.is_m_div = '1'))) or -- MUL/DIV
|
1016 |
|
|
((CPU_EXTENSION_RISCV_Zmmul = true) and (decode_aux.is_m_mul = '1')) then -- MUL
|
1017 |
74 |
zero_gravi |
ctrl_nxt(ctrl_cp_trig7_c downto ctrl_cp_trig0_c) <= cp_sel_muldiv_c; -- trigger MULDIV CP
|
1018 |
73 |
zero_gravi |
execute_engine.state_nxt <= ALU_WAIT;
|
1019 |
71 |
zero_gravi |
-- co-processor BIT-MANIPULATION operation (multi-cycle) --
|
1020 |
66 |
zero_gravi |
elsif (CPU_EXTENSION_RISCV_B = true) and
|
1021 |
71 |
zero_gravi |
(((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_b_reg = '1')) or -- register operation
|
1022 |
|
|
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_b_imm = '1'))) then -- immediate operation
|
1023 |
74 |
zero_gravi |
ctrl_nxt(ctrl_cp_trig7_c downto ctrl_cp_trig0_c) <= cp_sel_bitmanip_c; -- trigger BITMANIP CP
|
1024 |
73 |
zero_gravi |
execute_engine.state_nxt <= ALU_WAIT;
|
1025 |
71 |
zero_gravi |
-- co-processor SHIFT operation (multi-cycle) --
|
1026 |
68 |
zero_gravi |
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or
|
1027 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) then
|
1028 |
74 |
zero_gravi |
ctrl_nxt(ctrl_cp_trig7_c downto ctrl_cp_trig0_c) <= cp_sel_shifter_c; -- trigger SHIFTER CP
|
1029 |
73 |
zero_gravi |
execute_engine.state_nxt <= ALU_WAIT;
|
1030 |
69 |
zero_gravi |
-- ALU CORE operation (single-cycle) --
|
1031 |
61 |
zero_gravi |
else
|
1032 |
73 |
zero_gravi |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
1033 |
|
|
execute_engine.state_nxt <= DISPATCH;
|
1034 |
39 |
zero_gravi |
end if;
|
1035 |
|
|
|
1036 |
2 |
zero_gravi |
|
1037 |
25 |
zero_gravi |
when opcode_lui_c | opcode_auipc_c => -- load upper immediate / add upper immediate to PC
|
1038 |
2 |
zero_gravi |
-- ------------------------------------------------------------
|
1039 |
27 |
zero_gravi |
ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- ALU.OPA = PC (for AUIPC only)
|
1040 |
|
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB
|
1041 |
25 |
zero_gravi |
if (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_lui_c(5)) then -- LUI
|
1042 |
68 |
zero_gravi |
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_movb_c; -- actual ALU operation = MOVB
|
1043 |
27 |
zero_gravi |
else -- AUIPC
|
1044 |
68 |
zero_gravi |
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_add_c; -- actual ALU operation = ADD
|
1045 |
2 |
zero_gravi |
end if;
|
1046 |
68 |
zero_gravi |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
1047 |
|
|
execute_engine.state_nxt <= DISPATCH;
|
1048 |
2 |
zero_gravi |
|
1049 |
68 |
zero_gravi |
|
1050 |
53 |
zero_gravi |
when opcode_load_c | opcode_store_c | opcode_atomic_c => -- load/store / atomic memory access
|
1051 |
2 |
zero_gravi |
-- ------------------------------------------------------------
|
1052 |
66 |
zero_gravi |
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB
|
1053 |
|
|
ctrl_nxt(ctrl_bus_mo_we_c) <= '1'; -- write to MAR and MDO (MDO only relevant for store)
|
1054 |
68 |
zero_gravi |
execute_engine.state_nxt <= LOADSTORE_0;
|
1055 |
2 |
zero_gravi |
|
1056 |
68 |
zero_gravi |
|
1057 |
29 |
zero_gravi |
when opcode_branch_c | opcode_jal_c | opcode_jalr_c => -- branch / jump and link (with register)
|
1058 |
2 |
zero_gravi |
-- ------------------------------------------------------------
|
1059 |
29 |
zero_gravi |
if (execute_engine.i_reg(instr_opcode_lsb_c+3 downto instr_opcode_lsb_c+2) = opcode_jalr_c(3 downto 2)) then -- JALR
|
1060 |
|
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '0'; -- use RS1 as ALU.OPA (branch target address base)
|
1061 |
49 |
zero_gravi |
else -- JAL
|
1062 |
29 |
zero_gravi |
ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- use PC as ALU.OPA (branch target address base)
|
1063 |
2 |
zero_gravi |
end if;
|
1064 |
29 |
zero_gravi |
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (branch target address offset)
|
1065 |
49 |
zero_gravi |
execute_engine.state_nxt <= BRANCH;
|
1066 |
2 |
zero_gravi |
|
1067 |
68 |
zero_gravi |
|
1068 |
8 |
zero_gravi |
when opcode_fence_c => -- fence operations
|
1069 |
|
|
-- ------------------------------------------------------------
|
1070 |
74 |
zero_gravi |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c+1) = funct3_fence_c(2 downto 1)) then -- FENCE / FENCE.I
|
1071 |
|
|
ctrl_nxt(ctrl_bus_fence_c) <= not execute_engine.i_reg(instr_funct3_lsb_c); -- FENCE
|
1072 |
|
|
ctrl_nxt(ctrl_bus_fencei_c) <= execute_engine.i_reg(instr_funct3_lsb_c) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- FENCE.I
|
1073 |
66 |
zero_gravi |
end if;
|
1074 |
74 |
zero_gravi |
execute_engine.state_nxt <= TRAP_EXECUTE; -- use TRAP_EXECUTE to "modify" PC (PC <= PC)
|
1075 |
8 |
zero_gravi |
|
1076 |
68 |
zero_gravi |
|
1077 |
53 |
zero_gravi |
when opcode_fop_c => -- floating-point operations
|
1078 |
52 |
zero_gravi |
-- ------------------------------------------------------------
|
1079 |
68 |
zero_gravi |
if (CPU_EXTENSION_RISCV_Zfinx = true) then
|
1080 |
74 |
zero_gravi |
ctrl_nxt(ctrl_cp_trig7_c downto ctrl_cp_trig0_c) <= cp_sel_fpu_c; -- trigger FPU CP
|
1081 |
68 |
zero_gravi |
execute_engine.state_nxt <= ALU_WAIT;
|
1082 |
53 |
zero_gravi |
else
|
1083 |
73 |
zero_gravi |
execute_engine.state_nxt <= DISPATCH;
|
1084 |
52 |
zero_gravi |
end if;
|
1085 |
|
|
|
1086 |
68 |
zero_gravi |
|
1087 |
72 |
zero_gravi |
when opcode_cust0_c => -- CFU: custom RISC-V instructions (CUSTOM0 OPCODE space)
|
1088 |
|
|
-- ------------------------------------------------------------
|
1089 |
|
|
if (CPU_EXTENSION_RISCV_Zxcfu = true) then
|
1090 |
74 |
zero_gravi |
ctrl_nxt(ctrl_cp_trig7_c downto ctrl_cp_trig0_c) <= cp_sel_cfu_c; -- trigger CFU CP
|
1091 |
72 |
zero_gravi |
execute_engine.state_nxt <= ALU_WAIT;
|
1092 |
|
|
else
|
1093 |
73 |
zero_gravi |
execute_engine.state_nxt <= DISPATCH;
|
1094 |
72 |
zero_gravi |
end if;
|
1095 |
|
|
|
1096 |
|
|
|
1097 |
74 |
zero_gravi |
when opcode_system_c => -- environment/csr access
|
1098 |
2 |
zero_gravi |
-- ------------------------------------------------------------
|
1099 |
74 |
zero_gravi |
csr.re_nxt <= '1'; -- always read CSR, only relevant for CSR access
|
1100 |
71 |
zero_gravi |
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
1101 |
74 |
zero_gravi |
execute_engine.state_nxt <= SYSTEM;
|
1102 |
71 |
zero_gravi |
else
|
1103 |
73 |
zero_gravi |
execute_engine.state_nxt <= DISPATCH;
|
1104 |
71 |
zero_gravi |
end if;
|
1105 |
2 |
zero_gravi |
|
1106 |
|
|
|
1107 |
74 |
zero_gravi |
when others => -- illegal opcode
|
1108 |
|
|
-- ------------------------------------------------------------
|
1109 |
|
|
execute_engine.state_nxt <= DISPATCH;
|
1110 |
39 |
zero_gravi |
|
1111 |
74 |
zero_gravi |
end case; -- /EXECUTE
|
1112 |
39 |
zero_gravi |
|
1113 |
|
|
|
1114 |
74 |
zero_gravi |
when SYSTEM => -- system environment operation
|
1115 |
39 |
zero_gravi |
-- ------------------------------------------------------------
|
1116 |
74 |
zero_gravi |
ctrl_nxt(ctrl_rf_mux1_c downto ctrl_rf_mux0_c) <= rf_mux_csr_c; -- only relevant for CSR access
|
1117 |
|
|
execute_engine.state_nxt <= DISPATCH; -- default
|
1118 |
|
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) and -- ENVIRONMENT
|
1119 |
|
|
(trap_ctrl.exc_buf(exc_iillegal_c) = '0') then -- and NOT already identified as illegal instruction
|
1120 |
|
|
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
|
1121 |
|
|
when funct12_ecall_c => trap_ctrl.env_call <= '1'; -- ecall
|
1122 |
|
|
when funct12_ebreak_c => trap_ctrl.break_point <= '1'; -- ebreak
|
1123 |
|
|
when funct12_mret_c => execute_engine.state_nxt <= TRAP_EXIT; -- mret
|
1124 |
|
|
when funct12_dret_c => execute_engine.state_nxt <= TRAP_EXIT; debug_ctrl.dret <= '1'; -- dret
|
1125 |
|
|
when others => execute_engine.sleep_nxt <= '1'; -- "funct12_wfi_c" - wfi/sleep
|
1126 |
|
|
end case;
|
1127 |
|
|
else -- CSR ACCESS - there will be no state change if illegal instruction
|
1128 |
|
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or -- CSRRW: always write CSR
|
1129 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) or -- CSRRWI: always write CSR
|
1130 |
|
|
(decode_aux.rs1_zero = '0') then -- CSRR(S/C)(I): write CSR if rs1/imm5 is NOT zero
|
1131 |
|
|
csr.we_nxt <= '1';
|
1132 |
|
|
end if;
|
1133 |
|
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
1134 |
68 |
zero_gravi |
end if;
|
1135 |
2 |
zero_gravi |
|
1136 |
39 |
zero_gravi |
|
1137 |
73 |
zero_gravi |
when ALU_WAIT => -- wait for multi-cycle ALU operation (ALU co-processor) to finish
|
1138 |
2 |
zero_gravi |
-- ------------------------------------------------------------
|
1139 |
73 |
zero_gravi |
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_cp_c;
|
1140 |
71 |
zero_gravi |
-- wait for completion or abort on illegal instruction exception (the co-processor will also terminate operations)
|
1141 |
73 |
zero_gravi |
if (alu_idone_i = '1') or (trap_ctrl.exc_buf(exc_iillegal_c) = '1') then
|
1142 |
72 |
zero_gravi |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (won't happen in case of an illegal instruction)
|
1143 |
56 |
zero_gravi |
execute_engine.state_nxt <= DISPATCH;
|
1144 |
2 |
zero_gravi |
end if;
|
1145 |
|
|
|
1146 |
39 |
zero_gravi |
|
1147 |
74 |
zero_gravi |
when BRANCH => -- update PC on taken branches and jumps
|
1148 |
6 |
zero_gravi |
-- ------------------------------------------------------------
|
1149 |
39 |
zero_gravi |
-- get and store return address (only relevant for jump-and-link operations) --
|
1150 |
73 |
zero_gravi |
ctrl_nxt(ctrl_rf_mux1_c downto ctrl_rf_mux0_c) <= rf_mux_npc_c; -- next PC
|
1151 |
68 |
zero_gravi |
ctrl_nxt(ctrl_rf_wb_en_c) <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- valid RF write-back? (is jump-and-link?)
|
1152 |
39 |
zero_gravi |
-- destination address --
|
1153 |
68 |
zero_gravi |
execute_engine.pc_mux_sel <= '1'; -- PC <= alu.add = branch/jump destination
|
1154 |
74 |
zero_gravi |
execute_engine.pc_we <= '1'; -- update PC with destination; will be overridden again in DISPATCH if branch not taken
|
1155 |
40 |
zero_gravi |
if (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') or (execute_engine.branch_taken = '1') then -- JAL/JALR or taken branch
|
1156 |
74 |
zero_gravi |
fetch_engine.reset <= '1'; -- reset instruction fetch starting at modified PC
|
1157 |
|
|
execute_engine.state_nxt <= BRANCHED;
|
1158 |
|
|
else
|
1159 |
|
|
execute_engine.state_nxt <= DISPATCH;
|
1160 |
6 |
zero_gravi |
end if;
|
1161 |
|
|
|
1162 |
39 |
zero_gravi |
|
1163 |
74 |
zero_gravi |
when BRANCHED => -- delay cycle to wait for reset of pipeline front-end
|
1164 |
|
|
-- ------------------------------------------------------------
|
1165 |
|
|
execute_engine.branched_nxt <= '1'; -- this is an actual branch
|
1166 |
|
|
execute_engine.state_nxt <= DISPATCH;
|
1167 |
|
|
|
1168 |
|
|
|
1169 |
12 |
zero_gravi |
when LOADSTORE_0 => -- trigger memory request
|
1170 |
6 |
zero_gravi |
-- ------------------------------------------------------------
|
1171 |
71 |
zero_gravi |
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_a_lr = '1') then -- normal load or atomic load-reservate
|
1172 |
74 |
zero_gravi |
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- bus read request
|
1173 |
|
|
elsif (decode_aux.is_a_sc = '0') or (excl_state_i = '1') then -- normal store request or atomic store-conditional with lock still OK
|
1174 |
|
|
ctrl_nxt(ctrl_bus_wr_c) <= '1'; -- bus write request
|
1175 |
12 |
zero_gravi |
end if;
|
1176 |
74 |
zero_gravi |
ctrl_nxt(ctrl_bus_lock_c) <= decode_aux.is_a_lr; -- atomic load-reservate: set lock
|
1177 |
|
|
execute_engine.state_nxt <= LOADSTORE_1;
|
1178 |
6 |
zero_gravi |
|
1179 |
39 |
zero_gravi |
|
1180 |
61 |
zero_gravi |
when LOADSTORE_1 => -- memory access latency
|
1181 |
6 |
zero_gravi |
-- ------------------------------------------------------------
|
1182 |
74 |
zero_gravi |
ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- write input data to MDI (only relevant for load and SC.W operations)
|
1183 |
57 |
zero_gravi |
execute_engine.state_nxt <= LOADSTORE_2;
|
1184 |
6 |
zero_gravi |
|
1185 |
39 |
zero_gravi |
|
1186 |
12 |
zero_gravi |
when LOADSTORE_2 => -- wait for bus transaction to finish
|
1187 |
6 |
zero_gravi |
-- ------------------------------------------------------------
|
1188 |
74 |
zero_gravi |
ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for load and SC.W operations)
|
1189 |
73 |
zero_gravi |
ctrl_nxt(ctrl_rf_mux1_c downto ctrl_rf_mux0_c) <= rf_mux_mem_c; -- memory read data
|
1190 |
68 |
zero_gravi |
-- wait for memory response --
|
1191 |
|
|
if (trap_ctrl.env_start = '1') and (trap_ctrl.cause(6 downto 5) = "00") then -- abort if SYNC EXCEPTION (from bus or illegal cmd) / no IRQs and NOT DEBUG-MODE-related
|
1192 |
|
|
execute_engine.state_nxt <= DISPATCH;
|
1193 |
26 |
zero_gravi |
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
|
1194 |
57 |
zero_gravi |
-- data write-back --
|
1195 |
|
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or -- normal load
|
1196 |
71 |
zero_gravi |
(decode_aux.is_a_lr = '1') or -- atomic load-reservate
|
1197 |
|
|
(decode_aux.is_a_sc = '1') then -- atomic store-conditional
|
1198 |
53 |
zero_gravi |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1';
|
1199 |
6 |
zero_gravi |
end if;
|
1200 |
61 |
zero_gravi |
-- remove atomic lock if this is NOT the LR.W instruction used to SET the lock --
|
1201 |
71 |
zero_gravi |
if (decode_aux.is_a_lr = '0') then -- execute and evaluate atomic store-conditional
|
1202 |
61 |
zero_gravi |
ctrl_nxt(ctrl_bus_de_lock_c) <= '1';
|
1203 |
|
|
end if;
|
1204 |
6 |
zero_gravi |
execute_engine.state_nxt <= DISPATCH;
|
1205 |
|
|
end if;
|
1206 |
|
|
|
1207 |
39 |
zero_gravi |
|
1208 |
2 |
zero_gravi |
when others => -- undefined
|
1209 |
|
|
-- ------------------------------------------------------------
|
1210 |
73 |
zero_gravi |
execute_engine.state_nxt <= DISPATCH;
|
1211 |
2 |
zero_gravi |
|
1212 |
|
|
end case;
|
1213 |
6 |
zero_gravi |
end process execute_engine_fsm_comb;
|
1214 |
2 |
zero_gravi |
|
1215 |
|
|
|
1216 |
15 |
zero_gravi |
-- ****************************************************************************************************************************
|
1217 |
71 |
zero_gravi |
-- Illegal Instruction and CSR Access Check
|
1218 |
15 |
zero_gravi |
-- ****************************************************************************************************************************
|
1219 |
|
|
|
1220 |
49 |
zero_gravi |
-- CSR Access Check -----------------------------------------------------------------------
|
1221 |
15 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
1222 |
68 |
zero_gravi |
csr_access_check: process(execute_engine.i_reg, decode_aux, csr, debug_ctrl)
|
1223 |
|
|
variable csr_wacc_v : std_ulogic; -- actual CSR write
|
1224 |
15 |
zero_gravi |
begin
|
1225 |
58 |
zero_gravi |
-- is this CSR instruction really going to write to a CSR? --
|
1226 |
73 |
zero_gravi |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or -- always write CSR
|
1227 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) or -- always write CSR
|
1228 |
|
|
(decode_aux.rs1_zero = '0') then -- clear/set: write CSR if rs1/imm5 is NOT zero
|
1229 |
|
|
csr_wacc_v := '1';
|
1230 |
|
|
else
|
1231 |
|
|
csr_wacc_v := '0';
|
1232 |
30 |
zero_gravi |
end if;
|
1233 |
|
|
|
1234 |
15 |
zero_gravi |
-- check CSR access --
|
1235 |
73 |
zero_gravi |
csr_acc_valid <= '0'; -- default: invalid access
|
1236 |
41 |
zero_gravi |
case csr.addr is
|
1237 |
56 |
zero_gravi |
|
1238 |
58 |
zero_gravi |
-- floating-point CSRs --
|
1239 |
56 |
zero_gravi |
when csr_fflags_c | csr_frm_c | csr_fcsr_c =>
|
1240 |
65 |
zero_gravi |
csr_acc_valid <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- full access for everyone if FPU implemented
|
1241 |
56 |
zero_gravi |
|
1242 |
68 |
zero_gravi |
-- machine trap setup/handling & counters --
|
1243 |
65 |
zero_gravi |
when csr_mstatus_c | csr_mstatush_c | csr_misa_c | csr_mie_c | csr_mtvec_c | csr_mscratch_c | csr_mepc_c | csr_mcause_c | csr_mip_c | csr_mtval_c |
|
1244 |
|
|
csr_mcycle_c | csr_mcycleh_c | csr_minstret_c | csr_minstreth_c | csr_mcountinhibit_c =>
|
1245 |
69 |
zero_gravi |
-- NOTE: MISA and MTVAL are read-only in the NEORV32 but we do not cause an exception here for compatibility.
|
1246 |
65 |
zero_gravi |
-- Machine-level code should read-back those CSRs after writing them to realize they are read-only.
|
1247 |
73 |
zero_gravi |
csr_acc_valid <= csr.privilege_eff; -- M-mode only
|
1248 |
56 |
zero_gravi |
|
1249 |
72 |
zero_gravi |
-- machine information registers & NEORV32-specific registers, read-only --
|
1250 |
|
|
when csr_mvendorid_c | csr_marchid_c | csr_mimpid_c | csr_mhartid_c | csr_mconfigptr_c | csr_mxisa_c =>
|
1251 |
73 |
zero_gravi |
csr_acc_valid <= (not csr_wacc_v) and csr.privilege_eff; -- M-mode only, read-only
|
1252 |
65 |
zero_gravi |
|
1253 |
68 |
zero_gravi |
-- user-mode registers --
|
1254 |
|
|
when csr_mcounteren_c | csr_menvcfg_c | csr_menvcfgh_c =>
|
1255 |
73 |
zero_gravi |
csr_acc_valid <= csr.privilege_eff and bool_to_ulogic_f(CPU_EXTENSION_RISCV_U);
|
1256 |
64 |
zero_gravi |
|
1257 |
63 |
zero_gravi |
-- physical memory protection (PMP) --
|
1258 |
|
|
when csr_pmpaddr0_c | csr_pmpaddr1_c | csr_pmpaddr2_c | csr_pmpaddr3_c | csr_pmpaddr4_c | csr_pmpaddr5_c | csr_pmpaddr6_c | csr_pmpaddr7_c | -- address
|
1259 |
42 |
zero_gravi |
csr_pmpaddr8_c | csr_pmpaddr9_c | csr_pmpaddr10_c | csr_pmpaddr11_c | csr_pmpaddr12_c | csr_pmpaddr13_c | csr_pmpaddr14_c | csr_pmpaddr15_c |
|
1260 |
73 |
zero_gravi |
csr_pmpcfg0_c | csr_pmpcfg1_c | csr_pmpcfg2_c | csr_pmpcfg3_c => -- configuration
|
1261 |
|
|
csr_acc_valid <= csr.privilege_eff and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS > 0)); -- M-mode only
|
1262 |
56 |
zero_gravi |
|
1263 |
73 |
zero_gravi |
-- machine hardware performance monitors (MHPM) --
|
1264 |
61 |
zero_gravi |
when csr_mhpmcounter3_c | csr_mhpmcounter4_c | csr_mhpmcounter5_c | csr_mhpmcounter6_c | csr_mhpmcounter7_c | csr_mhpmcounter8_c | -- counter LOW
|
1265 |
56 |
zero_gravi |
csr_mhpmcounter9_c | csr_mhpmcounter10_c | csr_mhpmcounter11_c | csr_mhpmcounter12_c | csr_mhpmcounter13_c | csr_mhpmcounter14_c |
|
1266 |
|
|
csr_mhpmcounter15_c | csr_mhpmcounter16_c | csr_mhpmcounter17_c | csr_mhpmcounter18_c | csr_mhpmcounter19_c | csr_mhpmcounter20_c |
|
1267 |
|
|
csr_mhpmcounter21_c | csr_mhpmcounter22_c | csr_mhpmcounter23_c | csr_mhpmcounter24_c | csr_mhpmcounter25_c | csr_mhpmcounter26_c |
|
1268 |
|
|
csr_mhpmcounter27_c | csr_mhpmcounter28_c | csr_mhpmcounter29_c | csr_mhpmcounter30_c | csr_mhpmcounter31_c |
|
1269 |
61 |
zero_gravi |
csr_mhpmcounter3h_c | csr_mhpmcounter4h_c | csr_mhpmcounter5h_c | csr_mhpmcounter6h_c | csr_mhpmcounter7h_c | csr_mhpmcounter8h_c | -- counter HIGH
|
1270 |
56 |
zero_gravi |
csr_mhpmcounter9h_c | csr_mhpmcounter10h_c | csr_mhpmcounter11h_c | csr_mhpmcounter12h_c | csr_mhpmcounter13h_c | csr_mhpmcounter14h_c |
|
1271 |
|
|
csr_mhpmcounter15h_c | csr_mhpmcounter16h_c | csr_mhpmcounter17h_c | csr_mhpmcounter18h_c | csr_mhpmcounter19h_c | csr_mhpmcounter20h_c |
|
1272 |
|
|
csr_mhpmcounter21h_c | csr_mhpmcounter22h_c | csr_mhpmcounter23h_c | csr_mhpmcounter24h_c | csr_mhpmcounter25h_c | csr_mhpmcounter26h_c |
|
1273 |
61 |
zero_gravi |
csr_mhpmcounter27h_c | csr_mhpmcounter28h_c | csr_mhpmcounter29h_c | csr_mhpmcounter30h_c | csr_mhpmcounter31h_c |
|
1274 |
|
|
csr_mhpmevent3_c | csr_mhpmevent4_c | csr_mhpmevent5_c | csr_mhpmevent6_c | csr_mhpmevent7_c | csr_mhpmevent8_c | -- event configuration
|
1275 |
|
|
csr_mhpmevent9_c | csr_mhpmevent10_c | csr_mhpmevent11_c | csr_mhpmevent12_c | csr_mhpmevent13_c | csr_mhpmevent14_c |
|
1276 |
|
|
csr_mhpmevent15_c | csr_mhpmevent16_c | csr_mhpmevent17_c | csr_mhpmevent18_c | csr_mhpmevent19_c | csr_mhpmevent20_c |
|
1277 |
|
|
csr_mhpmevent21_c | csr_mhpmevent22_c | csr_mhpmevent23_c | csr_mhpmevent24_c | csr_mhpmevent25_c | csr_mhpmevent26_c |
|
1278 |
|
|
csr_mhpmevent27_c | csr_mhpmevent28_c | csr_mhpmevent29_c | csr_mhpmevent30_c | csr_mhpmevent31_c =>
|
1279 |
73 |
zero_gravi |
csr_acc_valid <= csr.privilege_eff and bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zihpm); -- M-mode only
|
1280 |
56 |
zero_gravi |
|
1281 |
73 |
zero_gravi |
-- -- user hardware performance monitors (HPM) --
|
1282 |
|
|
-- when csr_hpmcounter3_c | csr_hpmcounter4_c | csr_hpmcounter5_c | csr_hpmcounter6_c | csr_hpmcounter7_c | csr_hpmcounter8_c | -- counter LOW
|
1283 |
|
|
-- csr_hpmcounter9_c | csr_hpmcounter10_c | csr_hpmcounter11_c | csr_hpmcounter12_c | csr_hpmcounter13_c | csr_hpmcounter14_c |
|
1284 |
|
|
-- csr_hpmcounter15_c | csr_hpmcounter16_c | csr_hpmcounter17_c | csr_hpmcounter18_c | csr_hpmcounter19_c | csr_hpmcounter20_c |
|
1285 |
|
|
-- csr_hpmcounter21_c | csr_hpmcounter22_c | csr_hpmcounter23_c | csr_hpmcounter24_c | csr_hpmcounter25_c | csr_hpmcounter26_c |
|
1286 |
|
|
-- csr_hpmcounter27_c | csr_hpmcounter28_c | csr_hpmcounter29_c | csr_hpmcounter30_c | csr_hpmcounter31_c |
|
1287 |
|
|
-- csr_hpmcounter3h_c | csr_hpmcounter4h_c | csr_hpmcounter5h_c | csr_hpmcounter6h_c | csr_hpmcounter7h_c | csr_hpmcounter8h_c | -- counter HIGH
|
1288 |
|
|
-- csr_hpmcounter9h_c | csr_hpmcounter10h_c | csr_hpmcounter11h_c | csr_hpmcounter12h_c | csr_hpmcounter13h_c | csr_hpmcounter14h_c |
|
1289 |
|
|
-- csr_hpmcounter15h_c | csr_hpmcounter16h_c | csr_hpmcounter17h_c | csr_hpmcounter18h_c | csr_hpmcounter19h_c | csr_hpmcounter20h_c |
|
1290 |
|
|
-- csr_hpmcounter21h_c | csr_hpmcounter22h_c | csr_hpmcounter23h_c | csr_hpmcounter24h_c | csr_hpmcounter25h_c | csr_hpmcounter26h_c |
|
1291 |
|
|
-- csr_hpmcounter27h_c | csr_hpmcounter28h_c | csr_hpmcounter29h_c | csr_hpmcounter30h_c | csr_hpmcounter31h_c =>
|
1292 |
|
|
-- csr_acc_valid <= '0'; -- >>> NOT IMPLEMENTED <<<
|
1293 |
|
|
|
1294 |
68 |
zero_gravi |
-- user-level counters/timers (read-only) --
|
1295 |
73 |
zero_gravi |
when csr_cycle_c | csr_cycleh_c | csr_time_c | csr_timeh_c | csr_instret_c | csr_instreth_c =>
|
1296 |
65 |
zero_gravi |
case csr.addr(1 downto 0) is
|
1297 |
73 |
zero_gravi |
when "00" => csr_acc_valid <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr) and (not csr_wacc_v) and (csr.privilege_eff or csr.mcounteren_cy); -- cyle[h]: M-mode, U-mode if authorized, implemented at all, read-only
|
1298 |
|
|
when "01" => csr_acc_valid <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr) and (not csr_wacc_v) and (csr.privilege_eff or csr.mcounteren_tm); -- time[h]: M-mode, U-mode if authorized, implemented at all, read-only
|
1299 |
|
|
when "10" => csr_acc_valid <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr) and (not csr_wacc_v) and (csr.privilege_eff or csr.mcounteren_ir); -- instret[h]: M-mode, U-mode if authorized, implemented at all read-only
|
1300 |
65 |
zero_gravi |
when others => csr_acc_valid <= '0';
|
1301 |
|
|
end case;
|
1302 |
56 |
zero_gravi |
|
1303 |
59 |
zero_gravi |
-- debug mode CSRs --
|
1304 |
|
|
when csr_dcsr_c | csr_dpc_c | csr_dscratch0_c =>
|
1305 |
65 |
zero_gravi |
csr_acc_valid <= debug_ctrl.running and bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG); -- access only in debug-mode
|
1306 |
59 |
zero_gravi |
|
1307 |
72 |
zero_gravi |
-- trigger module CSRs --
|
1308 |
|
|
when csr_tselect_c | csr_tdata1_c | csr_tdata2_c | csr_tdata3_c | csr_tinfo_c | csr_tcontrol_c | csr_mcontext_c | csr_scontext_c =>
|
1309 |
73 |
zero_gravi |
-- access in debug-mode or M-mode (M-mode: writes to tdata* are ignored as DMODE is hardwired to 1)
|
1310 |
|
|
csr_acc_valid <= (debug_ctrl.running or csr.privilege_eff) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG);
|
1311 |
72 |
zero_gravi |
|
1312 |
56 |
zero_gravi |
-- undefined / not implemented --
|
1313 |
|
|
when others =>
|
1314 |
65 |
zero_gravi |
csr_acc_valid <= '0'; -- invalid access
|
1315 |
15 |
zero_gravi |
end case;
|
1316 |
49 |
zero_gravi |
end process csr_access_check;
|
1317 |
15 |
zero_gravi |
|
1318 |
|
|
|
1319 |
2 |
zero_gravi |
-- Illegal Instruction Check --------------------------------------------------------------
|
1320 |
|
|
-- -------------------------------------------------------------------------------------------
|
1321 |
62 |
zero_gravi |
illegal_instruction_check: process(execute_engine, decode_aux, csr, csr_acc_valid, debug_ctrl)
|
1322 |
2 |
zero_gravi |
begin
|
1323 |
73 |
zero_gravi |
-- defaults --
|
1324 |
74 |
zero_gravi |
illegal_cmd <= '0';
|
1325 |
|
|
illegal_reg <= '0';
|
1326 |
2 |
zero_gravi |
|
1327 |
74 |
zero_gravi |
-- check instruction word encoding and side effects --
|
1328 |
|
|
case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is
|
1329 |
36 |
zero_gravi |
|
1330 |
74 |
zero_gravi |
when opcode_lui_c | opcode_auipc_c | opcode_jal_c => -- LUI, UIPC, JAL (only check actual OPCODE)
|
1331 |
73 |
zero_gravi |
-- ------------------------------------------------------------
|
1332 |
74 |
zero_gravi |
illegal_cmd <= '0';
|
1333 |
|
|
illegal_reg <= execute_engine.i_reg(instr_rd_msb_c); -- illegal 'E' register?
|
1334 |
73 |
zero_gravi |
|
1335 |
74 |
zero_gravi |
when opcode_jalr_c => -- check JALR.funct3
|
1336 |
73 |
zero_gravi |
-- ------------------------------------------------------------
|
1337 |
74 |
zero_gravi |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
1338 |
|
|
when "000" => illegal_cmd <= '0';
|
1339 |
|
|
when others => illegal_cmd <= '1';
|
1340 |
|
|
end case;
|
1341 |
|
|
illegal_reg <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); -- illegal 'E' register?
|
1342 |
2 |
zero_gravi |
|
1343 |
74 |
zero_gravi |
when opcode_branch_c => -- check BRANCH.funct3
|
1344 |
73 |
zero_gravi |
-- ------------------------------------------------------------
|
1345 |
74 |
zero_gravi |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
1346 |
|
|
when funct3_beq_c | funct3_bne_c | funct3_blt_c | funct3_bge_c | funct3_bltu_c | funct3_bgeu_c => illegal_cmd <= '0';
|
1347 |
|
|
when others => illegal_cmd <= '1';
|
1348 |
|
|
end case;
|
1349 |
|
|
illegal_reg <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c); -- illegal 'E' register?
|
1350 |
44 |
zero_gravi |
|
1351 |
73 |
zero_gravi |
when opcode_load_c => -- check LOAD.funct3
|
1352 |
|
|
-- ------------------------------------------------------------
|
1353 |
74 |
zero_gravi |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
1354 |
|
|
when funct3_lb_c | funct3_lh_c | funct3_lw_c | funct3_lbu_c | funct3_lhu_c => illegal_cmd <= '0';
|
1355 |
|
|
when others => illegal_cmd <= '1';
|
1356 |
|
|
end case;
|
1357 |
|
|
illegal_reg <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); -- illegal 'E' register?
|
1358 |
39 |
zero_gravi |
|
1359 |
73 |
zero_gravi |
when opcode_store_c => -- check STORE.funct3
|
1360 |
|
|
-- ------------------------------------------------------------
|
1361 |
74 |
zero_gravi |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
1362 |
|
|
when funct3_sb_c | funct3_sh_c | funct3_sw_c => illegal_cmd <= '0';
|
1363 |
|
|
when others => illegal_cmd <= '1';
|
1364 |
|
|
end case;
|
1365 |
|
|
illegal_reg <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c); -- illegal 'E' register?
|
1366 |
39 |
zero_gravi |
|
1367 |
74 |
zero_gravi |
when opcode_alu_c => -- check ALU.funct3 & ALU.funct7
|
1368 |
73 |
zero_gravi |
-- ------------------------------------------------------------
|
1369 |
74 |
zero_gravi |
if ((((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and
|
1370 |
|
|
(execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0')) or
|
1371 |
|
|
(((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or
|
1372 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or
|
1373 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) or
|
1374 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_xor_c) or
|
1375 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_or_c) or
|
1376 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_and_c)) and
|
1377 |
|
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000000"))) or -- valid base ALU instruction?
|
1378 |
|
|
(((CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = true)) and (decode_aux.is_m_mul = '1')) or -- valid MUL instruction?
|
1379 |
|
|
((CPU_EXTENSION_RISCV_M = true) and (decode_aux.is_m_div = '1')) or -- valid DIV instruction?
|
1380 |
|
|
((CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_b_reg = '1')) then -- valid BITMANIP register instruction?
|
1381 |
|
|
illegal_cmd <= '0';
|
1382 |
73 |
zero_gravi |
else
|
1383 |
74 |
zero_gravi |
illegal_cmd <= '1';
|
1384 |
73 |
zero_gravi |
end if;
|
1385 |
74 |
zero_gravi |
illegal_reg <= execute_engine.i_reg(instr_rd_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c); -- illegal 'E' register?
|
1386 |
2 |
zero_gravi |
|
1387 |
74 |
zero_gravi |
when opcode_alui_c => -- check ALU.funct3 & ALU.funct7
|
1388 |
73 |
zero_gravi |
-- ------------------------------------------------------------
|
1389 |
74 |
zero_gravi |
if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
|
1390 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or
|
1391 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sltu_c) or
|
1392 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_xor_c) or
|
1393 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_or_c) or
|
1394 |
|
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_and_c) or
|
1395 |
|
|
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and
|
1396 |
|
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000000")) or
|
1397 |
|
|
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and
|
1398 |
|
|
((execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0')))) or -- valid base ALUI instruction?
|
1399 |
|
|
((CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_b_imm = '1')) then -- valid BITMANIP immediate instruction?
|
1400 |
|
|
illegal_cmd <= '0';
|
1401 |
73 |
zero_gravi |
else
|
1402 |
74 |
zero_gravi |
illegal_cmd <= '1';
|
1403 |
73 |
zero_gravi |
end if;
|
1404 |
74 |
zero_gravi |
illegal_reg <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); -- illegal 'E' register?
|
1405 |
2 |
zero_gravi |
|
1406 |
74 |
zero_gravi |
when opcode_fence_c => -- check FENCE.funct3, ignore all remaining bit-fields
|
1407 |
73 |
zero_gravi |
-- ------------------------------------------------------------
|
1408 |
74 |
zero_gravi |
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
1409 |
|
|
when funct3_fence_c => illegal_cmd <= '0'; -- FENCE
|
1410 |
|
|
when funct3_fencei_c => illegal_cmd <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- FENCE.I
|
1411 |
|
|
when others => illegal_cmd <= '1';
|
1412 |
|
|
end case;
|
1413 |
8 |
zero_gravi |
|
1414 |
74 |
zero_gravi |
when opcode_atomic_c => -- check AMO.funct3 and AMO.funct5
|
1415 |
73 |
zero_gravi |
-- ------------------------------------------------------------
|
1416 |
74 |
zero_gravi |
if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010") and
|
1417 |
|
|
(execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c+1) = "0001") then -- LR/SC
|
1418 |
|
|
illegal_cmd <= '0';
|
1419 |
73 |
zero_gravi |
else
|
1420 |
74 |
zero_gravi |
illegal_cmd <= '1';
|
1421 |
73 |
zero_gravi |
end if;
|
1422 |
74 |
zero_gravi |
illegal_reg <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rd_msb_c); -- illegal 'E' register?
|
1423 |
39 |
zero_gravi |
|
1424 |
74 |
zero_gravi |
when opcode_system_c => -- check system instructions
|
1425 |
73 |
zero_gravi |
-- ------------------------------------------------------------
|
1426 |
74 |
zero_gravi |
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system environment
|
1427 |
|
|
if (decode_aux.rs1_zero = '1') and (decode_aux.rd_zero = '1') then
|
1428 |
|
|
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
|
1429 |
|
|
when funct12_ecall_c | funct12_ebreak_c => illegal_cmd <= '0'; -- ECALL, EBREAK
|
1430 |
|
|
when funct12_mret_c => illegal_cmd <= not csr.privilege; -- MRET (only allowed in ACTUAL M-mode)
|
1431 |
|
|
when funct12_wfi_c => illegal_cmd <= (not csr.privilege) and csr.mstatus_tw; -- WFI (only allowed in ACTUAL M-mode or if mstatus.TW = 0)
|
1432 |
|
|
when funct12_dret_c => illegal_cmd <= not debug_ctrl.running; -- DRET (only allowed in D-mode)
|
1433 |
|
|
when others => illegal_cmd <= '1';
|
1434 |
|
|
end case;
|
1435 |
|
|
else
|
1436 |
|
|
illegal_cmd <= '1';
|
1437 |
72 |
zero_gravi |
end if;
|
1438 |
74 |
zero_gravi |
else -- CSR access
|
1439 |
|
|
if (csr_acc_valid = '0') then -- invalid CSR access?
|
1440 |
|
|
illegal_cmd <= '1';
|
1441 |
|
|
end if;
|
1442 |
73 |
zero_gravi |
end if;
|
1443 |
74 |
zero_gravi |
-- illegal E-CPU register? --
|
1444 |
|
|
if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR (or ENV where rd=rs1=zero)
|
1445 |
|
|
illegal_reg <= execute_engine.i_reg(instr_rd_msb_c) or execute_engine.i_reg(instr_rs1_msb_c);
|
1446 |
|
|
else -- reg-imm CSR
|
1447 |
|
|
illegal_reg <= execute_engine.i_reg(instr_rd_msb_c);
|
1448 |
|
|
end if;
|
1449 |
72 |
zero_gravi |
|
1450 |
73 |
zero_gravi |
when opcode_fop_c => -- floating point operations - single/dual operands
|
1451 |
|
|
-- ------------------------------------------------------------
|
1452 |
|
|
if (CPU_EXTENSION_RISCV_Zfinx = true) and -- F extension implemented
|
1453 |
|
|
(execute_engine.i_reg(instr_funct7_lsb_c+1 downto instr_funct7_lsb_c) = float_single_c) and -- single-precision operations only
|
1454 |
|
|
(decode_aux.is_f_op = '1') then -- is correct/supported floating-point instruction
|
1455 |
74 |
zero_gravi |
illegal_cmd <= '0';
|
1456 |
73 |
zero_gravi |
else
|
1457 |
74 |
zero_gravi |
illegal_cmd <= '1';
|
1458 |
73 |
zero_gravi |
end if;
|
1459 |
74 |
zero_gravi |
illegal_reg <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); -- illegal 'E' register?
|
1460 |
2 |
zero_gravi |
|
1461 |
73 |
zero_gravi |
when opcode_cust0_c => -- CFU: custom instructions
|
1462 |
|
|
-- ------------------------------------------------------------
|
1463 |
74 |
zero_gravi |
illegal_cmd <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zxcfu); -- CFU extension not implemented
|
1464 |
|
|
illegal_reg <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c); -- illegal 'E' register?
|
1465 |
73 |
zero_gravi |
|
1466 |
74 |
zero_gravi |
when others => -- illegal opcode
|
1467 |
73 |
zero_gravi |
-- ------------------------------------------------------------
|
1468 |
74 |
zero_gravi |
illegal_cmd <= '1';
|
1469 |
73 |
zero_gravi |
|
1470 |
|
|
end case;
|
1471 |
2 |
zero_gravi |
end process illegal_instruction_check;
|
1472 |
|
|
|
1473 |
|
|
|
1474 |
73 |
zero_gravi |
-- Illegal Operation Check ----------------------------------------------------------------
|
1475 |
|
|
-- -------------------------------------------------------------------------------------------
|
1476 |
|
|
-- check in EXECUTE state: any illegal condition? --
|
1477 |
74 |
zero_gravi |
trap_ctrl.instr_il <= (illegal_cmd or -- illegal instruction
|
1478 |
|
|
(bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and illegal_reg) or -- illegal register access in E extension
|
1479 |
|
|
(bool_to_ulogic_f(CPU_EXTENSION_RISCV_C) and execute_engine.is_ici)) -- illegal compressed instruction
|
1480 |
|
|
when (execute_engine.state = EXECUTE) else '0'; -- evaluate in EXECUTE stage only
|
1481 |
2 |
zero_gravi |
|
1482 |
73 |
zero_gravi |
|
1483 |
6 |
zero_gravi |
-- ****************************************************************************************************************************
|
1484 |
71 |
zero_gravi |
-- Exception and Interrupt (= Traps) Control
|
1485 |
6 |
zero_gravi |
-- ****************************************************************************************************************************
|
1486 |
2 |
zero_gravi |
|
1487 |
6 |
zero_gravi |
-- Trap Controller ------------------------------------------------------------------------
|
1488 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
1489 |
6 |
zero_gravi |
trap_controller: process(rstn_i, clk_i)
|
1490 |
2 |
zero_gravi |
begin
|
1491 |
|
|
if (rstn_i = '0') then
|
1492 |
6 |
zero_gravi |
trap_ctrl.exc_buf <= (others => '0');
|
1493 |
64 |
zero_gravi |
trap_ctrl.irq_buf <= (others => '0');
|
1494 |
47 |
zero_gravi |
trap_ctrl.env_start <= '0';
|
1495 |
65 |
zero_gravi |
trap_ctrl.cause <= (others => '0');
|
1496 |
2 |
zero_gravi |
elsif rising_edge(clk_i) then
|
1497 |
|
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
1498 |
73 |
zero_gravi |
-- > clear all queued exception triggers when starting the trap handling environment (trap_ctrl.env_start = 1)
|
1499 |
59 |
zero_gravi |
|
1500 |
68 |
zero_gravi |
-- exception queue: misaligned load/store/instruction address --
|
1501 |
73 |
zero_gravi |
trap_ctrl.exc_buf(exc_lalign_c) <= (trap_ctrl.exc_buf(exc_lalign_c) or ma_load_i) and (not trap_ctrl.env_start);
|
1502 |
|
|
trap_ctrl.exc_buf(exc_salign_c) <= (trap_ctrl.exc_buf(exc_salign_c) or ma_store_i) and (not trap_ctrl.env_start);
|
1503 |
|
|
trap_ctrl.exc_buf(exc_ialign_c) <= (trap_ctrl.exc_buf(exc_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.env_start);
|
1504 |
59 |
zero_gravi |
|
1505 |
68 |
zero_gravi |
-- exception queue: load/store/instruction bus access error --
|
1506 |
73 |
zero_gravi |
trap_ctrl.exc_buf(exc_laccess_c) <= (trap_ctrl.exc_buf(exc_laccess_c) or be_load_i) and (not trap_ctrl.env_start);
|
1507 |
|
|
trap_ctrl.exc_buf(exc_saccess_c) <= (trap_ctrl.exc_buf(exc_saccess_c) or be_store_i) and (not trap_ctrl.env_start);
|
1508 |
|
|
trap_ctrl.exc_buf(exc_iaccess_c) <= (trap_ctrl.exc_buf(exc_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.env_start);
|
1509 |
59 |
zero_gravi |
|
1510 |
68 |
zero_gravi |
-- exception queue: illegal instruction / environment calls --
|
1511 |
73 |
zero_gravi |
trap_ctrl.exc_buf(exc_m_envcall_c) <= (trap_ctrl.exc_buf(exc_m_envcall_c) or (trap_ctrl.env_call and ( csr.privilege))) and (not trap_ctrl.env_start);
|
1512 |
|
|
trap_ctrl.exc_buf(exc_u_envcall_c) <= (trap_ctrl.exc_buf(exc_u_envcall_c) or (trap_ctrl.env_call and (not csr.privilege))) and (not trap_ctrl.env_start);
|
1513 |
|
|
trap_ctrl.exc_buf(exc_iillegal_c) <= (trap_ctrl.exc_buf(exc_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.env_start);
|
1514 |
68 |
zero_gravi |
|
1515 |
|
|
-- exception queue: break point --
|
1516 |
59 |
zero_gravi |
if (CPU_EXTENSION_RISCV_DEBUG = true) then
|
1517 |
73 |
zero_gravi |
trap_ctrl.exc_buf(exc_break_c) <= (not trap_ctrl.env_start) and (trap_ctrl.exc_buf(exc_break_c) or
|
1518 |
|
|
(trap_ctrl.break_point and ( csr.privilege) and (not csr.dcsr_ebreakm) and (not debug_ctrl.running)) or -- break to machine-trap-handler when in machine mode on "ebreak"
|
1519 |
|
|
(trap_ctrl.break_point and (not csr.privilege) and (not csr.dcsr_ebreaku) and (not debug_ctrl.running))); -- break to machine-trap-handler when in user mode on "ebreak"
|
1520 |
59 |
zero_gravi |
else
|
1521 |
73 |
zero_gravi |
trap_ctrl.exc_buf(exc_break_c) <= (trap_ctrl.exc_buf(exc_break_c) or trap_ctrl.break_point) and (not trap_ctrl.env_start);
|
1522 |
59 |
zero_gravi |
end if;
|
1523 |
|
|
|
1524 |
72 |
zero_gravi |
-- exception queue / interrupt buffer: enter debug mode --
|
1525 |
73 |
zero_gravi |
if (CPU_EXTENSION_RISCV_DEBUG = true) then
|
1526 |
|
|
trap_ctrl.exc_buf(exc_db_break_c) <= (trap_ctrl.exc_buf(exc_db_break_c) or debug_ctrl.trig_break) and (not trap_ctrl.env_start);
|
1527 |
|
|
trap_ctrl.exc_buf(exc_db_hw_c) <= (trap_ctrl.exc_buf(exc_db_hw_c) or debug_ctrl.trig_hw) and (not trap_ctrl.env_start);
|
1528 |
|
|
trap_ctrl.irq_buf(irq_db_halt_c) <= debug_ctrl.trig_halt;
|
1529 |
|
|
trap_ctrl.irq_buf(irq_db_step_c) <= debug_ctrl.trig_step;
|
1530 |
|
|
end if;
|
1531 |
59 |
zero_gravi |
|
1532 |
68 |
zero_gravi |
-- interrupt buffer: machine software/external/timer interrupt --
|
1533 |
73 |
zero_gravi |
trap_ctrl.irq_buf(irq_msw_irq_c) <= csr.mie_msie and msw_irq_i;
|
1534 |
|
|
trap_ctrl.irq_buf(irq_mext_irq_c) <= csr.mie_meie and mext_irq_i;
|
1535 |
|
|
trap_ctrl.irq_buf(irq_mtime_irq_c) <= csr.mie_mtie and mtime_irq_i;
|
1536 |
59 |
zero_gravi |
|
1537 |
72 |
zero_gravi |
-- interrupt *queue*: NEORV32-specific fast interrupts (FIRQ) - require manual ACK/clear --
|
1538 |
73 |
zero_gravi |
trap_ctrl.irq_buf(irq_firq_15_c downto irq_firq_0_c) <= (trap_ctrl.irq_buf(irq_firq_15_c downto irq_firq_0_c) or (csr.mie_firqe and firq_i)) and csr.mip_firq_nclr;
|
1539 |
68 |
zero_gravi |
|
1540 |
|
|
-- trap environment control --
|
1541 |
6 |
zero_gravi |
if (trap_ctrl.env_start = '0') then -- no started trap handler
|
1542 |
68 |
zero_gravi |
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception triggered!
|
1543 |
49 |
zero_gravi |
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP_ENTER))) then -- fire IRQs in EXECUTE or TRAP state only to continue execution even on permanent IRQ
|
1544 |
73 |
zero_gravi |
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture trap ID for mcause csr
|
1545 |
65 |
zero_gravi |
trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler
|
1546 |
2 |
zero_gravi |
end if;
|
1547 |
73 |
zero_gravi |
elsif (trap_ctrl.env_start_ack = '1') then -- start of trap handler acknowledged by execute engine
|
1548 |
|
|
trap_ctrl.env_start <= '0';
|
1549 |
2 |
zero_gravi |
end if;
|
1550 |
|
|
end if;
|
1551 |
|
|
end if;
|
1552 |
6 |
zero_gravi |
end process trap_controller;
|
1553 |
2 |
zero_gravi |
|
1554 |
|
|
-- any exception/interrupt? --
|
1555 |
74 |
zero_gravi |
trap_ctrl.exc_fire <= '1' when (or_reduce_f(trap_ctrl.exc_buf) = '1') else '0'; -- sync. exceptions CANNOT be masked
|
1556 |
|
|
trap_ctrl.irq_fire <= '1' when ((or_reduce_f(trap_ctrl.irq_buf) = '1') and (csr.mstatus_mie = '1') and (trap_ctrl.db_irq_en = '1')) or -- interrupts CAN be masked
|
1557 |
|
|
(trap_ctrl.db_irq_fire = '1') else '0'; -- but not the DEBUG halt IRQ
|
1558 |
2 |
zero_gravi |
|
1559 |
59 |
zero_gravi |
-- debug mode (entry) interrupts --
|
1560 |
61 |
zero_gravi |
trap_ctrl.db_irq_en <= '0' when (CPU_EXTENSION_RISCV_DEBUG = true) and ((debug_ctrl.running = '1') or (csr.dcsr_step = '1')) else '1'; -- no interrupts when IN debug mode or IN single-step mode
|
1561 |
73 |
zero_gravi |
trap_ctrl.db_irq_fire <= (trap_ctrl.irq_buf(irq_db_step_c) or trap_ctrl.irq_buf(irq_db_halt_c)) when (CPU_EXTENSION_RISCV_DEBUG = true) else '0'; -- "NMI" for debug mode entry
|
1562 |
59 |
zero_gravi |
|
1563 |
40 |
zero_gravi |
|
1564 |
42 |
zero_gravi |
-- Trap Priority Encoder ------------------------------------------------------------------
|
1565 |
6 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
1566 |
|
|
trap_priority: process(trap_ctrl)
|
1567 |
2 |
zero_gravi |
begin
|
1568 |
58 |
zero_gravi |
-- ----------------------------------------------------------------------------------------
|
1569 |
68 |
zero_gravi |
-- the following traps are caused by *synchronous* exceptions; we do not need a
|
1570 |
64 |
zero_gravi |
-- specific acknowledge mask since only _one_ exception (the one with highest priority)
|
1571 |
|
|
-- is allowed to kick in at once
|
1572 |
59 |
zero_gravi |
-- ----------------------------------------------------------------------------------------
|
1573 |
|
|
|
1574 |
64 |
zero_gravi |
-- exception: 0.0 instruction address misaligned --
|
1575 |
73 |
zero_gravi |
if (trap_ctrl.exc_buf(exc_ialign_c) = '1') then
|
1576 |
64 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_ima_c;
|
1577 |
|
|
|
1578 |
|
|
-- exception: 0.1 instruction access fault --
|
1579 |
73 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exc_iaccess_c) = '1') then
|
1580 |
64 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_iba_c;
|
1581 |
|
|
|
1582 |
|
|
-- exception: 0.2 illegal instruction --
|
1583 |
73 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exc_iillegal_c) = '1') then
|
1584 |
64 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_iil_c;
|
1585 |
|
|
|
1586 |
|
|
|
1587 |
|
|
-- exception: 0.11 environment call from M-mode --
|
1588 |
73 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exc_m_envcall_c) = '1') then
|
1589 |
64 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_menv_c;
|
1590 |
|
|
|
1591 |
|
|
-- exception: 0.8 environment call from U-mode --
|
1592 |
73 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exc_u_envcall_c) = '1') then
|
1593 |
64 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_uenv_c;
|
1594 |
|
|
|
1595 |
|
|
-- exception: 0.3 breakpoint --
|
1596 |
73 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exc_break_c) = '1') then
|
1597 |
64 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_brk_c;
|
1598 |
|
|
|
1599 |
|
|
|
1600 |
|
|
-- exception: 0.6 store address misaligned -
|
1601 |
73 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exc_salign_c) = '1') then
|
1602 |
64 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_sma_c;
|
1603 |
|
|
|
1604 |
|
|
-- exception: 0.4 load address misaligned --
|
1605 |
73 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exc_lalign_c) = '1') then
|
1606 |
64 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_lma_c;
|
1607 |
|
|
|
1608 |
|
|
-- exception: 0.7 store access fault --
|
1609 |
73 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exc_saccess_c) = '1') then
|
1610 |
64 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_sbe_c;
|
1611 |
|
|
|
1612 |
|
|
-- exception: 0.5 load access fault --
|
1613 |
73 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exc_laccess_c) = '1') then
|
1614 |
64 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_lbe_c;
|
1615 |
|
|
|
1616 |
|
|
-- ----------------------------------------------------------------------------------------
|
1617 |
69 |
zero_gravi |
-- (re-)enter debug mode requests: basically, these are standard traps that have some
|
1618 |
64 |
zero_gravi |
-- special handling - they have the highest INTERRUPT priority in order to go to debug when requested
|
1619 |
|
|
-- even if other IRQs are pending right now
|
1620 |
|
|
-- ----------------------------------------------------------------------------------------
|
1621 |
|
|
|
1622 |
72 |
zero_gravi |
-- hardware trigger (sync) --
|
1623 |
73 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exc_db_hw_c) = '1') then
|
1624 |
72 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_db_hw_c;
|
1625 |
|
|
|
1626 |
71 |
zero_gravi |
-- break instruction (sync) --
|
1627 |
73 |
zero_gravi |
elsif (trap_ctrl.exc_buf(exc_db_break_c) = '1') then
|
1628 |
59 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_db_break_c;
|
1629 |
|
|
|
1630 |
73 |
zero_gravi |
-- async. exceptions / interrupts
|
1631 |
|
|
|
1632 |
71 |
zero_gravi |
-- external halt request (async) --
|
1633 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_db_halt_c) = '1') then
|
1634 |
59 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_db_halt_c;
|
1635 |
|
|
|
1636 |
71 |
zero_gravi |
-- single stepping (async) --
|
1637 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_db_step_c) = '1') then
|
1638 |
64 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_db_step_c;
|
1639 |
59 |
zero_gravi |
|
1640 |
|
|
-- ----------------------------------------------------------------------------------------
|
1641 |
71 |
zero_gravi |
-- custom FAST interrupts (*asynchronous* exceptions)
|
1642 |
58 |
zero_gravi |
-- ----------------------------------------------------------------------------------------
|
1643 |
9 |
zero_gravi |
|
1644 |
14 |
zero_gravi |
-- interrupt: 1.16 fast interrupt channel 0 --
|
1645 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_0_c) = '1') then
|
1646 |
14 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq0_c;
|
1647 |
|
|
|
1648 |
|
|
-- interrupt: 1.17 fast interrupt channel 1 --
|
1649 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_1_c) = '1') then
|
1650 |
14 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq1_c;
|
1651 |
|
|
|
1652 |
|
|
-- interrupt: 1.18 fast interrupt channel 2 --
|
1653 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_2_c) = '1') then
|
1654 |
14 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq2_c;
|
1655 |
|
|
|
1656 |
|
|
-- interrupt: 1.19 fast interrupt channel 3 --
|
1657 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_3_c) = '1') then
|
1658 |
14 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq3_c;
|
1659 |
|
|
|
1660 |
47 |
zero_gravi |
-- interrupt: 1.20 fast interrupt channel 4 --
|
1661 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_4_c) = '1') then
|
1662 |
47 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq4_c;
|
1663 |
14 |
zero_gravi |
|
1664 |
47 |
zero_gravi |
-- interrupt: 1.21 fast interrupt channel 5 --
|
1665 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_5_c) = '1') then
|
1666 |
47 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq5_c;
|
1667 |
|
|
|
1668 |
|
|
-- interrupt: 1.22 fast interrupt channel 6 --
|
1669 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_6_c) = '1') then
|
1670 |
47 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq6_c;
|
1671 |
|
|
|
1672 |
|
|
-- interrupt: 1.23 fast interrupt channel 7 --
|
1673 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_7_c) = '1') then
|
1674 |
47 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq7_c;
|
1675 |
|
|
|
1676 |
48 |
zero_gravi |
-- interrupt: 1.24 fast interrupt channel 8 --
|
1677 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_8_c) = '1') then
|
1678 |
48 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq8_c;
|
1679 |
47 |
zero_gravi |
|
1680 |
48 |
zero_gravi |
-- interrupt: 1.25 fast interrupt channel 9 --
|
1681 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_9_c) = '1') then
|
1682 |
48 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq9_c;
|
1683 |
|
|
|
1684 |
|
|
-- interrupt: 1.26 fast interrupt channel 10 --
|
1685 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_10_c) = '1') then
|
1686 |
48 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq10_c;
|
1687 |
|
|
|
1688 |
|
|
-- interrupt: 1.27 fast interrupt channel 11 --
|
1689 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_11_c) = '1') then
|
1690 |
48 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq11_c;
|
1691 |
|
|
|
1692 |
|
|
-- interrupt: 1.28 fast interrupt channel 12 --
|
1693 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_12_c) = '1') then
|
1694 |
48 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq12_c;
|
1695 |
|
|
|
1696 |
|
|
-- interrupt: 1.29 fast interrupt channel 13 --
|
1697 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_13_c) = '1') then
|
1698 |
48 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq13_c;
|
1699 |
|
|
|
1700 |
|
|
-- interrupt: 1.30 fast interrupt channel 14 --
|
1701 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_14_c) = '1') then
|
1702 |
48 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq14_c;
|
1703 |
|
|
|
1704 |
|
|
-- interrupt: 1.31 fast interrupt channel 15 --
|
1705 |
73 |
zero_gravi |
elsif (trap_ctrl.irq_buf(irq_firq_15_c) = '1') then
|
1706 |
48 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_firq15_c;
|
1707 |
|
|
|
1708 |
71 |
zero_gravi |
-- ----------------------------------------------------------------------------------------
|
1709 |
|
|
-- standard RISC-V interrupts (*asynchronous* exceptions)
|
1710 |
|
|
-- ----------------------------------------------------------------------------------------
|
1711 |
48 |
zero_gravi |
|
1712 |
73 |
zero_gravi |
-- interrupt: 1.11 machine external interrupt (MEI) --
|
1713 |
|
|
elsif (trap_ctrl.irq_buf(irq_mext_irq_c) = '1') then
|
1714 |
64 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_mei_c;
|
1715 |
2 |
zero_gravi |
|
1716 |
73 |
zero_gravi |
-- interrupt: 1.3 machine SW interrupt (MSI) --
|
1717 |
|
|
elsif (trap_ctrl.irq_buf(irq_msw_irq_c) = '1') then
|
1718 |
64 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_msi_c;
|
1719 |
2 |
zero_gravi |
|
1720 |
73 |
zero_gravi |
-- interrupt: 1.7 machine timer interrupt (MTI) --
|
1721 |
|
|
else--if (trap_ctrl.irq_buf(irq_mtime_irq_c) = '1') then -- last condition, so NO IF required
|
1722 |
64 |
zero_gravi |
trap_ctrl.cause_nxt <= trap_mti_c;
|
1723 |
2 |
zero_gravi |
|
1724 |
|
|
end if;
|
1725 |
6 |
zero_gravi |
end process trap_priority;
|
1726 |
|
|
|
1727 |
2 |
zero_gravi |
|
1728 |
6 |
zero_gravi |
-- ****************************************************************************************************************************
|
1729 |
|
|
-- Control and Status Registers (CSRs)
|
1730 |
|
|
-- ****************************************************************************************************************************
|
1731 |
2 |
zero_gravi |
|
1732 |
71 |
zero_gravi |
-- Control and Status Registers - Write Data ----------------------------------------------
|
1733 |
27 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
1734 |
36 |
zero_gravi |
csr_write_data: process(execute_engine.i_reg, csr.rdata, rs1_i)
|
1735 |
71 |
zero_gravi |
variable csr_imm_v : std_ulogic_vector(data_width_c-1 downto 0);
|
1736 |
27 |
zero_gravi |
begin
|
1737 |
71 |
zero_gravi |
-- tiny ALU to compute CSR write data --
|
1738 |
|
|
csr_imm_v := (others => '0');
|
1739 |
|
|
csr_imm_v(4 downto 0) := execute_engine.i_reg(19 downto 15); -- uimm5
|
1740 |
|
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
1741 |
|
|
when funct3_csrrw_c => csr.wdata <= rs1_i;
|
1742 |
|
|
when funct3_csrrs_c => csr.wdata <= csr.rdata or rs1_i;
|
1743 |
|
|
when funct3_csrrc_c => csr.wdata <= csr.rdata and (not rs1_i);
|
1744 |
|
|
when funct3_csrrwi_c => csr.wdata <= csr_imm_v;
|
1745 |
|
|
when funct3_csrrsi_c => csr.wdata <= csr.rdata or csr_imm_v;
|
1746 |
|
|
when funct3_csrrci_c => csr.wdata <= csr.rdata and (not csr_imm_v);
|
1747 |
74 |
zero_gravi |
when others => csr.wdata <= (others => '0'); -- undefined
|
1748 |
27 |
zero_gravi |
end case;
|
1749 |
|
|
end process csr_write_data;
|
1750 |
|
|
|
1751 |
|
|
|
1752 |
52 |
zero_gravi |
-- Control and Status Registers - Write Access --------------------------------------------
|
1753 |
2 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
1754 |
|
|
csr_write_access: process(rstn_i, clk_i)
|
1755 |
65 |
zero_gravi |
variable cause_v : std_ulogic_vector(6 downto 0);
|
1756 |
2 |
zero_gravi |
begin
|
1757 |
|
|
if (rstn_i = '0') then
|
1758 |
68 |
zero_gravi |
csr.we <= '0';
|
1759 |
74 |
zero_gravi |
csr.re <= def_rst_val_c;
|
1760 |
11 |
zero_gravi |
--
|
1761 |
68 |
zero_gravi |
csr.mstatus_mie <= '0';
|
1762 |
|
|
csr.mstatus_mpie <= '0';
|
1763 |
73 |
zero_gravi |
csr.mstatus_mpp <= '0';
|
1764 |
|
|
csr.mstatus_tw <= '0';
|
1765 |
68 |
zero_gravi |
csr.privilege <= priv_mode_m_c; -- start in MACHINE mode
|
1766 |
|
|
csr.mie_msie <= def_rst_val_c;
|
1767 |
|
|
csr.mie_meie <= def_rst_val_c;
|
1768 |
|
|
csr.mie_mtie <= def_rst_val_c;
|
1769 |
|
|
csr.mie_firqe <= (others => def_rst_val_c);
|
1770 |
|
|
csr.mtvec <= (others => def_rst_val_c);
|
1771 |
|
|
csr.mscratch <= x"19880704";
|
1772 |
|
|
csr.mepc <= (others => def_rst_val_c);
|
1773 |
|
|
csr.mcause <= (others => def_rst_val_c);
|
1774 |
|
|
csr.mtval <= (others => def_rst_val_c);
|
1775 |
73 |
zero_gravi |
csr.mip_firq_nclr <= (others => def_rst_val_c);
|
1776 |
42 |
zero_gravi |
--
|
1777 |
68 |
zero_gravi |
csr.pmpcfg <= (others => (others => '0'));
|
1778 |
|
|
csr.pmpaddr <= (others => (others => def_rst_val_c));
|
1779 |
34 |
zero_gravi |
--
|
1780 |
68 |
zero_gravi |
csr.mhpmevent <= (others => (others => def_rst_val_c));
|
1781 |
41 |
zero_gravi |
--
|
1782 |
68 |
zero_gravi |
csr.mcounteren_cy <= def_rst_val_c;
|
1783 |
|
|
csr.mcounteren_tm <= def_rst_val_c;
|
1784 |
|
|
csr.mcounteren_ir <= def_rst_val_c;
|
1785 |
42 |
zero_gravi |
--
|
1786 |
56 |
zero_gravi |
csr.mcountinhibit_cy <= def_rst_val_c;
|
1787 |
|
|
csr.mcountinhibit_ir <= def_rst_val_c;
|
1788 |
|
|
csr.mcountinhibit_hpm <= (others => def_rst_val_c);
|
1789 |
52 |
zero_gravi |
--
|
1790 |
68 |
zero_gravi |
csr.fflags <= (others => def_rst_val_c);
|
1791 |
|
|
csr.frm <= (others => def_rst_val_c);
|
1792 |
59 |
zero_gravi |
--
|
1793 |
68 |
zero_gravi |
csr.dcsr_ebreakm <= '0';
|
1794 |
|
|
csr.dcsr_ebreaku <= '0';
|
1795 |
|
|
csr.dcsr_step <= '0';
|
1796 |
73 |
zero_gravi |
csr.dcsr_prv <= priv_mode_m_c;
|
1797 |
68 |
zero_gravi |
csr.dcsr_cause <= (others => def_rst_val_c);
|
1798 |
|
|
csr.dpc <= (others => def_rst_val_c);
|
1799 |
|
|
csr.dscratch0 <= (others => def_rst_val_c);
|
1800 |
72 |
zero_gravi |
--
|
1801 |
|
|
csr.tdata1_exe <= '0';
|
1802 |
|
|
csr.tdata2 <= (others => def_rst_val_c);
|
1803 |
49 |
zero_gravi |
|
1804 |
2 |
zero_gravi |
elsif rising_edge(clk_i) then
|
1805 |
29 |
zero_gravi |
-- write access? --
|
1806 |
74 |
zero_gravi |
csr.we <= csr.we_nxt and (not trap_ctrl.exc_buf(exc_iillegal_c)); -- write if not illegal instruction
|
1807 |
|
|
csr.re <= csr.re_nxt;
|
1808 |
56 |
zero_gravi |
|
1809 |
69 |
zero_gravi |
-- defaults --
|
1810 |
73 |
zero_gravi |
csr.mip_firq_nclr <= (others => '1'); -- active low
|
1811 |
69 |
zero_gravi |
|
1812 |
36 |
zero_gravi |
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
1813 |
|
|
-- --------------------------------------------------------------------------------
|
1814 |
|
|
-- CSR access by application software
|
1815 |
|
|
-- --------------------------------------------------------------------------------
|
1816 |
74 |
zero_gravi |
if (csr.we = '1') then -- manual write access and not illegal instruction
|
1817 |
52 |
zero_gravi |
|
1818 |
|
|
-- user floating-point CSRs --
|
1819 |
|
|
-- --------------------------------------------------------------------
|
1820 |
56 |
zero_gravi |
if (CPU_EXTENSION_RISCV_Zfinx = true) then -- floating point CSR class
|
1821 |
68 |
zero_gravi |
if (csr.addr(11 downto 2) = csr_class_float_c) then
|
1822 |
|
|
if (csr.addr(1 downto 0) = "01") then -- R/W: fflags - floating-point (FPU) exception flags
|
1823 |
|
|
csr.fflags <= csr.wdata(4 downto 0);
|
1824 |
|
|
elsif (csr.addr(1 downto 0) = "10") then -- R/W: frm - floating-point (FPU) rounding mode
|
1825 |
|
|
csr.frm <= csr.wdata(2 downto 0);
|
1826 |
|
|
elsif (csr.addr(1 downto 0) = "11") then -- R/W: fcsr - floating-point (FPU) control/status (frm + fflags)
|
1827 |
|
|
csr.frm <= csr.wdata(7 downto 5);
|
1828 |
|
|
csr.fflags <= csr.wdata(4 downto 0);
|
1829 |
|
|
end if;
|
1830 |
52 |
zero_gravi |
end if;
|
1831 |
|
|
end if;
|
1832 |
|
|
|
1833 |
|
|
-- machine trap setup --
|
1834 |
|
|
-- --------------------------------------------------------------------
|
1835 |
63 |
zero_gravi |
if (csr.addr(11 downto 3) = csr_class_setup_c) then -- trap setup CSR class
|
1836 |
52 |
zero_gravi |
-- R/W: mstatus - machine status register --
|
1837 |
63 |
zero_gravi |
if (csr.addr(2 downto 0) = csr_mstatus_c(2 downto 0)) then
|
1838 |
36 |
zero_gravi |
csr.mstatus_mie <= csr.wdata(03);
|
1839 |
|
|
csr.mstatus_mpie <= csr.wdata(07);
|
1840 |
|
|
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
|
1841 |
73 |
zero_gravi |
csr.mstatus_mpp <= csr.wdata(11) or csr.wdata(12); -- everything /= U will fall back to M
|
1842 |
|
|
csr.mstatus_tw <= csr.wdata(21);
|
1843 |
36 |
zero_gravi |
end if;
|
1844 |
52 |
zero_gravi |
end if;
|
1845 |
|
|
-- R/W: mie - machine interrupt enable register --
|
1846 |
63 |
zero_gravi |
if (csr.addr(2 downto 0) = csr_mie_c(2 downto 0)) then
|
1847 |
73 |
zero_gravi |
csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable
|
1848 |
|
|
csr.mie_mtie <= csr.wdata(07); -- machine TIMER IRQ enable
|
1849 |
|
|
csr.mie_meie <= csr.wdata(11); -- machine EXT IRQ enable
|
1850 |
|
|
csr.mie_firqe <= csr.wdata(31 downto 16); -- fast interrupt channels 0..15
|
1851 |
52 |
zero_gravi |
end if;
|
1852 |
|
|
-- R/W: mtvec - machine trap-handler base address (for ALL exceptions) --
|
1853 |
63 |
zero_gravi |
if (csr.addr(2 downto 0) = csr_mtvec_c(2 downto 0)) then
|
1854 |
29 |
zero_gravi |
csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
1855 |
52 |
zero_gravi |
end if;
|
1856 |
66 |
zero_gravi |
-- R/W: mcounteren - machine counter enable register --
|
1857 |
56 |
zero_gravi |
if (CPU_EXTENSION_RISCV_U = true) then -- this CSR is hardwired to zero if user mode is not implemented
|
1858 |
63 |
zero_gravi |
if (csr.addr(2 downto 0) = csr_mcounteren_c(2 downto 0)) then
|
1859 |
61 |
zero_gravi |
csr.mcounteren_cy <= csr.wdata(0); -- enable user-level access to cycle[h]
|
1860 |
|
|
csr.mcounteren_tm <= csr.wdata(1); -- enable user-level access to time[h]
|
1861 |
|
|
csr.mcounteren_ir <= csr.wdata(2); -- enable user-level access to instret[h]
|
1862 |
51 |
zero_gravi |
end if;
|
1863 |
52 |
zero_gravi |
end if;
|
1864 |
|
|
end if;
|
1865 |
29 |
zero_gravi |
|
1866 |
52 |
zero_gravi |
-- machine trap handling --
|
1867 |
|
|
-- --------------------------------------------------------------------
|
1868 |
69 |
zero_gravi |
if (csr.addr(11 downto 4) = csr_class_trap_c) then -- machine trap handling CSR class
|
1869 |
52 |
zero_gravi |
-- R/W: mscratch - machine scratch register --
|
1870 |
69 |
zero_gravi |
if (csr.addr(3 downto 0) = csr_mscratch_c(3 downto 0)) then
|
1871 |
36 |
zero_gravi |
csr.mscratch <= csr.wdata;
|
1872 |
52 |
zero_gravi |
end if;
|
1873 |
|
|
-- R/W: mepc - machine exception program counter --
|
1874 |
69 |
zero_gravi |
if (csr.addr(3 downto 0) = csr_mepc_c(3 downto 0)) then
|
1875 |
64 |
zero_gravi |
csr.mepc <= csr.wdata;
|
1876 |
52 |
zero_gravi |
end if;
|
1877 |
|
|
-- R/W: mcause - machine trap cause --
|
1878 |
69 |
zero_gravi |
if (csr.addr(3 downto 0) = csr_mcause_c(3 downto 0)) then
|
1879 |
74 |
zero_gravi |
csr.mcause <= csr.wdata(31) & csr.wdata(4 downto 0); -- type + identifier
|
1880 |
52 |
zero_gravi |
end if;
|
1881 |
69 |
zero_gravi |
-- R/W: mip - machine interrupt pending --
|
1882 |
71 |
zero_gravi |
if (csr.addr(3 downto 0) = csr_mip_c(3 downto 0)) then
|
1883 |
73 |
zero_gravi |
csr.mip_firq_nclr <= csr.wdata(31 downto 16); -- set low to clear according bit (FIRQs only)
|
1884 |
69 |
zero_gravi |
end if;
|
1885 |
52 |
zero_gravi |
end if;
|
1886 |
29 |
zero_gravi |
|
1887 |
74 |
zero_gravi |
-- physical memory protection --
|
1888 |
52 |
zero_gravi |
-- --------------------------------------------------------------------
|
1889 |
56 |
zero_gravi |
if (PMP_NUM_REGIONS > 0) then
|
1890 |
74 |
zero_gravi |
-- R/W: pmpcfg* - PMP configuration registers --
|
1891 |
73 |
zero_gravi |
if (csr.addr(11 downto 2) = csr_class_pmpcfg_c) then -- pmp configuration CSR class
|
1892 |
|
|
for i in 0 to 3 loop -- 3 pmpcfg CSRs
|
1893 |
|
|
if (csr.addr(1 downto 0) = std_ulogic_vector(to_unsigned(i, 2))) then
|
1894 |
|
|
for j in 0 to 3 loop -- 4 entries per CSR
|
1895 |
|
|
if (csr.pmpcfg(i*4+j)(7) = '0') then -- unlocked pmpcfg entry
|
1896 |
|
|
csr.pmpcfg(i*4+j)(0) <= csr.wdata(j*8+0); -- R - read
|
1897 |
|
|
csr.pmpcfg(i*4+j)(1) <= csr.wdata(j*8+1); -- W - write
|
1898 |
|
|
csr.pmpcfg(i*4+j)(2) <= csr.wdata(j*8+2); -- X - execute
|
1899 |
|
|
csr.pmpcfg(i*4+j)(3) <= csr.wdata(j*8+3); -- A_L - mode low [TOR-mode only!]
|
1900 |
|
|
csr.pmpcfg(i*4+j)(4) <= '0'; -- A_H - mode high [TOR-mode only!]
|
1901 |
|
|
csr.pmpcfg(i*4+j)(5) <= '0'; -- reserved
|
1902 |
|
|
csr.pmpcfg(i*4+j)(6) <= '0'; -- reserved
|
1903 |
|
|
csr.pmpcfg(i*4+j)(7) <= csr.wdata(j*8+7); -- L (locked / also enforce in machine-mode)
|
1904 |
|
|
end if;
|
1905 |
|
|
end loop; -- j (entry)
|
1906 |
52 |
zero_gravi |
end if;
|
1907 |
73 |
zero_gravi |
end loop; -- i (pmpcfg CSR)
|
1908 |
52 |
zero_gravi |
end if;
|
1909 |
74 |
zero_gravi |
-- R/W: pmpaddr* - PMP address registers --
|
1910 |
73 |
zero_gravi |
if (csr.addr(11 downto 4) = csr_class_pmpaddr_c) then
|
1911 |
52 |
zero_gravi |
for i in 0 to PMP_NUM_REGIONS-1 loop
|
1912 |
73 |
zero_gravi |
if (csr.addr(3 downto 0) = std_ulogic_vector(to_unsigned(i, 4))) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access
|
1913 |
|
|
csr.pmpaddr(i) <= csr.wdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2);
|
1914 |
52 |
zero_gravi |
end if;
|
1915 |
|
|
end loop; -- i (PMP regions)
|
1916 |
|
|
end if;
|
1917 |
|
|
end if;
|
1918 |
2 |
zero_gravi |
|
1919 |
52 |
zero_gravi |
-- machine counter setup --
|
1920 |
|
|
-- --------------------------------------------------------------------
|
1921 |
56 |
zero_gravi |
if (csr.addr(11 downto 5) = csr_cnt_setup_c) then -- counter configuration CSR class
|
1922 |
|
|
-- R/W: mcountinhibit - machine counter-inhibit register --
|
1923 |
|
|
if (csr.addr(4 downto 0) = csr_mcountinhibit_c(4 downto 0)) then
|
1924 |
65 |
zero_gravi |
csr.mcountinhibit_cy <= csr.wdata(0); -- enable auto-increment of [m]cycle[h] counter
|
1925 |
|
|
csr.mcountinhibit_ir <= csr.wdata(2); -- enable auto-increment of [m]instret[h] counter
|
1926 |
73 |
zero_gravi |
if (HPM_NUM_CNTS > 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then -- any HPMs available?
|
1927 |
63 |
zero_gravi |
csr.mcountinhibit_hpm <= csr.wdata(csr.mcountinhibit_hpm'left+3 downto 3); -- enable auto-increment of [m]hpmcounter*[h] counter
|
1928 |
|
|
end if;
|
1929 |
56 |
zero_gravi |
end if;
|
1930 |
66 |
zero_gravi |
-- R/W: mhpmevent - machine performance-monitors event selector --
|
1931 |
|
|
if (HPM_NUM_CNTS > 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then
|
1932 |
52 |
zero_gravi |
for i in 0 to HPM_NUM_CNTS-1 loop
|
1933 |
|
|
if (csr.addr(4 downto 0) = std_ulogic_vector(to_unsigned(i+3, 5))) then
|
1934 |
|
|
csr.mhpmevent(i) <= csr.wdata(csr.mhpmevent(i)'left downto 0);
|
1935 |
|
|
end if;
|
1936 |
56 |
zero_gravi |
csr.mhpmevent(i)(hpmcnt_event_never_c) <= '0'; -- would be used for "TIME"
|
1937 |
52 |
zero_gravi |
end loop; -- i (CSRs)
|
1938 |
|
|
end if;
|
1939 |
|
|
end if;
|
1940 |
42 |
zero_gravi |
|
1941 |
59 |
zero_gravi |
-- debug mode CSRs --
|
1942 |
|
|
-- --------------------------------------------------------------------
|
1943 |
|
|
if (CPU_EXTENSION_RISCV_DEBUG = true) then
|
1944 |
|
|
if (csr.addr(11 downto 2) = csr_class_debug_c) then -- debug CSR class
|
1945 |
|
|
-- R/W: dcsr - debug mode control and status register --
|
1946 |
|
|
if (csr.addr(1 downto 0) = csr_dcsr_c(1 downto 0)) then
|
1947 |
|
|
csr.dcsr_ebreakm <= csr.wdata(15);
|
1948 |
|
|
csr.dcsr_step <= csr.wdata(2);
|
1949 |
|
|
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
|
1950 |
|
|
csr.dcsr_ebreaku <= csr.wdata(12);
|
1951 |
73 |
zero_gravi |
csr.dcsr_prv <= csr.wdata(1) or csr.wdata(0); -- everything /= U will fall back to M
|
1952 |
59 |
zero_gravi |
end if;
|
1953 |
|
|
end if;
|
1954 |
|
|
-- R/W: dpc - debug mode program counter --
|
1955 |
|
|
if (csr.addr(1 downto 0) = csr_dpc_c(1 downto 0)) then
|
1956 |
64 |
zero_gravi |
csr.dpc <= csr.wdata(data_width_c-1 downto 1) & '0';
|
1957 |
59 |
zero_gravi |
end if;
|
1958 |
|
|
-- R/W: dscratch0 - debug mode scratch register 0 --
|
1959 |
|
|
if (csr.addr(1 downto 0) = csr_dscratch0_c(1 downto 0)) then
|
1960 |
|
|
csr.dscratch0 <= csr.wdata;
|
1961 |
|
|
end if;
|
1962 |
|
|
end if;
|
1963 |
|
|
end if;
|
1964 |
29 |
zero_gravi |
|
1965 |
72 |
zero_gravi |
-- trigger module CSRs - only writable in DEBUG MODE (dmode == 1) --
|
1966 |
|
|
-- --------------------------------------------------------------------
|
1967 |
|
|
if (CPU_EXTENSION_RISCV_DEBUG = true) then
|
1968 |
|
|
if (csr.addr(11 downto 4) = csr_class_trigger_c) then -- trigger CSR class
|
1969 |
|
|
if (debug_ctrl.running = '1') then -- actual write only in debug mode
|
1970 |
|
|
-- R/W: tdata1 - match control --
|
1971 |
|
|
if (csr.addr(3 downto 0) = csr_tdata1_c(3 downto 0)) then
|
1972 |
|
|
csr.tdata1_exe <= csr.wdata(2);
|
1973 |
|
|
end if;
|
1974 |
|
|
-- R/W: tdata2 - address compare --
|
1975 |
|
|
if (csr.addr(3 downto 0) = csr_tdata2_c(3 downto 0)) then
|
1976 |
|
|
csr.tdata2 <= csr.wdata(data_width_c-1 downto 1) & '0';
|
1977 |
|
|
end if;
|
1978 |
|
|
end if;
|
1979 |
|
|
end if;
|
1980 |
|
|
end if;
|
1981 |
59 |
zero_gravi |
|
1982 |
72 |
zero_gravi |
|
1983 |
36 |
zero_gravi |
-- --------------------------------------------------------------------------------
|
1984 |
|
|
-- CSR access by hardware
|
1985 |
|
|
-- --------------------------------------------------------------------------------
|
1986 |
|
|
else
|
1987 |
|
|
|
1988 |
52 |
zero_gravi |
-- --------------------------------------------------------------------
|
1989 |
73 |
zero_gravi |
-- floating-point (FPU) exception flags
|
1990 |
|
|
-- --------------------------------------------------------------------
|
1991 |
|
|
if (CPU_EXTENSION_RISCV_Zfinx = true) and (trap_ctrl.exc_buf(exc_iillegal_c) = '0') then -- no illegal instruction
|
1992 |
52 |
zero_gravi |
csr.fflags <= csr.fflags or fpu_flags_i; -- accumulate flags ("accrued exception flags")
|
1993 |
|
|
end if;
|
1994 |
|
|
|
1995 |
36 |
zero_gravi |
-- --------------------------------------------------------------------
|
1996 |
73 |
zero_gravi |
-- TRAP ENTER: write machine trap cause, PC and trap value register
|
1997 |
|
|
-- --------------------------------------------------------------------
|
1998 |
36 |
zero_gravi |
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
|
1999 |
66 |
zero_gravi |
|
2000 |
73 |
zero_gravi |
-- normal trap entry: write mcause, mepc and mtval --
|
2001 |
|
|
-- --------------------------------------------------------------------
|
2002 |
|
|
if (CPU_EXTENSION_RISCV_DEBUG = false) or ((trap_ctrl.cause(5) = '0') and (debug_ctrl.running = '0')) then
|
2003 |
59 |
zero_gravi |
|
2004 |
|
|
-- trap cause ID code --
|
2005 |
74 |
zero_gravi |
csr.mcause <= trap_ctrl.cause(trap_ctrl.cause'left) & trap_ctrl.cause(4 downto 0); -- type + identifier
|
2006 |
59 |
zero_gravi |
|
2007 |
|
|
-- trap PC --
|
2008 |
|
|
if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS (async source)
|
2009 |
|
|
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
|
2010 |
|
|
else -- for sync. EXCEPTIONS (sync source)
|
2011 |
73 |
zero_gravi |
csr.mepc <= execute_engine.pc_last(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
|
2012 |
59 |
zero_gravi |
end if;
|
2013 |
|
|
|
2014 |
|
|
-- trap value --
|
2015 |
65 |
zero_gravi |
cause_v := trap_ctrl.cause;
|
2016 |
74 |
zero_gravi |
cause_v(5) := '0'; -- bit 5 is always zero here (= normal trapping / no debug-mode-entry), so we do not need to check that again
|
2017 |
65 |
zero_gravi |
case cause_v is
|
2018 |
59 |
zero_gravi |
when trap_ima_c | trap_iba_c => -- misaligned instruction address OR instruction access error
|
2019 |
|
|
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
|
2020 |
|
|
when trap_lma_c | trap_lbe_c | trap_sma_c | trap_sbe_c => -- misaligned load/store address OR load/store access error
|
2021 |
|
|
csr.mtval <= mar_i; -- faulting data access address
|
2022 |
|
|
when trap_iil_c => -- illegal instruction
|
2023 |
74 |
zero_gravi |
csr.mtval <= execute_engine.i_reg_last; -- faulting instruction word (decompressed if C-instruction)
|
2024 |
59 |
zero_gravi |
when others => -- everything else including all interrupts
|
2025 |
|
|
csr.mtval <= (others => '0');
|
2026 |
|
|
end case;
|
2027 |
|
|
|
2028 |
40 |
zero_gravi |
end if;
|
2029 |
59 |
zero_gravi |
|
2030 |
61 |
zero_gravi |
-- DEBUG MODE (trap) enter: write dpc and dcsr --
|
2031 |
59 |
zero_gravi |
-- --------------------------------------------------------------------
|
2032 |
73 |
zero_gravi |
if (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.cause(5) = '1') and (debug_ctrl.running = '0') then
|
2033 |
59 |
zero_gravi |
|
2034 |
|
|
-- trap cause ID code --
|
2035 |
|
|
csr.dcsr_cause <= trap_ctrl.cause(2 downto 0); -- why did we enter debug mode?
|
2036 |
73 |
zero_gravi |
|
2037 |
59 |
zero_gravi |
-- current privilege mode when debug mode was entered --
|
2038 |
|
|
csr.dcsr_prv <= csr.privilege;
|
2039 |
|
|
|
2040 |
|
|
-- trap PC --
|
2041 |
|
|
if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS (async source)
|
2042 |
|
|
csr.dpc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
|
2043 |
|
|
else -- for sync. EXCEPTIONS (sync source)
|
2044 |
73 |
zero_gravi |
csr.dpc <= execute_engine.pc_last(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
|
2045 |
59 |
zero_gravi |
end if;
|
2046 |
|
|
|
2047 |
|
|
end if;
|
2048 |
|
|
|
2049 |
2 |
zero_gravi |
end if;
|
2050 |
|
|
|
2051 |
36 |
zero_gravi |
-- --------------------------------------------------------------------
|
2052 |
73 |
zero_gravi |
-- mstatus: context switch
|
2053 |
|
|
-- --------------------------------------------------------------------
|
2054 |
|
|
-- ENTER: trap handler starting
|
2055 |
66 |
zero_gravi |
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
|
2056 |
59 |
zero_gravi |
if (CPU_EXTENSION_RISCV_DEBUG = false) or -- normal trapping (debug mode NOT implemented)
|
2057 |
|
|
((debug_ctrl.running = '0') and (trap_ctrl.cause(5) = '0')) then -- not IN debug mode and not ENTERING debug mode
|
2058 |
|
|
csr.mstatus_mie <= '0'; -- disable interrupts
|
2059 |
|
|
csr.mstatus_mpie <= csr.mstatus_mie; -- buffer previous mie state
|
2060 |
73 |
zero_gravi |
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
|
2061 |
59 |
zero_gravi |
csr.privilege <= priv_mode_m_c; -- execute trap in machine mode
|
2062 |
73 |
zero_gravi |
csr.mstatus_mpp <= csr.privilege; -- backup previous privilege mode
|
2063 |
59 |
zero_gravi |
end if;
|
2064 |
2 |
zero_gravi |
end if;
|
2065 |
59 |
zero_gravi |
|
2066 |
73 |
zero_gravi |
-- EXIT: return from trap
|
2067 |
59 |
zero_gravi |
elsif (trap_ctrl.env_end = '1') then
|
2068 |
|
|
if (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1') then -- return from debug mode
|
2069 |
73 |
zero_gravi |
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
|
2070 |
59 |
zero_gravi |
csr.privilege <= csr.dcsr_prv;
|
2071 |
|
|
end if;
|
2072 |
|
|
else -- return from "normal trap"
|
2073 |
|
|
csr.mstatus_mie <= csr.mstatus_mpie; -- restore global IRQ enable flag
|
2074 |
|
|
csr.mstatus_mpie <= '1';
|
2075 |
73 |
zero_gravi |
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
|
2076 |
59 |
zero_gravi |
csr.privilege <= csr.mstatus_mpp; -- go back to previous privilege mode
|
2077 |
73 |
zero_gravi |
csr.mstatus_mpp <= '0'; -- MRET has to clear mstatus.MPP
|
2078 |
59 |
zero_gravi |
end if;
|
2079 |
30 |
zero_gravi |
end if;
|
2080 |
2 |
zero_gravi |
end if;
|
2081 |
59 |
zero_gravi |
|
2082 |
52 |
zero_gravi |
end if; -- /hardware csr access
|
2083 |
|
|
end if;
|
2084 |
73 |
zero_gravi |
end if;
|
2085 |
|
|
end process csr_write_access;
|
2086 |
29 |
zero_gravi |
|
2087 |
73 |
zero_gravi |
-- effective privilege mode is M when in debug mode --
|
2088 |
|
|
csr.privilege_eff <= priv_mode_m_c when (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1') else csr.privilege;
|
2089 |
52 |
zero_gravi |
|
2090 |
73 |
zero_gravi |
-- PMP output to bus unit --
|
2091 |
|
|
pmp_output:
|
2092 |
|
|
for i in 0 to PMP_NUM_REGIONS-1 generate
|
2093 |
|
|
pmp_addr_o(i)(data_width_c-1 downto index_size_f(PMP_MIN_GRANULARITY)) <= csr.pmpaddr(i); -- physical address
|
2094 |
|
|
pmp_ctrl_o(i) <= csr.pmpcfg(i);
|
2095 |
|
|
end generate;
|
2096 |
52 |
zero_gravi |
|
2097 |
|
|
|
2098 |
73 |
zero_gravi |
-- Control and Status Registers - Read Access ---------------------------------------------
|
2099 |
|
|
-- -------------------------------------------------------------------------------------------
|
2100 |
74 |
zero_gravi |
csr_read_access: process(clk_i)
|
2101 |
73 |
zero_gravi |
variable csr_addr_v : std_ulogic_vector(11 downto 0);
|
2102 |
|
|
begin
|
2103 |
|
|
if rising_edge(clk_i) then
|
2104 |
74 |
zero_gravi |
csr.rdata <= (others => '0'); -- default output, unimplemented CSRs read as zero
|
2105 |
73 |
zero_gravi |
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
2106 |
74 |
zero_gravi |
|
2107 |
|
|
-- AND-gate CSR read address: csr.rdata is zero if csr.re is not set --
|
2108 |
|
|
if (csr.re = '1') then
|
2109 |
|
|
csr_addr_v(11 downto 10) := csr.addr(11 downto 10);
|
2110 |
|
|
csr_addr_v(09 downto 08) := (others => csr.addr(8)); -- !!! WARNING: MACHINE (11) and USER (00) CSRS ONLY !!!
|
2111 |
|
|
csr_addr_v(07 downto 00) := csr.addr(07 downto 00);
|
2112 |
|
|
else -- reduce switching activity if not accessed
|
2113 |
|
|
csr_addr_v := (others => '0'); -- = csr_zero_c
|
2114 |
|
|
end if;
|
2115 |
73 |
zero_gravi |
case csr_addr_v is
|
2116 |
52 |
zero_gravi |
|
2117 |
74 |
zero_gravi |
-- hardware-only CSRs --
|
2118 |
|
|
-- --------------------------------------------------------------------
|
2119 |
|
|
-- when csr_zero_c => -- zero (r/-): always returns zero, only relevant for hardware-access, not visible to ISA
|
2120 |
|
|
-- csr.rdata <= (others => '0');
|
2121 |
|
|
|
2122 |
73 |
zero_gravi |
-- floating-point CSRs --
|
2123 |
|
|
-- --------------------------------------------------------------------
|
2124 |
|
|
when csr_fflags_c => -- fflags (r/w): floating-point (FPU) exception flags
|
2125 |
|
|
if (CPU_EXTENSION_RISCV_Zfinx) then csr.rdata(4 downto 0) <= csr.fflags; else NULL; end if;
|
2126 |
|
|
when csr_frm_c => -- frm (r/w): floating-point (FPU) rounding mode
|
2127 |
|
|
if (CPU_EXTENSION_RISCV_Zfinx) then csr.rdata(2 downto 0) <= csr.frm; else NULL; end if;
|
2128 |
|
|
when csr_fcsr_c => -- fcsr (r/w): floating-point (FPU) control/status (frm + fflags)
|
2129 |
|
|
if (CPU_EXTENSION_RISCV_Zfinx) then csr.rdata(7 downto 0) <= csr.frm & csr.fflags; else NULL; end if;
|
2130 |
56 |
zero_gravi |
|
2131 |
73 |
zero_gravi |
-- machine trap setup --
|
2132 |
|
|
-- --------------------------------------------------------------------
|
2133 |
74 |
zero_gravi |
when csr_mstatus_c => -- mstatus (r/w): machine status register - low word
|
2134 |
73 |
zero_gravi |
csr.rdata(03) <= csr.mstatus_mie; -- MIE
|
2135 |
|
|
csr.rdata(07) <= csr.mstatus_mpie; -- MPIE
|
2136 |
|
|
csr.rdata(12 downto 11) <= (others => csr.mstatus_mpp); -- MPP: machine previous privilege mode
|
2137 |
|
|
csr.rdata(21) <= csr.mstatus_tw and bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- TW
|
2138 |
74 |
zero_gravi |
-- when csr_mstatush_c => -- mstatush (r/w): machine status register - high word, implemented but always zero
|
2139 |
73 |
zero_gravi |
-- csr.rdata <= (others => '0');
|
2140 |
|
|
when csr_misa_c => -- misa (r/-): ISA and extensions
|
2141 |
|
|
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension
|
2142 |
|
|
csr.rdata(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- B CPU extension
|
2143 |
|
|
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
|
2144 |
|
|
csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
|
2145 |
|
|
csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
|
2146 |
|
|
csr.rdata(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension
|
2147 |
|
|
csr.rdata(20) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- U CPU extension
|
2148 |
|
|
csr.rdata(23) <= '1'; -- X CPU extension (non-standard extensions / NEORV32-specific)
|
2149 |
|
|
csr.rdata(30) <= '1'; -- 32-bit architecture (MXL lo)
|
2150 |
|
|
csr.rdata(31) <= '0'; -- 32-bit architecture (MXL hi)
|
2151 |
|
|
when csr_mie_c => -- mie (r/w): machine interrupt-enable register
|
2152 |
|
|
csr.rdata(03) <= csr.mie_msie; -- machine software IRQ enable
|
2153 |
|
|
csr.rdata(07) <= csr.mie_mtie; -- machine timer IRQ enable
|
2154 |
|
|
csr.rdata(11) <= csr.mie_meie; -- machine external IRQ enable
|
2155 |
|
|
csr.rdata(31 downto 16) <= csr.mie_firqe;
|
2156 |
|
|
when csr_mtvec_c => -- mtvec (r/w): machine trap-handler base address (for ALL exceptions)
|
2157 |
|
|
csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
2158 |
|
|
when csr_mcounteren_c => -- mcounteren (r/w): machine counter enable register, hardwired to zero if user mode is not implemented
|
2159 |
|
|
csr.rdata(0) <= csr.mcounteren_cy and bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- enable user-level access to cycle[h]
|
2160 |
|
|
csr.rdata(1) <= csr.mcounteren_tm and bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- enable user-level access to time[h]
|
2161 |
|
|
csr.rdata(2) <= csr.mcounteren_ir and bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- enable user-level access to instret[h]
|
2162 |
52 |
zero_gravi |
|
2163 |
73 |
zero_gravi |
-- machine trap handling --
|
2164 |
|
|
-- --------------------------------------------------------------------
|
2165 |
|
|
when csr_mscratch_c => -- mscratch (r/w): machine scratch register
|
2166 |
|
|
csr.rdata <= csr.mscratch;
|
2167 |
|
|
when csr_mepc_c => -- mepc (r/w): machine exception program counter
|
2168 |
|
|
csr.rdata <= csr.mepc(data_width_c-1 downto 1) & '0';
|
2169 |
|
|
when csr_mcause_c => -- mcause (r/w): machine trap cause
|
2170 |
74 |
zero_gravi |
csr.rdata(31) <= csr.mcause(5);
|
2171 |
|
|
csr.rdata(4 downto 0) <= csr.mcause(4 downto 0);
|
2172 |
73 |
zero_gravi |
when csr_mtval_c => -- mtval (r/-): machine bad address or instruction
|
2173 |
|
|
csr.rdata <= csr.mtval;
|
2174 |
|
|
when csr_mip_c => -- mip (r/w): machine interrupt pending
|
2175 |
|
|
csr.rdata(03) <= trap_ctrl.irq_buf(irq_msw_irq_c);
|
2176 |
|
|
csr.rdata(07) <= trap_ctrl.irq_buf(irq_mtime_irq_c);
|
2177 |
|
|
csr.rdata(11) <= trap_ctrl.irq_buf(irq_mext_irq_c);
|
2178 |
|
|
csr.rdata(31 downto 16) <= trap_ctrl.irq_buf(irq_firq_15_c downto irq_firq_0_c);
|
2179 |
59 |
zero_gravi |
|
2180 |
73 |
zero_gravi |
-- physical memory protection - configuration (r/w) --
|
2181 |
|
|
-- --------------------------------------------------------------------
|
2182 |
|
|
when csr_pmpcfg0_c =>
|
2183 |
|
|
if (PMP_NUM_REGIONS > 0) then
|
2184 |
|
|
if (PMP_NUM_REGIONS > 00) then csr.rdata(07 downto 00) <= csr.pmpcfg(00); end if;
|
2185 |
|
|
if (PMP_NUM_REGIONS > 01) then csr.rdata(15 downto 08) <= csr.pmpcfg(01); end if;
|
2186 |
|
|
if (PMP_NUM_REGIONS > 02) then csr.rdata(23 downto 16) <= csr.pmpcfg(02); end if;
|
2187 |
|
|
if (PMP_NUM_REGIONS > 03) then csr.rdata(31 downto 24) <= csr.pmpcfg(03); end if;
|
2188 |
|
|
else NULL; end if;
|
2189 |
|
|
when csr_pmpcfg1_c =>
|
2190 |
|
|
if (PMP_NUM_REGIONS > 4) then
|
2191 |
|
|
if (PMP_NUM_REGIONS > 04) then csr.rdata(07 downto 00) <= csr.pmpcfg(04); end if;
|
2192 |
|
|
if (PMP_NUM_REGIONS > 05) then csr.rdata(15 downto 08) <= csr.pmpcfg(05); end if;
|
2193 |
|
|
if (PMP_NUM_REGIONS > 06) then csr.rdata(23 downto 16) <= csr.pmpcfg(06); end if;
|
2194 |
|
|
if (PMP_NUM_REGIONS > 07) then csr.rdata(31 downto 24) <= csr.pmpcfg(07); end if;
|
2195 |
|
|
else NULL; end if;
|
2196 |
|
|
when csr_pmpcfg2_c =>
|
2197 |
|
|
if (PMP_NUM_REGIONS > 8) then
|
2198 |
|
|
if (PMP_NUM_REGIONS > 08) then csr.rdata(07 downto 00) <= csr.pmpcfg(08); end if;
|
2199 |
|
|
if (PMP_NUM_REGIONS > 09) then csr.rdata(15 downto 08) <= csr.pmpcfg(09); end if;
|
2200 |
|
|
if (PMP_NUM_REGIONS > 10) then csr.rdata(23 downto 16) <= csr.pmpcfg(10); end if;
|
2201 |
|
|
if (PMP_NUM_REGIONS > 11) then csr.rdata(31 downto 24) <= csr.pmpcfg(11); end if;
|
2202 |
|
|
else NULL; end if;
|
2203 |
|
|
when csr_pmpcfg3_c =>
|
2204 |
|
|
if (PMP_NUM_REGIONS > 12) then
|
2205 |
|
|
if (PMP_NUM_REGIONS > 12) then csr.rdata(07 downto 00) <= csr.pmpcfg(12); end if;
|
2206 |
|
|
if (PMP_NUM_REGIONS > 13) then csr.rdata(15 downto 08) <= csr.pmpcfg(13); end if;
|
2207 |
|
|
if (PMP_NUM_REGIONS > 14) then csr.rdata(23 downto 16) <= csr.pmpcfg(14); end if;
|
2208 |
|
|
if (PMP_NUM_REGIONS > 15) then csr.rdata(31 downto 24) <= csr.pmpcfg(15); end if;
|
2209 |
|
|
else NULL; end if;
|
2210 |
72 |
zero_gravi |
|
2211 |
73 |
zero_gravi |
-- physical memory protection - addresses (r/w) --
|
2212 |
|
|
-- --------------------------------------------------------------------
|
2213 |
|
|
when csr_pmpaddr0_c => if (PMP_NUM_REGIONS > 00) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(00); else NULL; end if;
|
2214 |
|
|
when csr_pmpaddr1_c => if (PMP_NUM_REGIONS > 01) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(01); else NULL; end if;
|
2215 |
|
|
when csr_pmpaddr2_c => if (PMP_NUM_REGIONS > 02) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(02); else NULL; end if;
|
2216 |
|
|
when csr_pmpaddr3_c => if (PMP_NUM_REGIONS > 03) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(03); else NULL; end if;
|
2217 |
|
|
when csr_pmpaddr4_c => if (PMP_NUM_REGIONS > 04) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(04); else NULL; end if;
|
2218 |
|
|
when csr_pmpaddr5_c => if (PMP_NUM_REGIONS > 05) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(05); else NULL; end if;
|
2219 |
|
|
when csr_pmpaddr6_c => if (PMP_NUM_REGIONS > 06) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(06); else NULL; end if;
|
2220 |
|
|
when csr_pmpaddr7_c => if (PMP_NUM_REGIONS > 07) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(07); else NULL; end if;
|
2221 |
|
|
when csr_pmpaddr8_c => if (PMP_NUM_REGIONS > 08) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(08); else NULL; end if;
|
2222 |
|
|
when csr_pmpaddr9_c => if (PMP_NUM_REGIONS > 09) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(09); else NULL; end if;
|
2223 |
|
|
when csr_pmpaddr10_c => if (PMP_NUM_REGIONS > 10) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(10); else NULL; end if;
|
2224 |
|
|
when csr_pmpaddr11_c => if (PMP_NUM_REGIONS > 11) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(11); else NULL; end if;
|
2225 |
|
|
when csr_pmpaddr12_c => if (PMP_NUM_REGIONS > 12) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(12); else NULL; end if;
|
2226 |
|
|
when csr_pmpaddr13_c => if (PMP_NUM_REGIONS > 13) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(13); else NULL; end if;
|
2227 |
|
|
when csr_pmpaddr14_c => if (PMP_NUM_REGIONS > 14) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(14); else NULL; end if;
|
2228 |
|
|
when csr_pmpaddr15_c => if (PMP_NUM_REGIONS > 15) then csr.rdata(data_width_c-3 downto index_size_f(PMP_MIN_GRANULARITY)-2) <= csr.pmpaddr(15); else NULL; end if;
|
2229 |
2 |
zero_gravi |
|
2230 |
73 |
zero_gravi |
-- machine counter setup --
|
2231 |
|
|
-- --------------------------------------------------------------------
|
2232 |
|
|
when csr_mcountinhibit_c => -- mcountinhibit (r/w): machine counter-inhibit register
|
2233 |
|
|
csr.rdata(0) <= csr.mcountinhibit_cy; -- enable auto-increment of [m]cycle[h] counter
|
2234 |
|
|
csr.rdata(2) <= csr.mcountinhibit_ir; -- enable auto-increment of [m]instret[h] counter
|
2235 |
|
|
if (HPM_NUM_CNTS > 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then -- any HPMs available?
|
2236 |
|
|
csr.rdata(csr.mcountinhibit_hpm'left+3 downto 3) <= csr.mcountinhibit_hpm; -- enable auto-increment of [m]hpmcounterx[h] counter
|
2237 |
|
|
end if;
|
2238 |
40 |
zero_gravi |
|
2239 |
73 |
zero_gravi |
-- machine performance-monitoring event selector (r/w) --
|
2240 |
|
|
-- --------------------------------------------------------------------
|
2241 |
|
|
when csr_mhpmevent3_c => if (HPM_NUM_CNTS > 00) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(00); else NULL; end if;
|
2242 |
|
|
when csr_mhpmevent4_c => if (HPM_NUM_CNTS > 01) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(01); else NULL; end if;
|
2243 |
|
|
when csr_mhpmevent5_c => if (HPM_NUM_CNTS > 02) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(02); else NULL; end if;
|
2244 |
|
|
when csr_mhpmevent6_c => if (HPM_NUM_CNTS > 03) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(03); else NULL; end if;
|
2245 |
|
|
when csr_mhpmevent7_c => if (HPM_NUM_CNTS > 04) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(04); else NULL; end if;
|
2246 |
|
|
when csr_mhpmevent8_c => if (HPM_NUM_CNTS > 05) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(05); else NULL; end if;
|
2247 |
|
|
when csr_mhpmevent9_c => if (HPM_NUM_CNTS > 06) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(06); else NULL; end if;
|
2248 |
|
|
when csr_mhpmevent10_c => if (HPM_NUM_CNTS > 07) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(07); else NULL; end if;
|
2249 |
|
|
when csr_mhpmevent11_c => if (HPM_NUM_CNTS > 08) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(08); else NULL; end if;
|
2250 |
|
|
when csr_mhpmevent12_c => if (HPM_NUM_CNTS > 09) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(09); else NULL; end if;
|
2251 |
|
|
when csr_mhpmevent13_c => if (HPM_NUM_CNTS > 10) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(10); else NULL; end if;
|
2252 |
|
|
when csr_mhpmevent14_c => if (HPM_NUM_CNTS > 11) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(11); else NULL; end if;
|
2253 |
|
|
when csr_mhpmevent15_c => if (HPM_NUM_CNTS > 12) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(12); else NULL; end if;
|
2254 |
|
|
when csr_mhpmevent16_c => if (HPM_NUM_CNTS > 13) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(13); else NULL; end if;
|
2255 |
|
|
when csr_mhpmevent17_c => if (HPM_NUM_CNTS > 14) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(14); else NULL; end if;
|
2256 |
|
|
when csr_mhpmevent18_c => if (HPM_NUM_CNTS > 15) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(15); else NULL; end if;
|
2257 |
|
|
when csr_mhpmevent19_c => if (HPM_NUM_CNTS > 16) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(16); else NULL; end if;
|
2258 |
|
|
when csr_mhpmevent20_c => if (HPM_NUM_CNTS > 17) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(17); else NULL; end if;
|
2259 |
|
|
when csr_mhpmevent21_c => if (HPM_NUM_CNTS > 18) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(18); else NULL; end if;
|
2260 |
|
|
when csr_mhpmevent22_c => if (HPM_NUM_CNTS > 19) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(19); else NULL; end if;
|
2261 |
|
|
when csr_mhpmevent23_c => if (HPM_NUM_CNTS > 20) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(20); else NULL; end if;
|
2262 |
|
|
when csr_mhpmevent24_c => if (HPM_NUM_CNTS > 21) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(21); else NULL; end if;
|
2263 |
|
|
when csr_mhpmevent25_c => if (HPM_NUM_CNTS > 22) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(22); else NULL; end if;
|
2264 |
|
|
when csr_mhpmevent26_c => if (HPM_NUM_CNTS > 23) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(23); else NULL; end if;
|
2265 |
|
|
when csr_mhpmevent27_c => if (HPM_NUM_CNTS > 24) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(24); else NULL; end if;
|
2266 |
|
|
when csr_mhpmevent28_c => if (HPM_NUM_CNTS > 25) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(25); else NULL; end if;
|
2267 |
|
|
when csr_mhpmevent29_c => if (HPM_NUM_CNTS > 26) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(26); else NULL; end if;
|
2268 |
|
|
when csr_mhpmevent30_c => if (HPM_NUM_CNTS > 27) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(27); else NULL; end if;
|
2269 |
|
|
when csr_mhpmevent31_c => if (HPM_NUM_CNTS > 28) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmevent_rd(28); else NULL; end if;
|
2270 |
42 |
zero_gravi |
|
2271 |
73 |
zero_gravi |
-- counters and timers --
|
2272 |
|
|
-- --------------------------------------------------------------------
|
2273 |
|
|
when csr_cycle_c | csr_mcycle_c => -- [m]cycle (r/w): Cycle counter LOW
|
2274 |
|
|
if (cpu_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr) then csr.rdata(cpu_cnt_lo_width_c-1 downto 0) <= csr.mcycle(cpu_cnt_lo_width_c-1 downto 0); else NULL; end if;
|
2275 |
|
|
when csr_cycleh_c | csr_mcycleh_c => -- [m]cycleh (r/w): Cycle counter HIGH
|
2276 |
|
|
if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr) then csr.rdata(cpu_cnt_hi_width_c-1 downto 0) <= csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0); else NULL; end if;
|
2277 |
|
|
|
2278 |
|
|
when csr_instret_c | csr_minstret_c => -- [m]instret (r/w): Instructions-retired counter LOW
|
2279 |
|
|
if (cpu_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr) then csr.rdata(cpu_cnt_lo_width_c-1 downto 0) <= csr.minstret(cpu_cnt_lo_width_c-1 downto 0); else NULL; end if;
|
2280 |
|
|
when csr_instreth_c | csr_minstreth_c => -- [m]instreth (r/w): Instructions-retired counter HIGH
|
2281 |
|
|
if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr) then csr.rdata(cpu_cnt_hi_width_c-1 downto 0) <= csr.minstreth(cpu_cnt_hi_width_c-1 downto 0); else NULL; end if;
|
2282 |
|
|
|
2283 |
|
|
when csr_time_c => -- time (r/-): System time LOW (from MTIME unit)
|
2284 |
|
|
if (CPU_EXTENSION_RISCV_Zicntr) then csr.rdata <= time_i(31 downto 00); else NULL; end if;
|
2285 |
|
|
when csr_timeh_c => -- timeh (r/-): System time HIGH (from MTIME unit)
|
2286 |
|
|
if (CPU_EXTENSION_RISCV_Zicntr) then csr.rdata <= time_i(63 downto 32); else NULL; end if;
|
2287 |
|
|
|
2288 |
|
|
-- hardware performance counters --
|
2289 |
|
|
-- --------------------------------------------------------------------
|
2290 |
|
|
-- low word (r/w) --
|
2291 |
|
|
when csr_mhpmcounter3_c | csr_hpmcounter3_c => if (HPM_NUM_CNTS > 00) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(00); else NULL; end if;
|
2292 |
|
|
when csr_mhpmcounter4_c | csr_hpmcounter4_c => if (HPM_NUM_CNTS > 01) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(01); else NULL; end if;
|
2293 |
|
|
when csr_mhpmcounter5_c | csr_hpmcounter5_c => if (HPM_NUM_CNTS > 02) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(02); else NULL; end if;
|
2294 |
|
|
when csr_mhpmcounter6_c | csr_hpmcounter6_c => if (HPM_NUM_CNTS > 03) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(03); else NULL; end if;
|
2295 |
|
|
when csr_mhpmcounter7_c | csr_hpmcounter7_c => if (HPM_NUM_CNTS > 04) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(04); else NULL; end if;
|
2296 |
|
|
when csr_mhpmcounter8_c | csr_hpmcounter8_c => if (HPM_NUM_CNTS > 05) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(05); else NULL; end if;
|
2297 |
|
|
when csr_mhpmcounter9_c | csr_hpmcounter9_c => if (HPM_NUM_CNTS > 06) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(06); else NULL; end if;
|
2298 |
|
|
when csr_mhpmcounter10_c | csr_hpmcounter10_c => if (HPM_NUM_CNTS > 07) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(07); else NULL; end if;
|
2299 |
|
|
when csr_mhpmcounter11_c | csr_hpmcounter11_c => if (HPM_NUM_CNTS > 08) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(08); else NULL; end if;
|
2300 |
|
|
when csr_mhpmcounter12_c | csr_hpmcounter12_c => if (HPM_NUM_CNTS > 09) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(09); else NULL; end if;
|
2301 |
|
|
when csr_mhpmcounter13_c | csr_hpmcounter13_c => if (HPM_NUM_CNTS > 10) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(10); else NULL; end if;
|
2302 |
|
|
when csr_mhpmcounter14_c | csr_hpmcounter14_c => if (HPM_NUM_CNTS > 11) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(11); else NULL; end if;
|
2303 |
|
|
when csr_mhpmcounter15_c | csr_hpmcounter15_c => if (HPM_NUM_CNTS > 12) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(12); else NULL; end if;
|
2304 |
|
|
when csr_mhpmcounter16_c | csr_hpmcounter16_c => if (HPM_NUM_CNTS > 13) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(13); else NULL; end if;
|
2305 |
|
|
when csr_mhpmcounter17_c | csr_hpmcounter17_c => if (HPM_NUM_CNTS > 14) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(14); else NULL; end if;
|
2306 |
|
|
when csr_mhpmcounter18_c | csr_hpmcounter18_c => if (HPM_NUM_CNTS > 15) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(15); else NULL; end if;
|
2307 |
|
|
when csr_mhpmcounter19_c | csr_hpmcounter19_c => if (HPM_NUM_CNTS > 16) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(16); else NULL; end if;
|
2308 |
|
|
when csr_mhpmcounter20_c | csr_hpmcounter20_c => if (HPM_NUM_CNTS > 17) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(17); else NULL; end if;
|
2309 |
|
|
when csr_mhpmcounter21_c | csr_hpmcounter21_c => if (HPM_NUM_CNTS > 18) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(18); else NULL; end if;
|
2310 |
|
|
when csr_mhpmcounter22_c | csr_hpmcounter22_c => if (HPM_NUM_CNTS > 19) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(19); else NULL; end if;
|
2311 |
|
|
when csr_mhpmcounter23_c | csr_hpmcounter23_c => if (HPM_NUM_CNTS > 20) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(20); else NULL; end if;
|
2312 |
|
|
when csr_mhpmcounter24_c | csr_hpmcounter24_c => if (HPM_NUM_CNTS > 21) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(21); else NULL; end if;
|
2313 |
|
|
when csr_mhpmcounter25_c | csr_hpmcounter25_c => if (HPM_NUM_CNTS > 22) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(22); else NULL; end if;
|
2314 |
|
|
when csr_mhpmcounter26_c | csr_hpmcounter26_c => if (HPM_NUM_CNTS > 23) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(23); else NULL; end if;
|
2315 |
|
|
when csr_mhpmcounter27_c | csr_hpmcounter27_c => if (HPM_NUM_CNTS > 24) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(24); else NULL; end if;
|
2316 |
|
|
when csr_mhpmcounter28_c | csr_hpmcounter28_c => if (HPM_NUM_CNTS > 25) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(25); else NULL; end if;
|
2317 |
|
|
when csr_mhpmcounter29_c | csr_hpmcounter29_c => if (HPM_NUM_CNTS > 26) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(26); else NULL; end if;
|
2318 |
|
|
when csr_mhpmcounter30_c | csr_hpmcounter30_c => if (HPM_NUM_CNTS > 27) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(27); else NULL; end if;
|
2319 |
|
|
when csr_mhpmcounter31_c | csr_hpmcounter31_c => if (HPM_NUM_CNTS > 28) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounter_rd(28); else NULL; end if;
|
2320 |
|
|
-- high word (r/w) --
|
2321 |
|
|
when csr_mhpmcounter3h_c | csr_hpmcounter3h_c => if (HPM_NUM_CNTS > 00) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(00); else NULL; end if;
|
2322 |
|
|
when csr_mhpmcounter4h_c | csr_hpmcounter4h_c => if (HPM_NUM_CNTS > 01) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(01); else NULL; end if;
|
2323 |
|
|
when csr_mhpmcounter5h_c | csr_hpmcounter5h_c => if (HPM_NUM_CNTS > 02) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(02); else NULL; end if;
|
2324 |
|
|
when csr_mhpmcounter6h_c | csr_hpmcounter6h_c => if (HPM_NUM_CNTS > 03) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(03); else NULL; end if;
|
2325 |
|
|
when csr_mhpmcounter7h_c | csr_hpmcounter7h_c => if (HPM_NUM_CNTS > 04) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(04); else NULL; end if;
|
2326 |
|
|
when csr_mhpmcounter8h_c | csr_hpmcounter8h_c => if (HPM_NUM_CNTS > 05) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(05); else NULL; end if;
|
2327 |
|
|
when csr_mhpmcounter9h_c | csr_hpmcounter9h_c => if (HPM_NUM_CNTS > 06) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(06); else NULL; end if;
|
2328 |
|
|
when csr_mhpmcounter10h_c | csr_hpmcounter10h_c => if (HPM_NUM_CNTS > 07) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(07); else NULL; end if;
|
2329 |
|
|
when csr_mhpmcounter11h_c | csr_hpmcounter11h_c => if (HPM_NUM_CNTS > 08) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(08); else NULL; end if;
|
2330 |
|
|
when csr_mhpmcounter12h_c | csr_hpmcounter12h_c => if (HPM_NUM_CNTS > 09) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(09); else NULL; end if;
|
2331 |
|
|
when csr_mhpmcounter13h_c | csr_hpmcounter13h_c => if (HPM_NUM_CNTS > 10) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(10); else NULL; end if;
|
2332 |
|
|
when csr_mhpmcounter14h_c | csr_hpmcounter14h_c => if (HPM_NUM_CNTS > 11) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(11); else NULL; end if;
|
2333 |
|
|
when csr_mhpmcounter15h_c | csr_hpmcounter15h_c => if (HPM_NUM_CNTS > 12) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(12); else NULL; end if;
|
2334 |
|
|
when csr_mhpmcounter16h_c | csr_hpmcounter16h_c => if (HPM_NUM_CNTS > 13) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(13); else NULL; end if;
|
2335 |
|
|
when csr_mhpmcounter17h_c | csr_hpmcounter17h_c => if (HPM_NUM_CNTS > 14) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(14); else NULL; end if;
|
2336 |
|
|
when csr_mhpmcounter18h_c | csr_hpmcounter18h_c => if (HPM_NUM_CNTS > 15) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(15); else NULL; end if;
|
2337 |
|
|
when csr_mhpmcounter19h_c | csr_hpmcounter19h_c => if (HPM_NUM_CNTS > 16) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(16); else NULL; end if;
|
2338 |
|
|
when csr_mhpmcounter20h_c | csr_hpmcounter20h_c => if (HPM_NUM_CNTS > 17) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(17); else NULL; end if;
|
2339 |
|
|
when csr_mhpmcounter21h_c | csr_hpmcounter21h_c => if (HPM_NUM_CNTS > 18) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(18); else NULL; end if;
|
2340 |
|
|
when csr_mhpmcounter22h_c | csr_hpmcounter22h_c => if (HPM_NUM_CNTS > 19) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(19); else NULL; end if;
|
2341 |
|
|
when csr_mhpmcounter23h_c | csr_hpmcounter23h_c => if (HPM_NUM_CNTS > 20) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(20); else NULL; end if;
|
2342 |
|
|
when csr_mhpmcounter24h_c | csr_hpmcounter24h_c => if (HPM_NUM_CNTS > 21) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(21); else NULL; end if;
|
2343 |
|
|
when csr_mhpmcounter25h_c | csr_hpmcounter25h_c => if (HPM_NUM_CNTS > 22) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(22); else NULL; end if;
|
2344 |
|
|
when csr_mhpmcounter26h_c | csr_hpmcounter26h_c => if (HPM_NUM_CNTS > 23) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(23); else NULL; end if;
|
2345 |
|
|
when csr_mhpmcounter27h_c | csr_hpmcounter27h_c => if (HPM_NUM_CNTS > 24) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(24); else NULL; end if;
|
2346 |
|
|
when csr_mhpmcounter28h_c | csr_hpmcounter28h_c => if (HPM_NUM_CNTS > 25) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(25); else NULL; end if;
|
2347 |
|
|
when csr_mhpmcounter29h_c | csr_hpmcounter29h_c => if (HPM_NUM_CNTS > 26) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(26); else NULL; end if;
|
2348 |
|
|
when csr_mhpmcounter30h_c | csr_hpmcounter30h_c => if (HPM_NUM_CNTS > 27) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(27); else NULL; end if;
|
2349 |
|
|
when csr_mhpmcounter31h_c | csr_hpmcounter31h_c => if (HPM_NUM_CNTS > 28) and (CPU_EXTENSION_RISCV_Zihpm) then csr.rdata <= csr.mhpmcounterh_rd(28); else NULL; end if;
|
2350 |
|
|
|
2351 |
|
|
-- machine information registers --
|
2352 |
|
|
-- --------------------------------------------------------------------
|
2353 |
|
|
-- when csr_mvendorid_c => csr.rdata <= (others => '0'); -- mvendorid (r/-): vendor ID, implemented but always zero
|
2354 |
|
|
when csr_marchid_c => csr.rdata(4 downto 0) <= "10011"; -- marchid (r/-): arch ID - official RISC-V open-source arch ID
|
2355 |
|
|
when csr_mimpid_c => csr.rdata <= hw_version_c; -- mimpid (r/-): implementation ID -- NEORV32 hardware version
|
2356 |
|
|
when csr_mhartid_c => csr.rdata <= std_ulogic_vector(to_unsigned(HW_THREAD_ID, 32)); -- mhartid (r/-): hardware thread ID
|
2357 |
|
|
-- when csr_mconfigptr_c => csr.rdata <= (others => '0'); -- mconfigptr (r/-): machine configuration pointer register, implemented but always zero
|
2358 |
|
|
|
2359 |
|
|
-- debug mode CSRs --
|
2360 |
|
|
-- --------------------------------------------------------------------
|
2361 |
|
|
when csr_dcsr_c => if (CPU_EXTENSION_RISCV_DEBUG) then csr.rdata <= csr.dcsr_rd; else NULL; end if; -- dcsr (r/w): debug mode control and status
|
2362 |
|
|
when csr_dpc_c => if (CPU_EXTENSION_RISCV_DEBUG) then csr.rdata <= csr.dpc; else NULL; end if; -- dpc (r/w): debug mode program counter
|
2363 |
|
|
when csr_dscratch0_c => if (CPU_EXTENSION_RISCV_DEBUG) then csr.rdata <= csr.dscratch0; else NULL; end if; -- dscratch0 (r/w): debug mode scratch register 0
|
2364 |
|
|
|
2365 |
|
|
-- trigger module CSRs --
|
2366 |
|
|
-- --------------------------------------------------------------------
|
2367 |
|
|
-- when csr_tselect_c => if (CPU_EXTENSION_RISCV_DEBUG) then csr.rdata <= (others => '0'); else NULL; end if; -- tselect (r/w): always zero = only 1 trigger available
|
2368 |
|
|
when csr_tdata1_c => if (CPU_EXTENSION_RISCV_DEBUG) then csr.rdata <= csr.tdata1_rd; else NULL; end if; -- tdata1 (r/w): match control
|
2369 |
|
|
when csr_tdata2_c => if (CPU_EXTENSION_RISCV_DEBUG) then csr.rdata <= csr.tdata2; else NULL; end if; -- tdata2 (r/w): address-compare
|
2370 |
|
|
-- when csr_tdata3_c => if (CPU_EXTENSION_RISCV_DEBUG) then csr.rdata <= (others => '0'); else NULL; end if; -- tdata3 (r/w): implemented but always zero
|
2371 |
|
|
when csr_tinfo_c => if (CPU_EXTENSION_RISCV_DEBUG) then csr.rdata <= x"00000004"; else NULL; end if; -- tinfo (r/w): address-match trigger only
|
2372 |
|
|
-- when csr_tcontrol_c => if (CPU_EXTENSION_RISCV_DEBUG) then csr.rdata <= (others => '0'); else NULL; end if; -- tcontrol (r/w): implemented but always zero
|
2373 |
|
|
-- when csr_mcontext_c => if (CPU_EXTENSION_RISCV_DEBUG) then csr.rdata <= (others => '0'); else NULL; end if; -- mcontext (r/w): implemented but always zero
|
2374 |
|
|
-- when csr_scontext_c => if (CPU_EXTENSION_RISCV_DEBUG) then csr.rdata <= (others => '0'); else NULL; end if; -- scontext (r/w): implemented but always zero
|
2375 |
|
|
|
2376 |
|
|
-- NEORV32-specific (RISC-V "custom") read-only CSRs --
|
2377 |
|
|
-- --------------------------------------------------------------------
|
2378 |
|
|
-- machine extended ISA extensions information --
|
2379 |
|
|
when csr_mxisa_c =>
|
2380 |
|
|
-- ISA extended (sub-)extensions --
|
2381 |
|
|
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr: privileged architecture (!!!)
|
2382 |
|
|
csr.rdata(01) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei: instruction stream sync.
|
2383 |
|
|
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zmmul); -- Zmmul: mul/div
|
2384 |
|
|
csr.rdata(03) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zxcfu); -- Zxcfu: custom RISC-V instructions
|
2385 |
|
|
csr.rdata(04) <= '0'; -- reserved
|
2386 |
|
|
csr.rdata(05) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- Zfinx: FPU using x registers, "F-alternative"
|
2387 |
|
|
csr.rdata(06) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr) and
|
2388 |
|
|
bool_to_ulogic_f(boolean(CPU_CNT_WIDTH /= 64)); -- Zxscnt: reduced-size CPU counters (from Zicntr)
|
2389 |
|
|
csr.rdata(07) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicntr); -- Zicntr: base instructions, cycle and time CSRs
|
2390 |
|
|
csr.rdata(08) <= bool_to_ulogic_f(boolean(PMP_NUM_REGIONS > 0)); -- PMP: physical memory protection (Zspmp)
|
2391 |
|
|
csr.rdata(09) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zihpm); -- Zihpm: hardware performance monitors
|
2392 |
|
|
csr.rdata(10) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG); -- RISC-V debug mode
|
2393 |
|
|
-- tuning options --
|
2394 |
|
|
csr.rdata(30) <= bool_to_ulogic_f(FAST_MUL_EN); -- DSP-based multiplication (M extensions only)
|
2395 |
|
|
csr.rdata(31) <= bool_to_ulogic_f(FAST_SHIFT_EN); -- parallel logic for shifts (barrel shifters)
|
2396 |
|
|
|
2397 |
|
|
-- undefined/unavailable --
|
2398 |
|
|
-- --------------------------------------------------------------------
|
2399 |
|
|
when others =>
|
2400 |
|
|
NULL; -- not implemented, read as zero
|
2401 |
|
|
|
2402 |
|
|
end case;
|
2403 |
|
|
end if;
|
2404 |
56 |
zero_gravi |
end if;
|
2405 |
73 |
zero_gravi |
end process csr_read_access;
|
2406 |
42 |
zero_gravi |
|
2407 |
73 |
zero_gravi |
-- CSR read data output --
|
2408 |
|
|
csr_rdata_o <= csr.rdata;
|
2409 |
|
|
|
2410 |
42 |
zero_gravi |
|
2411 |
73 |
zero_gravi |
-- ****************************************************************************************************************************
|
2412 |
|
|
-- CPU Counters / HPMs (CSRs)
|
2413 |
|
|
-- ****************************************************************************************************************************
|
2414 |
|
|
|
2415 |
42 |
zero_gravi |
-- Control and Status Registers - Counters ------------------------------------------------
|
2416 |
|
|
-- -------------------------------------------------------------------------------------------
|
2417 |
56 |
zero_gravi |
csr_counters: process(rstn_i, clk_i)
|
2418 |
42 |
zero_gravi |
begin
|
2419 |
56 |
zero_gravi |
if (rstn_i = '0') then
|
2420 |
61 |
zero_gravi |
csr.mcycle <= (others => def_rst_val_c);
|
2421 |
|
|
csr.mcycle_ovfl <= (others => def_rst_val_c);
|
2422 |
|
|
csr.mcycleh <= (others => def_rst_val_c);
|
2423 |
|
|
csr.minstret <= (others => def_rst_val_c);
|
2424 |
|
|
csr.minstret_ovfl <= (others => def_rst_val_c);
|
2425 |
|
|
csr.minstreth <= (others => def_rst_val_c);
|
2426 |
|
|
csr.mhpmcounter <= (others => (others => def_rst_val_c));
|
2427 |
|
|
csr.mhpmcounter_ovfl <= (others => (others => def_rst_val_c));
|
2428 |
|
|
csr.mhpmcounterh <= (others => (others => def_rst_val_c));
|
2429 |
56 |
zero_gravi |
elsif rising_edge(clk_i) then
|
2430 |
42 |
zero_gravi |
|
2431 |
|
|
-- [m]cycle --
|
2432 |
66 |
zero_gravi |
if (cpu_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then
|
2433 |
68 |
zero_gravi |
csr.mcycle_ovfl(0) <= csr.mcycle_nxt(csr.mcycle_nxt'left) and (not csr.mcountinhibit_cy);
|
2434 |
60 |
zero_gravi |
if (csr.we = '1') and (csr.addr = csr_mcycle_c) then -- write access
|
2435 |
61 |
zero_gravi |
csr.mcycle(cpu_cnt_lo_width_c-1 downto 0) <= csr.wdata(cpu_cnt_lo_width_c-1 downto 0);
|
2436 |
72 |
zero_gravi |
elsif (csr.mcountinhibit_cy = '0') and (cnt_event(hpmcnt_event_cy_c) = '1') and (debug_ctrl.running = '0') then -- non-inhibited automatic update and not in debug mode
|
2437 |
61 |
zero_gravi |
csr.mcycle(cpu_cnt_lo_width_c-1 downto 0) <= csr.mcycle_nxt(cpu_cnt_lo_width_c-1 downto 0);
|
2438 |
60 |
zero_gravi |
end if;
|
2439 |
|
|
else
|
2440 |
74 |
zero_gravi |
csr.mcycle_ovfl <= (others => '0');
|
2441 |
|
|
csr.mcycle <= (others => '0');
|
2442 |
42 |
zero_gravi |
end if;
|
2443 |
|
|
|
2444 |
|
|
-- [m]cycleh --
|
2445 |
66 |
zero_gravi |
if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then
|
2446 |
60 |
zero_gravi |
if (csr.we = '1') and (csr.addr = csr_mcycleh_c) then -- write access
|
2447 |
|
|
csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0) <= csr.wdata(cpu_cnt_hi_width_c-1 downto 0);
|
2448 |
68 |
zero_gravi |
else -- automatic update
|
2449 |
61 |
zero_gravi |
csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.mcycleh(cpu_cnt_hi_width_c-1 downto 0)) + unsigned(csr.mcycle_ovfl));
|
2450 |
60 |
zero_gravi |
end if;
|
2451 |
|
|
else
|
2452 |
74 |
zero_gravi |
csr.mcycleh <= (others => '0');
|
2453 |
42 |
zero_gravi |
end if;
|
2454 |
|
|
|
2455 |
60 |
zero_gravi |
|
2456 |
42 |
zero_gravi |
-- [m]instret --
|
2457 |
66 |
zero_gravi |
if (cpu_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then
|
2458 |
68 |
zero_gravi |
csr.minstret_ovfl(0) <= csr.minstret_nxt(csr.minstret_nxt'left) and (not csr.mcountinhibit_ir);
|
2459 |
60 |
zero_gravi |
if (csr.we = '1') and (csr.addr = csr_minstret_c) then -- write access
|
2460 |
61 |
zero_gravi |
csr.minstret(cpu_cnt_lo_width_c-1 downto 0) <= csr.wdata(cpu_cnt_lo_width_c-1 downto 0);
|
2461 |
72 |
zero_gravi |
elsif (csr.mcountinhibit_ir = '0') and (cnt_event(hpmcnt_event_ir_c) = '1') and (debug_ctrl.running = '0') then -- non-inhibited automatic update and not in debug mode
|
2462 |
61 |
zero_gravi |
csr.minstret(cpu_cnt_lo_width_c-1 downto 0) <= csr.minstret_nxt(cpu_cnt_lo_width_c-1 downto 0);
|
2463 |
60 |
zero_gravi |
end if;
|
2464 |
|
|
else
|
2465 |
74 |
zero_gravi |
csr.minstret_ovfl <= (others => '0');
|
2466 |
|
|
csr.minstret <= (others => '0');
|
2467 |
42 |
zero_gravi |
end if;
|
2468 |
|
|
|
2469 |
|
|
-- [m]instreth --
|
2470 |
66 |
zero_gravi |
if (cpu_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zicntr = true) then
|
2471 |
60 |
zero_gravi |
if (csr.we = '1') and (csr.addr = csr_minstreth_c) then -- write access
|
2472 |
|
|
csr.minstreth(cpu_cnt_hi_width_c-1 downto 0) <= csr.wdata(cpu_cnt_hi_width_c-1 downto 0);
|
2473 |
68 |
zero_gravi |
else -- automatic update
|
2474 |
61 |
zero_gravi |
csr.minstreth(cpu_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.minstreth(cpu_cnt_hi_width_c-1 downto 0)) + unsigned(csr.minstret_ovfl));
|
2475 |
60 |
zero_gravi |
end if;
|
2476 |
|
|
else
|
2477 |
74 |
zero_gravi |
csr.minstreth <= (others => '0');
|
2478 |
42 |
zero_gravi |
end if;
|
2479 |
|
|
|
2480 |
60 |
zero_gravi |
|
2481 |
45 |
zero_gravi |
-- [machine] hardware performance monitors (counters) --
|
2482 |
42 |
zero_gravi |
for i in 0 to HPM_NUM_CNTS-1 loop
|
2483 |
60 |
zero_gravi |
|
2484 |
|
|
-- [m]hpmcounter* --
|
2485 |
66 |
zero_gravi |
if (hpm_cnt_lo_width_c > 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then
|
2486 |
68 |
zero_gravi |
csr.mhpmcounter_ovfl(i)(0) <= csr.mhpmcounter_nxt(i)(csr.mhpmcounter_nxt(i)'left) and (not csr.mcountinhibit_hpm(i));
|
2487 |
56 |
zero_gravi |
if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3_c) + i)) then -- write access
|
2488 |
61 |
zero_gravi |
csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0) <= csr.wdata(hpm_cnt_lo_width_c-1 downto 0);
|
2489 |
56 |
zero_gravi |
elsif (csr.mcountinhibit_hpm(i) = '0') and (hpmcnt_trigger(i) = '1') then -- non-inhibited automatic update
|
2490 |
61 |
zero_gravi |
csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0) <= csr.mhpmcounter_nxt(i)(hpm_cnt_lo_width_c-1 downto 0);
|
2491 |
56 |
zero_gravi |
end if;
|
2492 |
60 |
zero_gravi |
else
|
2493 |
74 |
zero_gravi |
csr.mhpmcounter_ovfl(i) <= (others => '0');
|
2494 |
|
|
csr.mhpmcounter(i) <= (others => '0');
|
2495 |
42 |
zero_gravi |
end if;
|
2496 |
|
|
|
2497 |
|
|
-- [m]hpmcounter*h --
|
2498 |
66 |
zero_gravi |
if (hpm_cnt_hi_width_c > 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then
|
2499 |
56 |
zero_gravi |
if (csr.we = '1') and (csr.addr = std_ulogic_vector(unsigned(csr_mhpmcounter3h_c) + i)) then -- write access
|
2500 |
|
|
csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0) <= csr.wdata(hpm_cnt_hi_width_c-1 downto 0);
|
2501 |
68 |
zero_gravi |
else -- automatic update
|
2502 |
61 |
zero_gravi |
csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0) <= std_ulogic_vector(unsigned(csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0)) + unsigned(csr.mhpmcounter_ovfl(i)));
|
2503 |
56 |
zero_gravi |
end if;
|
2504 |
60 |
zero_gravi |
else
|
2505 |
74 |
zero_gravi |
csr.mhpmcounterh(i) <= (others => '0');
|
2506 |
42 |
zero_gravi |
end if;
|
2507 |
60 |
zero_gravi |
|
2508 |
34 |
zero_gravi |
end loop; -- i
|
2509 |
42 |
zero_gravi |
|
2510 |
34 |
zero_gravi |
end if;
|
2511 |
42 |
zero_gravi |
end process csr_counters;
|
2512 |
34 |
zero_gravi |
|
2513 |
61 |
zero_gravi |
-- mcycle & minstret increment LOW --
|
2514 |
68 |
zero_gravi |
csr.mcycle_nxt <= std_ulogic_vector(unsigned('0' & csr.mcycle) + 1);
|
2515 |
61 |
zero_gravi |
csr.minstret_nxt <= std_ulogic_vector(unsigned('0' & csr.minstret) + 1);
|
2516 |
|
|
|
2517 |
|
|
-- hpm counter increment LOW --
|
2518 |
|
|
hmp_cnt_lo_inc:
|
2519 |
|
|
for i in 0 to HPM_NUM_CNTS-1 generate
|
2520 |
|
|
csr.mhpmcounter_nxt(i) <= std_ulogic_vector(unsigned('0' & csr.mhpmcounter(i)) + 1);
|
2521 |
|
|
end generate;
|
2522 |
|
|
|
2523 |
|
|
|
2524 |
|
|
-- hpm counter read --
|
2525 |
42 |
zero_gravi |
hpm_rd_dummy: process(csr)
|
2526 |
|
|
begin
|
2527 |
73 |
zero_gravi |
csr.mhpmevent_rd <= (others => (others => '0'));
|
2528 |
42 |
zero_gravi |
csr.mhpmcounter_rd <= (others => (others => '0'));
|
2529 |
|
|
csr.mhpmcounterh_rd <= (others => (others => '0'));
|
2530 |
66 |
zero_gravi |
if (HPM_NUM_CNTS /= 0) and (CPU_EXTENSION_RISCV_Zihpm = true) then
|
2531 |
56 |
zero_gravi |
for i in 0 to HPM_NUM_CNTS-1 loop
|
2532 |
73 |
zero_gravi |
csr.mhpmevent_rd(i)(hpmcnt_event_size_c-1 downto 0) <= csr.mhpmevent(i);
|
2533 |
56 |
zero_gravi |
if (hpm_cnt_lo_width_c > 0) then
|
2534 |
59 |
zero_gravi |
csr.mhpmcounter_rd(i)(hpm_cnt_lo_width_c-1 downto 0) <= csr.mhpmcounter(i)(hpm_cnt_lo_width_c-1 downto 0);
|
2535 |
56 |
zero_gravi |
end if;
|
2536 |
|
|
if (hpm_cnt_hi_width_c > 0) then
|
2537 |
|
|
csr.mhpmcounterh_rd(i)(hpm_cnt_hi_width_c-1 downto 0) <= csr.mhpmcounterh(i)(hpm_cnt_hi_width_c-1 downto 0);
|
2538 |
|
|
end if;
|
2539 |
|
|
end loop; -- i
|
2540 |
|
|
end if;
|
2541 |
42 |
zero_gravi |
end process hpm_rd_dummy;
|
2542 |
34 |
zero_gravi |
|
2543 |
42 |
zero_gravi |
|
2544 |
74 |
zero_gravi |
-- Hardware Performance Monitor - Counter Event Control (Triggers) ------------------------
|
2545 |
42 |
zero_gravi |
-- -------------------------------------------------------------------------------------------
|
2546 |
73 |
zero_gravi |
hpmcnt_ctrl: process(clk_i)
|
2547 |
42 |
zero_gravi |
begin
|
2548 |
73 |
zero_gravi |
if rising_edge(clk_i) then
|
2549 |
47 |
zero_gravi |
-- enable selected triggers by ANDing actual events and according CSR configuration bits --
|
2550 |
|
|
-- OR everything to see if counter should increment --
|
2551 |
42 |
zero_gravi |
hpmcnt_trigger <= (others => '0'); -- default
|
2552 |
56 |
zero_gravi |
if (HPM_NUM_CNTS /= 0) then
|
2553 |
|
|
for i in 0 to HPM_NUM_CNTS-1 loop
|
2554 |
72 |
zero_gravi |
-- do not increment if CPU is in debug mode --
|
2555 |
74 |
zero_gravi |
if (or_reduce_f(cnt_event and csr.mhpmevent(i)(cnt_event'left downto 0)) = '1') and (debug_ctrl.running = '0') then
|
2556 |
|
|
hpmcnt_trigger(i) <= '1';
|
2557 |
|
|
else
|
2558 |
|
|
hpmcnt_trigger(i) <= '0';
|
2559 |
|
|
end if;
|
2560 |
56 |
zero_gravi |
end loop; -- i
|
2561 |
|
|
end if;
|
2562 |
42 |
zero_gravi |
end if;
|
2563 |
|
|
end process hpmcnt_ctrl;
|
2564 |
|
|
|
2565 |
74 |
zero_gravi |
hpm_triggers:
|
2566 |
|
|
if (HPM_NUM_CNTS /= 0) generate
|
2567 |
|
|
-- counter event trigger - RISC-V-specific --
|
2568 |
|
|
cnt_event(hpmcnt_event_cy_c) <= not execute_engine.sleep; -- active cycle
|
2569 |
|
|
cnt_event(hpmcnt_event_never_c) <= '0'; -- "never"
|
2570 |
|
|
cnt_event(hpmcnt_event_ir_c) <= '1' when (execute_engine.state = EXECUTE) else '0'; -- (any) retired instruction
|
2571 |
42 |
zero_gravi |
|
2572 |
74 |
zero_gravi |
-- counter event trigger - custom / NEORV32-specific --
|
2573 |
|
|
cnt_event(hpmcnt_event_cir_c) <= '1' when (execute_engine.state = EXECUTE) and (execute_engine.is_ci = '1') else '0'; -- retired compressed instruction
|
2574 |
|
|
cnt_event(hpmcnt_event_wait_if_c) <= '1' when (fetch_engine.state = IFETCH_ISSUE) and (fetch_engine.state_prev = IFETCH_ISSUE) else '0'; -- instruction fetch memory wait cycle
|
2575 |
|
|
cnt_event(hpmcnt_event_wait_ii_c) <= '1' when (execute_engine.state = DISPATCH) and (execute_engine.state_prev = DISPATCH) else '0'; -- instruction issue wait cycle
|
2576 |
|
|
cnt_event(hpmcnt_event_wait_mc_c) <= '1' when (execute_engine.state = ALU_WAIT) else '0'; -- multi-cycle alu-operation wait cycle
|
2577 |
42 |
zero_gravi |
|
2578 |
74 |
zero_gravi |
cnt_event(hpmcnt_event_load_c) <= '1' when (ctrl(ctrl_bus_rd_c) = '1') else '0'; -- load operation
|
2579 |
|
|
cnt_event(hpmcnt_event_store_c) <= '1' when (ctrl(ctrl_bus_wr_c) = '1') else '0'; -- store operation
|
2580 |
|
|
cnt_event(hpmcnt_event_wait_ls_c) <= '1' when (execute_engine.state = LOADSTORE_2) and (execute_engine.state_prev = LOADSTORE_2) else '0'; -- load/store memory wait cycle
|
2581 |
42 |
zero_gravi |
|
2582 |
74 |
zero_gravi |
cnt_event(hpmcnt_event_jump_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') else '0'; -- jump (unconditional)
|
2583 |
|
|
cnt_event(hpmcnt_event_branch_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') else '0'; -- branch (conditional, taken or not taken)
|
2584 |
|
|
cnt_event(hpmcnt_event_tbranch_c) <= '1' when (execute_engine.state = BRANCH) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '0') and (execute_engine.branch_taken = '1') else '0'; -- taken branch (conditional)
|
2585 |
42 |
zero_gravi |
|
2586 |
74 |
zero_gravi |
cnt_event(hpmcnt_event_trap_c) <= '1' when (trap_ctrl.env_start_ack = '1') else '0'; -- entered trap
|
2587 |
|
|
cnt_event(hpmcnt_event_illegal_c) <= '1' when (trap_ctrl.env_start_ack = '1') and (trap_ctrl.cause = trap_iil_c) else '0'; -- illegal operation
|
2588 |
|
|
end generate;
|
2589 |
42 |
zero_gravi |
|
2590 |
|
|
|
2591 |
71 |
zero_gravi |
-- ****************************************************************************************************************************
|
2592 |
|
|
-- CPU Debug Mode (Part of the On-Chip Debugger)
|
2593 |
|
|
-- ****************************************************************************************************************************
|
2594 |
|
|
|
2595 |
59 |
zero_gravi |
-- Debug Control --------------------------------------------------------------------------
|
2596 |
|
|
-- -------------------------------------------------------------------------------------------
|
2597 |
74 |
zero_gravi |
ocd_en:
|
2598 |
|
|
if (CPU_EXTENSION_RISCV_DEBUG = true) generate
|
2599 |
|
|
debug_control: process(rstn_i, clk_i)
|
2600 |
|
|
begin
|
2601 |
|
|
if (rstn_i = '0') then
|
2602 |
|
|
debug_ctrl.state <= DEBUG_OFFLINE;
|
2603 |
|
|
debug_ctrl.ext_halt_req <= '0';
|
2604 |
|
|
elsif rising_edge(clk_i) then
|
2605 |
68 |
zero_gravi |
-- external halt request (from Debug Module) --
|
2606 |
64 |
zero_gravi |
debug_ctrl.ext_halt_req <= db_halt_req_i;
|
2607 |
59 |
zero_gravi |
|
2608 |
|
|
-- state machine --
|
2609 |
|
|
case debug_ctrl.state is
|
2610 |
|
|
|
2611 |
|
|
when DEBUG_OFFLINE => -- not in debug mode, waiting for entering request
|
2612 |
72 |
zero_gravi |
if (debug_ctrl.trig_halt = '1') or -- external request (from DM)
|
2613 |
|
|
(debug_ctrl.trig_break = '1') or -- ebreak instruction
|
2614 |
|
|
(debug_ctrl.trig_hw = '1') or -- hardware trigger module
|
2615 |
59 |
zero_gravi |
(debug_ctrl.trig_step = '1') then -- single-stepping mode
|
2616 |
|
|
debug_ctrl.state <= DEBUG_PENDING;
|
2617 |
|
|
end if;
|
2618 |
|
|
|
2619 |
|
|
when DEBUG_PENDING => -- waiting to start debug mode
|
2620 |
|
|
if (trap_ctrl.env_start_ack = '1') and (trap_ctrl.cause(5) = '1') then -- processing trap entry into debug mode
|
2621 |
|
|
debug_ctrl.state <= DEBUG_ONLINE;
|
2622 |
|
|
end if;
|
2623 |
|
|
|
2624 |
|
|
when DEBUG_ONLINE => -- we are in debug mode
|
2625 |
|
|
if (debug_ctrl.dret = '1') then -- DRET instruction
|
2626 |
|
|
debug_ctrl.state <= DEBUG_EXIT;
|
2627 |
|
|
end if;
|
2628 |
|
|
|
2629 |
|
|
when DEBUG_EXIT => -- leaving debug mode
|
2630 |
|
|
if (execute_engine.state = TRAP_EXECUTE) then -- processing trap exit
|
2631 |
|
|
debug_ctrl.state <= DEBUG_OFFLINE;
|
2632 |
|
|
end if;
|
2633 |
|
|
|
2634 |
|
|
when others => -- undefined
|
2635 |
|
|
debug_ctrl.state <= DEBUG_OFFLINE;
|
2636 |
|
|
|
2637 |
|
|
end case;
|
2638 |
|
|
end if;
|
2639 |
74 |
zero_gravi |
end process debug_control;
|
2640 |
|
|
end generate;
|
2641 |
59 |
zero_gravi |
|
2642 |
|
|
-- state decoding --
|
2643 |
|
|
debug_ctrl.pending <= '1' when (debug_ctrl.state = DEBUG_PENDING) and (CPU_EXTENSION_RISCV_DEBUG = true) else '0';
|
2644 |
|
|
debug_ctrl.running <= '1' when ((debug_ctrl.state = DEBUG_ONLINE) or (debug_ctrl.state = DEBUG_EXIT)) and (CPU_EXTENSION_RISCV_DEBUG = true) else '0';
|
2645 |
|
|
|
2646 |
|
|
-- entry debug mode triggers --
|
2647 |
72 |
zero_gravi |
debug_ctrl.trig_hw <= hw_trigger_fire and (not debug_ctrl.running); -- enter debug mode by HW trigger module request
|
2648 |
|
|
debug_ctrl.trig_break <= trap_ctrl.break_point and (debug_ctrl.running or -- re-enter debug mode
|
2649 |
73 |
zero_gravi |
(( csr.privilege) and csr.dcsr_ebreakm) or -- enabled goto-debug-mode in machine mode on "ebreak"
|
2650 |
|
|
((not csr.privilege) and csr.dcsr_ebreaku)); -- enabled goto-debug-mode in user mode on "ebreak"
|
2651 |
72 |
zero_gravi |
debug_ctrl.trig_halt <= debug_ctrl.ext_halt_req and (not debug_ctrl.running); -- external halt request (if not halted already)
|
2652 |
|
|
debug_ctrl.trig_step <= csr.dcsr_step and (not debug_ctrl.running); -- single-step mode (trigger when NOT CURRENTLY in debug mode)
|
2653 |
59 |
zero_gravi |
|
2654 |
|
|
|
2655 |
|
|
-- Debug Control and Status Register (dcsr) - Read-Back -----------------------------------
|
2656 |
|
|
-- -------------------------------------------------------------------------------------------
|
2657 |
71 |
zero_gravi |
csr.dcsr_rd(31 downto 28) <= "0100"; -- xdebugver: external debug support compatible to spec
|
2658 |
|
|
csr.dcsr_rd(27 downto 16) <= (others => '0'); -- reserved
|
2659 |
72 |
zero_gravi |
csr.dcsr_rd(15) <= csr.dcsr_ebreakm; -- ebreakm: what happens on ebreak in m-mode? (normal trap OR debug-enter)
|
2660 |
|
|
csr.dcsr_rd(14) <= '0'; -- ebreakh: hypervisor mode not implemented
|
2661 |
|
|
csr.dcsr_rd(13) <= '0'; -- ebreaks: supervisor mode not implemented
|
2662 |
|
|
csr.dcsr_rd(12) <= csr.dcsr_ebreaku when (CPU_EXTENSION_RISCV_U = true) else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter)
|
2663 |
|
|
csr.dcsr_rd(11) <= '0'; -- stepie: interrupts are disabled during single-stepping
|
2664 |
|
|
csr.dcsr_rd(10) <= '1'; -- stopcount: standard counters and HPMs are stopped when in debug mode
|
2665 |
|
|
csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual
|
2666 |
71 |
zero_gravi |
csr.dcsr_rd(08 downto 06) <= csr.dcsr_cause; -- debug mode entry cause
|
2667 |
72 |
zero_gravi |
csr.dcsr_rd(05) <= '0'; -- reserved
|
2668 |
|
|
csr.dcsr_rd(04) <= '0'; -- mprven: mstatus.mprv is ignored in debug mode
|
2669 |
|
|
csr.dcsr_rd(03) <= '0'; -- nmip: no pending non-maskable interrupt
|
2670 |
|
|
csr.dcsr_rd(02) <= csr.dcsr_step; -- step: single-step mode
|
2671 |
73 |
zero_gravi |
csr.dcsr_rd(01 downto 00) <= (others => csr.dcsr_prv); -- prv: privilege mode when debug mode was entered
|
2672 |
59 |
zero_gravi |
|
2673 |
|
|
|
2674 |
72 |
zero_gravi |
-- ****************************************************************************************************************************
|
2675 |
|
|
-- Hardware Trigger Module (Part of the On-Chip Debugger)
|
2676 |
|
|
-- ****************************************************************************************************************************
|
2677 |
|
|
|
2678 |
|
|
-- trigger to enter debug-mode: instruction address match (fire AFTER execution) --
|
2679 |
|
|
hw_trigger_fire <= '1' when (CPU_EXTENSION_RISCV_DEBUG = true) and (csr.tdata1_exe = '1') and
|
2680 |
74 |
zero_gravi |
(csr.tdata2(data_width_c-1 downto 1) = execute_engine.pc(data_width_c-1 downto 1)) and
|
2681 |
|
|
(execute_engine.state = EXECUTE) else '0';
|
2682 |
72 |
zero_gravi |
|
2683 |
|
|
|
2684 |
|
|
-- Match Control CSR (mcontrol @ tdata1) - Read-Back --------------------------------------
|
2685 |
|
|
-- -------------------------------------------------------------------------------------------
|
2686 |
|
|
csr.tdata1_rd(31 downto 28) <= "0010"; -- type: address(/data) match trigger
|
2687 |
|
|
csr.tdata1_rd(27) <= '1'; -- dmode: only debug-mode can write tdata* registers
|
2688 |
|
|
csr.tdata1_rd(26 downto 21) <= "000000"; -- maskmax: only exact values
|
2689 |
|
|
csr.tdata1_rd(20) <= '0'; -- hit: feature not implemented
|
2690 |
|
|
csr.tdata1_rd(19) <= '0'; -- select: fire on address match
|
2691 |
|
|
csr.tdata1_rd(18) <= '1'; -- timing: trigger **after** executing the triggering instruction
|
2692 |
|
|
csr.tdata1_rd(17 downto 16) <= "00"; -- sizelo: match against an access of any size
|
2693 |
|
|
csr.tdata1_rd(15 downto 12) <= "0001"; -- action: enter debug mode on trigger
|
2694 |
|
|
csr.tdata1_rd(11) <= '0'; -- chain: chaining not supported - there is only one trigger
|
2695 |
|
|
csr.tdata1_rd(10 downto 07) <= "0000"; -- match: only full-address-match
|
2696 |
|
|
csr.tdata1_rd(6) <= '1'; -- m: trigger enabled when in machine mode
|
2697 |
|
|
csr.tdata1_rd(5) <= '0'; -- h: hypervisor mode not supported
|
2698 |
|
|
csr.tdata1_rd(4) <= '0'; -- s: supervisor mode not supported
|
2699 |
|
|
csr.tdata1_rd(3) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- u: trigger enabled when in user mode
|
2700 |
|
|
csr.tdata1_rd(2) <= csr.tdata1_exe; -- execute: enable trigger
|
2701 |
|
|
csr.tdata1_rd(1) <= '0'; -- store: store address or data matching not supported
|
2702 |
|
|
csr.tdata1_rd(0) <= '0'; -- load: load address or data matching not supported
|
2703 |
|
|
|
2704 |
|
|
|
2705 |
2 |
zero_gravi |
end neorv32_cpu_control_rtl;
|