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ndumitrach |
//////////////////////////////////////////////////////////////////////////////////
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//
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// This file is part of the Next186 Soc PC project
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// http://opencores.org/project,next186
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//
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// Filename: cache_controller.v
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// Description: Part of the Next186 SoC PC project, cache controller
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// Version 1.0
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// Creation date: Jan2012
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//
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// Author: Nicolae Dumitrache
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// e-mail: ndumitrache@opencores.org
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//
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/////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2012 Nicolae Dumitrache
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//
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//
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///////////////////////////////////////////////////////////////////////////////////
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// Additional Comments:
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//
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// 8 lines of 256bytes each
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// preloaded with bootstrap code (last 4 lines)
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//////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module cache_controller(
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input [19:0] addr,
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output [31:0] dout,
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input [31:0]din,
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input clk, // 3xCLK
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input mreq,
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input wr,
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input [3:0]wmask,
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output ce, // clock enable for CPU
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input [31:0]ddr_din,
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output [31:0]ddr_dout,
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input ddr_clk,
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input cache_write_data, // 1 when data must be written to cache, on posedge ddr_clk
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input [5:0]lowaddr,
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output reg ddr_rd = 0,
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output reg ddr_wr = 0,
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output reg [11:0] waddr
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);
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wire [7:0]fit;
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wire [7:0]free;
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reg [15:0]cache0 = 16'h0000; // 8'b:addr, 3'b:count, 1'b:dirty
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reg [15:0]cache1 = 16'h0012; // 8'b:addr, 3'b:count, 1'b:dirty
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reg [15:0]cache2 = 16'h0024; // 8'b:addr, 3'b:count, 1'b:dirty
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reg [15:0]cache3 = 16'h0036; // 8'b:addr, 3'b:count, 1'b:dirty
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reg [15:0]cache4 = 16'hffc9; // 8'b:addr, 3'b:count, 1'b:dirty
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reg [15:0]cache5 = 16'hffdb; // 8'b:addr, 3'b:count, 1'b:dirty
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reg [15:0]cache6 = 16'hffed; // 8'b:addr, 3'b:count, 1'b:dirty
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reg [15:0]cache7 = 16'hffff; // 8'b:addr, 3'b:count, 1'b:dirty
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reg dirty;
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reg [2:0]STATE = 0;
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reg ps_lowaddr5 = 0;
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reg s_lowaddr5 = 0;
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assign fit[0] = cache0[15:4] == addr[19:8];
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assign fit[1] = cache1[15:4] == addr[19:8];
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assign fit[2] = cache2[15:4] == addr[19:8];
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assign fit[3] = cache3[15:4] == addr[19:8];
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assign fit[4] = cache4[15:4] == addr[19:8];
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assign fit[5] = cache5[15:4] == addr[19:8];
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assign fit[6] = cache6[15:4] == addr[19:8];
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assign fit[7] = cache7[15:4] == addr[19:8];
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assign free[0] = cache0[3:1] == 3'b000;
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assign free[1] = cache1[3:1] == 3'b000;
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assign free[2] = cache2[3:1] == 3'b000;
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assign free[3] = cache3[3:1] == 3'b000;
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assign free[4] = cache4[3:1] == 3'b000;
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assign free[5] = cache5[3:1] == 3'b000;
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assign free[6] = cache6[3:1] == 3'b000;
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assign free[7] = cache7[3:1] == 3'b000;
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wire hit = |fit;
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wire st0 = STATE == 0;
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assign ce = st0 && (~mreq || hit);
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wire [2:0]blk = {fit[4] | fit[5] | fit[6] | fit[7], fit[2] | fit[3] | fit[6] | fit[7], fit[1] | fit[3] | fit[5] | fit[7]};
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wire [2:0]fblk = {free[4] | free[5] | free[6] | free[7], free[2] | free[3] | free[6] | free[7], free[1] | free[3] | free[5] | free[7]};
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wire [2:0]csblk = ({3{fit[0]}} & cache0[3:1]) | ({3{fit[1]}} & cache1[3:1]) |
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({3{fit[2]}} & cache2[3:1]) | ({3{fit[3]}} & cache3[3:1]) |
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({3{fit[4]}} & cache4[3:1]) | ({3{fit[5]}} & cache5[3:1]) |
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({3{fit[6]}} & cache6[3:1]) | ({3{fit[7]}} & cache7[3:1]);
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cache cache_mem (
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.clka(ddr_clk), // input clka
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.wea({4{cache_write_data}}), // input [3 : 0] wea
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.addra({blk, lowaddr}), // input [8 : 0] addra
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.dina(ddr_din), // input [31 : 0] dina
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.douta(ddr_dout), // output [31 : 0] douta
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.clkb(clk), // input clkb
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.enb(mreq & hit & st0),
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.web(wmask), // input [3 : 0] web
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.addrb({blk, addr[7:2]}), // input [8 : 0] addrb
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.dinb(din), // input [31 : 0] dinb
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.doutb(dout) // output [31 : 0] doutb
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);
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always @(cache0, cache1, cache2, cache3, cache4, cache5, cache6, cache7) begin
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dirty = 1'bx;
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case(1)
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free[0]: begin dirty = cache0[0]; end
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free[1]: begin dirty = cache1[0]; end
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free[2]: begin dirty = cache2[0]; end
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free[3]: begin dirty = cache3[0]; end
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free[4]: begin dirty = cache4[0]; end
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free[5]: begin dirty = cache5[0]; end
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free[6]: begin dirty = cache6[0]; end
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free[7]: begin dirty = cache7[0]; end
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endcase
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end
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always @(posedge clk) begin
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ps_lowaddr5 <= lowaddr[5];
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s_lowaddr5 <= ps_lowaddr5;
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case(STATE)
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3'b000: begin
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if(mreq) begin
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if(hit) begin // cache hit
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cache0[3:1] <= fit[0] ? 3'b111 : cache0[3:1] - (cache0[3:1] > csblk);
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cache1[3:1] <= fit[1] ? 3'b111 : cache1[3:1] - (cache1[3:1] > csblk);
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cache2[3:1] <= fit[2] ? 3'b111 : cache2[3:1] - (cache2[3:1] > csblk);
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cache3[3:1] <= fit[3] ? 3'b111 : cache3[3:1] - (cache3[3:1] > csblk);
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cache4[3:1] <= fit[4] ? 3'b111 : cache4[3:1] - (cache4[3:1] > csblk);
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cache5[3:1] <= fit[5] ? 3'b111 : cache5[3:1] - (cache5[3:1] > csblk);
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cache6[3:1] <= fit[6] ? 3'b111 : cache6[3:1] - (cache6[3:1] > csblk);
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cache7[3:1] <= fit[7] ? 3'b111 : cache7[3:1] - (cache7[3:1] > csblk);
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end else begin // cache miss
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case(fblk) // free block
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0: begin waddr <= cache0[15:4]; cache0[15:4] <= addr[19:8]; end
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1: begin waddr <= cache1[15:4]; cache1[15:4] <= addr[19:8]; end
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2: begin waddr <= cache2[15:4]; cache2[15:4] <= addr[19:8]; end
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3: begin waddr <= cache3[15:4]; cache3[15:4] <= addr[19:8]; end
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4: begin waddr <= cache4[15:4]; cache4[15:4] <= addr[19:8]; end
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5: begin waddr <= cache5[15:4]; cache5[15:4] <= addr[19:8]; end
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6: begin waddr <= cache6[15:4]; cache6[15:4] <= addr[19:8]; end
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7: begin waddr <= cache7[15:4]; cache7[15:4] <= addr[19:8]; end
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endcase
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ddr_rd <= ~dirty;
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ddr_wr <= dirty;
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STATE <= dirty ? 3'b011 : 3'b100;
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end
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if(hit) case(1) // free or hit block
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fit[0]: cache0[0] <= (cache0[0] | wr);
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fit[1]: cache1[0] <= (cache1[0] | wr);
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fit[2]: cache2[0] <= (cache2[0] | wr);
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fit[3]: cache3[0] <= (cache3[0] | wr);
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fit[4]: cache4[0] <= (cache4[0] | wr);
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fit[5]: cache5[0] <= (cache5[0] | wr);
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fit[6]: cache6[0] <= (cache6[0] | wr);
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fit[7]: cache7[0] <= (cache7[0] | wr);
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endcase else case(1)
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free[0]: cache0[0] <= 0;
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free[1]: cache1[0] <= 0;
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free[2]: cache2[0] <= 0;
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free[3]: cache3[0] <= 0;
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free[4]: cache4[0] <= 0;
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free[5]: cache5[0] <= 0;
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free[6]: cache6[0] <= 0;
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free[7]: cache7[0] <= 0;
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endcase
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end
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end
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3'b011: begin // write cache to ddr
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ddr_rd <= 1'b1;
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if(s_lowaddr5) begin
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ddr_wr <= 1'b0;
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STATE <= 3'b111;
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end
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end
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3'b111: begin // read cache from ddr
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if(~s_lowaddr5) STATE <= 3'b100;
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end
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3'b100: begin
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if(s_lowaddr5) STATE <= 3'b101;
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end
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3'b101: begin
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ddr_rd <= 1'b0;
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if(~s_lowaddr5) STATE <= 3'b000;
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end
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endcase
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end
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endmodule
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module seg_map(
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input CLK,
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input [3:0]addr,
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output [9:0]rdata,
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input [9:0]wdata,
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input [3:0]addr1,
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output [9:0]data1,
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input WE
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);
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RAM16X1D #(.INIT(16'haaaa) ) RAM16X1D_inst0
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(
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.DPO(data1[0]), // Read-only 1-bit data output for DPRA
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.SPO(rdata[0]), // Rw/ 1-bit data output for A0-A3
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.A0(addr[0]), // Rw/ address[0] input bit
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.A1(addr[1]), // Rw/ address[1] input bit
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.A2(addr[2]), // Rw/ address[2] input bit
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.A3(addr[3]), // Rw/ address[3] input bit
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.D(wdata[0]), // Write 1-bit data input
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.DPRA0(addr1[0]), // Read address[0] input bit
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.DPRA1(addr1[1]), // Read address[1] input bit
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.DPRA2(addr1[2]), // Read address[2] input bit
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.DPRA3(addr1[3]), // Read address[3] input bit
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.WCLK(CLK), // Write clock input
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.WE(WE) // Write enable input
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);
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RAM16X1D #(.INIT(16'hcccc) ) RAM16X1D_inst1
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(
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.DPO(data1[1]), // Read-only 1-bit data output for DPRA
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.SPO(rdata[1]), // Rw/ 1-bit data output for A0-A3
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.A0(addr[0]), // Rw/ address[0] input bit
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.A1(addr[1]), // Rw/ address[1] input bit
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.A2(addr[2]), // Rw/ address[2] input bit
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.A3(addr[3]), // Rw/ address[3] input bit
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.D(wdata[1]), // Write 1-bit data input
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.DPRA0(addr1[0]), // Read address[0] input bit
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.DPRA1(addr1[1]), // Read address[1] input bit
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.DPRA2(addr1[2]), // Read address[2] input bit
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.DPRA3(addr1[3]), // Read address[3] input bit
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.WCLK(CLK), // Write clock input
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.WE(WE) // Write enable input
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);
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RAM16X1D #(.INIT(16'hf0f0) ) RAM16X1D_inst2
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(
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.DPO(data1[2]), // Read-only 1-bit data output for DPRA
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.SPO(rdata[2]), // Rw/ 1-bit data output for A0-A3
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.A0(addr[0]), // Rw/ address[0] input bit
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.A1(addr[1]), // Rw/ address[1] input bit
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.A2(addr[2]), // Rw/ address[2] input bit
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.A3(addr[3]), // Rw/ address[3] input bit
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.D(wdata[2]), // Write 1-bit data input
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.DPRA0(addr1[0]), // Read address[0] input bit
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.DPRA1(addr1[1]), // Read address[1] input bit
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.DPRA2(addr1[2]), // Read address[2] input bit
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.DPRA3(addr1[3]), // Read address[3] input bit
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.WCLK(CLK), // Write clock input
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.WE(WE) // Write enable input
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);
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RAM16X1D #(.INIT(16'hff00) ) RAM16X1D_inst3
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(
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.DPO(data1[3]), // Read-only 1-bit data output for DPRA
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.SPO(rdata[3]), // Rw/ 1-bit data output for A0-A3
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.A0(addr[0]), // Rw/ address[0] input bit
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.A1(addr[1]), // Rw/ address[1] input bit
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.A2(addr[2]), // Rw/ address[2] input bit
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.A3(addr[3]), // Rw/ address[3] input bit
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.D(wdata[3]), // Write 1-bit data input
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.DPRA0(addr1[0]), // Read address[0] input bit
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.DPRA1(addr1[1]), // Read address[1] input bit
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.DPRA2(addr1[2]), // Read address[2] input bit
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.DPRA3(addr1[3]), // Read address[3] input bit
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.WCLK(CLK), // Write clock input
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.WE(WE) // Write enable input
|
293 |
|
|
);
|
294 |
|
|
|
295 |
|
|
|
296 |
|
|
RAM16X1D #(.INIT(16'h0000) ) RAM16X1D_inst4
|
297 |
|
|
(
|
298 |
|
|
.DPO(data1[4]), // Read-only 1-bit data output for DPRA
|
299 |
|
|
.SPO(rdata[4]), // Rw/ 1-bit data output for A0-A3
|
300 |
|
|
.A0(addr[0]), // Rw/ address[0] input bit
|
301 |
|
|
.A1(addr[1]), // Rw/ address[1] input bit
|
302 |
|
|
.A2(addr[2]), // Rw/ address[2] input bit
|
303 |
|
|
.A3(addr[3]), // Rw/ address[3] input bit
|
304 |
|
|
.D(wdata[4]), // Write 1-bit data input
|
305 |
|
|
.DPRA0(addr1[0]), // Read address[0] input bit
|
306 |
|
|
.DPRA1(addr1[1]), // Read address[1] input bit
|
307 |
|
|
.DPRA2(addr1[2]), // Read address[2] input bit
|
308 |
|
|
.DPRA3(addr1[3]), // Read address[3] input bit
|
309 |
|
|
.WCLK(CLK), // Write clock input
|
310 |
|
|
.WE(WE) // Write enable input
|
311 |
|
|
);
|
312 |
|
|
|
313 |
|
|
RAM16X1D #(.INIT(16'h0000) ) RAM16X1D_inst5
|
314 |
|
|
(
|
315 |
|
|
.DPO(data1[5]), // Read-only 1-bit data output for DPRA
|
316 |
|
|
.SPO(rdata[5]), // Rw/ 1-bit data output for A0-A3
|
317 |
|
|
.A0(addr[0]), // Rw/ address[0] input bit
|
318 |
|
|
.A1(addr[1]), // Rw/ address[1] input bit
|
319 |
|
|
.A2(addr[2]), // Rw/ address[2] input bit
|
320 |
|
|
.A3(addr[3]), // Rw/ address[3] input bit
|
321 |
|
|
.D(wdata[5]), // Write 1-bit data input
|
322 |
|
|
.DPRA0(addr1[0]), // Read address[0] input bit
|
323 |
|
|
.DPRA1(addr1[1]), // Read address[1] input bit
|
324 |
|
|
.DPRA2(addr1[2]), // Read address[2] input bit
|
325 |
|
|
.DPRA3(addr1[3]), // Read address[3] input bit
|
326 |
|
|
.WCLK(CLK), // Write clock input
|
327 |
|
|
.WE(WE) // Write enable input
|
328 |
|
|
);
|
329 |
|
|
|
330 |
|
|
RAM16X1D #(.INIT(16'h0000) ) RAM16X1D_inst6
|
331 |
|
|
(
|
332 |
|
|
.DPO(data1[6]), // Read-only 1-bit data output for DPRA
|
333 |
|
|
.SPO(rdata[6]), // Rw/ 1-bit data output for A0-A3
|
334 |
|
|
.A0(addr[0]), // Rw/ address[0] input bit
|
335 |
|
|
.A1(addr[1]), // Rw/ address[1] input bit
|
336 |
|
|
.A2(addr[2]), // Rw/ address[2] input bit
|
337 |
|
|
.A3(addr[3]), // Rw/ address[3] input bit
|
338 |
|
|
.D(wdata[6]), // Write 1-bit data input
|
339 |
|
|
.DPRA0(addr1[0]), // Read address[0] input bit
|
340 |
|
|
.DPRA1(addr1[1]), // Read address[1] input bit
|
341 |
|
|
.DPRA2(addr1[2]), // Read address[2] input bit
|
342 |
|
|
.DPRA3(addr1[3]), // Read address[3] input bit
|
343 |
|
|
.WCLK(CLK), // Write clock input
|
344 |
|
|
.WE(WE) // Write enable input
|
345 |
|
|
);
|
346 |
|
|
|
347 |
|
|
RAM16X1D #(.INIT(16'h0000) ) RAM16X1D_inst7
|
348 |
|
|
(
|
349 |
|
|
.DPO(data1[7]), // Read-only 1-bit data output for DPRA
|
350 |
|
|
.SPO(rdata[7]), // Rw/ 1-bit data output for A0-A3
|
351 |
|
|
.A0(addr[0]), // Rw/ address[0] input bit
|
352 |
|
|
.A1(addr[1]), // Rw/ address[1] input bit
|
353 |
|
|
.A2(addr[2]), // Rw/ address[2] input bit
|
354 |
|
|
.A3(addr[3]), // Rw/ address[3] input bit
|
355 |
|
|
.D(wdata[7]), // Write 1-bit data input
|
356 |
|
|
.DPRA0(addr1[0]), // Read address[0] input bit
|
357 |
|
|
.DPRA1(addr1[1]), // Read address[1] input bit
|
358 |
|
|
.DPRA2(addr1[2]), // Read address[2] input bit
|
359 |
|
|
.DPRA3(addr1[3]), // Read address[3] input bit
|
360 |
|
|
.WCLK(CLK), // Write clock input
|
361 |
|
|
.WE(WE) // Write enable input
|
362 |
|
|
);
|
363 |
|
|
|
364 |
|
|
RAM16X1D #(.INIT(16'h0000) ) RAM16X1D_inst8
|
365 |
|
|
(
|
366 |
|
|
.DPO(data1[8]), // Read-only 1-bit data output for DPRA
|
367 |
|
|
.SPO(rdata[8]), // Rw/ 1-bit data output for A0-A3
|
368 |
|
|
.A0(addr[0]), // Rw/ address[0] input bit
|
369 |
|
|
.A1(addr[1]), // Rw/ address[1] input bit
|
370 |
|
|
.A2(addr[2]), // Rw/ address[2] input bit
|
371 |
|
|
.A3(addr[3]), // Rw/ address[3] input bit
|
372 |
|
|
.D(wdata[8]), // Write 1-bit data input
|
373 |
|
|
.DPRA0(addr1[0]), // Read address[0] input bit
|
374 |
|
|
.DPRA1(addr1[1]), // Read address[1] input bit
|
375 |
|
|
.DPRA2(addr1[2]), // Read address[2] input bit
|
376 |
|
|
.DPRA3(addr1[3]), // Read address[3] input bit
|
377 |
|
|
.WCLK(CLK), // Write clock input
|
378 |
|
|
.WE(WE) // Write enable input
|
379 |
|
|
);
|
380 |
|
|
|
381 |
|
|
RAM16X1D #(.INIT(16'h0000) ) RAM16X1D_inst9
|
382 |
|
|
(
|
383 |
|
|
.DPO(data1[9]), // Read-only 1-bit data output for DPRA
|
384 |
|
|
.SPO(rdata[9]), // Rw/ 1-bit data output for A0-A3
|
385 |
|
|
.A0(addr[0]), // Rw/ address[0] input bit
|
386 |
|
|
.A1(addr[1]), // Rw/ address[1] input bit
|
387 |
|
|
.A2(addr[2]), // Rw/ address[2] input bit
|
388 |
|
|
.A3(addr[3]), // Rw/ address[3] input bit
|
389 |
|
|
.D(wdata[9]), // Write 1-bit data input
|
390 |
|
|
.DPRA0(addr1[0]), // Read address[0] input bit
|
391 |
|
|
.DPRA1(addr1[1]), // Read address[1] input bit
|
392 |
|
|
.DPRA2(addr1[2]), // Read address[2] input bit
|
393 |
|
|
.DPRA3(addr1[3]), // Read address[3] input bit
|
394 |
|
|
.WCLK(CLK), // Write clock input
|
395 |
|
|
.WE(WE) // Write enable input
|
396 |
|
|
);
|
397 |
|
|
endmodule
|