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//   ____  ____

//  /   /\/   /

// /___/  \  /   Vendor             : Xilinx

// \   \   \/    Version            : 3.6.1

//  \   \        Application        : MIG

//  /   /        Filename           : ddr_data_read_0.v

// /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:41 $

// \   \  /  \   Date Created       : Mon May 2 2005

//  \___\/\___\

// Device       : Spartan-3/3A/3A-DSP

// Design Name  : DDR2 SDRAM

// Purpose      : ram8d modules are instantiated for Read data FIFOs. RAM8D is 

//                each 8 bits or 4 bits depending on number data bits per strobe.

//                Each strobe  will have two instances, one for rising edge data

//                and one for falling edge data. 

//*****************************************************************************

`timescale 1ns/100ps

`include "../rtl/ddr_parameters_0.v"

module ddr_data_read_0

  (

   input                              clk90,

   input                              reset90,

   input [(`DATA_WIDTH-1):0]          ddr_dq_in,

   input [(`DATA_STROBE_WIDTH-1):0]   fifo_0_wr_en,

   input [(`DATA_STROBE_WIDTH-1):0]   fifo_1_wr_en,

   input [(4*`DATA_STROBE_WIDTH)-1:0] fifo_0_wr_addr ,

   input [(4*`DATA_STROBE_WIDTH)-1:0] fifo_1_wr_addr ,

   input [(`DATA_STROBE_WIDTH-1):0]   dqs_delayed_col0,

   input [(`DATA_STROBE_WIDTH-1):0]   dqs_delayed_col1,

   input                              read_fifo_rden,

   output [((`DATA_WIDTH*2)-1):0]     user_output_data,

   output                             u_data_val

   );

   reg                                reset90_r;

   reg [(4*`DATA_STROBE_WIDTH)-1:0]   fifo0_rd_addr_r

                                        /* synthesis syn_preserve=1 */;

   reg [(4*`DATA_STROBE_WIDTH)-1:0]   fifo1_rd_addr_r

                                        /* synthesis syn_preserve=1 */;

   reg [`DATA_WIDTH-1:0]               fifo_0_data_out_r

                                        /* synthesis syn_preserve=1 */;

   reg [`DATA_WIDTH-1:0]               fifo_1_data_out_r

                                        /* synthesis syn_preserve=1 */;

   reg [((`DATA_WIDTH*2)-1):0]         first_sdr_data;

   reg                               read_fifo_rden_90r1;

   reg                               read_fifo_rden_90r2;

   reg                               read_fifo_rden_90r3;

   reg                               read_fifo_rden_90r4;

   reg                               read_fifo_rden_90r5;

   reg                               read_fifo_rden_90r6;

   wire [3:0]                          fifo0_rd_addr;

   wire [3:0]                          fifo1_rd_addr;

   wire [`DATA_WIDTH-1:0]              fifo_0_data_out;

   wire [`DATA_WIDTH-1:0]              fifo_1_data_out;

   wire [(`DATA_STROBE_WIDTH-1):0]    dqs_delayed_col0_n;

   wire [(`DATA_STROBE_WIDTH-1):0]    dqs_delayed_col1_n;

   assign dqs_delayed_col0_n  = ~ dqs_delayed_col0;

   assign dqs_delayed_col1_n  = ~ dqs_delayed_col1;

   assign user_output_data    = first_sdr_data;

   assign u_data_val          = read_fifo_rden_90r6;

   always @( posedge clk90 )

     reset90_r <= reset90;

  // Read fifo read enable signal phase is changed from 180 to 90 clock domain 

   always@(posedge clk90) begin

      if(reset90_r)begin

         read_fifo_rden_90r1 <= 1'b0;

         read_fifo_rden_90r2 <= 1'b0;

         read_fifo_rden_90r3 <= 1'b0;

         read_fifo_rden_90r4 <= 1'b0;

         read_fifo_rden_90r5 <= 1'b0;

         read_fifo_rden_90r6 <= 1'b0;

      end

      else begin

         read_fifo_rden_90r1 <= read_fifo_rden;

         read_fifo_rden_90r2 <= read_fifo_rden_90r1;

         read_fifo_rden_90r3 <= read_fifo_rden_90r2;

         read_fifo_rden_90r4 <= read_fifo_rden_90r3;

         read_fifo_rden_90r5 <= read_fifo_rden_90r4;

         read_fifo_rden_90r6 <= read_fifo_rden_90r5;

      end

   end

   always@(posedge clk90) begin

     fifo_0_data_out_r <= fifo_0_data_out;

     fifo_1_data_out_r <= fifo_1_data_out;

   end

   genvar addr_i;

   generate for(addr_i = 0; addr_i < `DATA_STROBE_WIDTH;  addr_i = addr_i + 1) begin: gen_rd_addr

      always@(posedge clk90) begin

         fifo0_rd_addr_r[addr_i*4+:4] <= fifo0_rd_addr;

         fifo1_rd_addr_r[addr_i*4+:4] <= fifo1_rd_addr;

      end

   end

   endgenerate

   always@(posedge clk90)begin

      if(reset90_r)

        first_sdr_data       <= {(`DATA_WIDTH*2){1'b0}};

      else if(read_fifo_rden_90r5)

         first_sdr_data  <= {fifo_0_data_out_r, fifo_1_data_out_r};

   end

   ddr_rd_gray_cntr fifo0_rd_addr_inst

     (

      .clk90    (clk90),

      .reset90  (reset90),

      .cnt_en   (read_fifo_rden_90r3),

      .rgc_gcnt (fifo0_rd_addr)

      );

   ddr_rd_gray_cntr fifo1_rd_addr_inst

     (

      .clk90    (clk90),

      .reset90  (reset90),

      .cnt_en   (read_fifo_rden_90r3),

      .rgc_gcnt (fifo1_rd_addr)

       );

   genvar strobe_i;

   generate for(strobe_i = 0; strobe_i < `DATA_STROBE_WIDTH;  strobe_i = strobe_i + 1)

     begin: gen_strobe

      ddr_ram8d_0 strobe

        (

          .dout  (fifo_0_data_out[strobe_i*`DATABITSPERSTROBE+:`DATABITSPERSTROBE]),

          .waddr (fifo_0_wr_addr[strobe_i*4+:4]),

          .din   (ddr_dq_in[strobe_i*`DATABITSPERSTROBE+:`DATABITSPERSTROBE]),

          .raddr (fifo0_rd_addr_r[strobe_i*4+:4]),

          .wclk0 (dqs_delayed_col0[strobe_i]),

          .wclk1 (dqs_delayed_col1[strobe_i]),

          .we    (fifo_0_wr_en[strobe_i])

          );

      ddr_ram8d_0 strobe_n

        (

          .dout  (fifo_1_data_out[strobe_i*`DATABITSPERSTROBE+:`DATABITSPERSTROBE]),

          .waddr (fifo_1_wr_addr[strobe_i*4+:4]),

          .din   (ddr_dq_in[strobe_i*`DATABITSPERSTROBE+:`DATABITSPERSTROBE]),

          .raddr (fifo1_rd_addr_r[strobe_i*4+:4]),

          .wclk0 (dqs_delayed_col0_n[strobe_i]),

          .wclk1 (dqs_delayed_col1_n[strobe_i]),

          .we    (fifo_1_wr_en[strobe_i])

          );

   end

   endgenerate

endmodule