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ndumitrach |
//*****************************************************************************
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// DISCLAIMER OF LIABILITY
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//
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// This file contains proprietary and confidential information of
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// Xilinx, Inc. ("Xilinx"), that is distributed under a license
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// from Xilinx, and may be used, copied and/or disclosed only
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// pursuant to the terms of a valid license agreement with Xilinx.
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//
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// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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// does not warrant that functions included in the Materials will
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// meet the requirements of Licensee, or that the operation of the
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// Materials will be uninterrupted or error-free, or that defects
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// in the Materials will be corrected. Furthermore, Xilinx does
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// not warrant or make any representations regarding use, or the
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// results of the use, of the Materials in terms of correctness,
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// accuracy, reliability or otherwise.
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//
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// Xilinx products are not designed or intended to be fail-safe,
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// or for use in any application requiring fail-safe performance,
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// such as life-support or safety devices or systems, Class III
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// medical devices, nuclear facilities, applications related to
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// the deployment of airbags, or any other applications that could
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// lead to death, personal injury or severe property or
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// environmental damage (individually and collectively, "critical
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// applications"). Customer assumes the sole risk and liability
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// of any use of Xilinx products in critical applications,
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// subject only to applicable laws and regulations governing
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// limitations on product liability.
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//
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// Copyright 2005, 2006, 2007 Xilinx, Inc.
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// All rights reserved.
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//
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// This disclaimer and copyright notice must be retained as part
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// of this file at all times.
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 3.6.1
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// \ \ Application : MIG
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// / / Filename : ddr_infrastructure_top.v
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// /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:41 $
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// \ \ / \ Date Created : Mon May 2 2005
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// \___\/\___\
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// Device : Spartan-3/3A/3A-DSP
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// Design Name : DDR2 SDRAM
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// Purpose : This module has instantiation cal_top and generate reset
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// signals.
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//*****************************************************************************
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`timescale 1ns/100ps
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`include "../rtl/ddr_parameters_0.v"
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module ddr_infrastructure_top0
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(
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input clk_int,
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input clk90_int,
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input reset_in_n,
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input dcm_lock,
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output [4:0] delay_sel_val1_val,
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output sys_rst_val,
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output sys_rst90_val,
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output sys_rst180_val,
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output reg wait_200us_rout,
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// debug signals
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output [4:0] dbg_phase_cnt,
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output [5:0] dbg_cnt,
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output dbg_trans_onedtct,
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output dbg_trans_twodtct,
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output dbg_enb_trans_two_dtct
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);
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reg sys_rst_o;
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reg sys_rst_1;
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reg sys_rst;
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reg sys_rst90_o;
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reg sys_rst90_1;
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reg sys_rst90;
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reg sys_rst180_o;
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reg sys_rst180_1;
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reg sys_rst180;
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reg [15:0] counter200;
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reg wait_200us;
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reg wait_clk90;
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reg wait_clk270;
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reg wait_200us_r;
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wire clk_int_val1;
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wire clk_int_val2;
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wire clk90_int_val1;
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wire clk90_int_val2;
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wire [4:0] delay_sel_val;
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wire user_rst;
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wire sys_clk_ibuf;
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wire user_cal_rst;
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assign clk_int_val = clk_int;
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assign clk90_int_val = clk90_int;
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assign sys_rst_val = sys_rst;
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assign sys_rst90_val = sys_rst90;
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assign sys_rst180_val = sys_rst180;
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assign delay_sel_val1_val = delay_sel_val;
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assign clk_int_val1 = clk_int;
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assign clk90_int_val1 = clk90_int;
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assign clk_int_val2 = clk_int_val1;
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assign clk90_int_val2 = clk90_int_val1;
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assign user_rst = `RESET_ACTIVE_LOW == 1'b1 ?
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~reset_in_n : reset_in_n;
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assign user_cal_rst = `RESET_ACTIVE_LOW == 1'b1 ?
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reset_in_n : ~reset_in_n;
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always @(posedge clk_int_val2) begin
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if(user_rst == 1'b1 || dcm_lock == 1'b0) begin
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wait_200us <= 1'b1;
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counter200 <= 16'd0;
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end
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else
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`ifdef simulation
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wait_200us <= 1'b0;
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`else
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if ( counter200 < 16'd33400 ) begin
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counter200 <= counter200 + 1'b1;
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wait_200us <= 1'b1;
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end
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else begin
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counter200 <= counter200;
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wait_200us <= 1'b0;
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end
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`endif
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end
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always @( posedge clk_int_val2 )
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wait_200us_r <= wait_200us;
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always @( posedge clk_int_val2 )
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wait_200us_rout <= wait_200us;
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always @(negedge clk90_int_val2) begin
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if(user_rst == 1'b1 || dcm_lock == 1'b0)
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wait_clk270 <= 1'b1;
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else
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wait_clk270 <= wait_200us_r;
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end
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always @(posedge clk90_int_val2) begin
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wait_clk90 <= wait_clk270;
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end
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always@(posedge clk_int_val2) begin
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if(user_rst == 1'b1 || dcm_lock == 1'b0 || wait_200us_r == 1'b1 ) begin
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sys_rst_o <= 1'b1;
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sys_rst_1 <= 1'b1;
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sys_rst <= 1'b1;
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end
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else begin
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sys_rst_o <= 1'b0;
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sys_rst_1 <= sys_rst_o;
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sys_rst <= sys_rst_1;
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end
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end
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always@(posedge clk90_int_val2) begin
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if (user_rst == 1'b1 || dcm_lock == 1'b0 || wait_clk90 == 1'b1) begin
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sys_rst90_o <= 1'b1;
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sys_rst90_1 <= 1'b1;
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sys_rst90 <= 1'b1;
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end
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else begin
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sys_rst90_o <= 1'b0;
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sys_rst90_1 <= sys_rst90_o;
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sys_rst90 <= sys_rst90_1;
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end
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end
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always@(negedge clk_int_val2) begin
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if (user_rst == 1'b1 || dcm_lock == 1'b0 || wait_clk270 == 1'b1) begin
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sys_rst180_o <= 1'b1;
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sys_rst180_1 <= 1'b1;
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sys_rst180 <= 1'b1;
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end
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else begin
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sys_rst180_o <= 1'b0;
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sys_rst180_1 <= sys_rst180_o;
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sys_rst180 <= sys_rst180_1;
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end
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end
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ddr_cal_top cal_top0 (
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.clk0 (clk_int_val2),
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.clk0dcmlock (dcm_lock),
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.reset (user_cal_rst),
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.tapfordqs (delay_sel_val),
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.dbg_phase_cnt (dbg_phase_cnt),
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.dbg_cnt (dbg_cnt),
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.dbg_trans_onedtct (dbg_trans_onedtct),
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.dbg_trans_twodtct (dbg_trans_twodtct),
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.dbg_enb_trans_two_dtct (dbg_enb_trans_two_dtct)
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);
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endmodule
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