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-- ------------------------------------------------------------------------

-- Copyright (C) 2010 Arif Endro Nugroho

-- All rights reserved.

-- 

-- Redistribution and use in source and binary forms, with or without

-- modification, are permitted provided that the following conditions

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-- 1. Redistributions of source code must retain the above copyright

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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS

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-- ------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity mulx is

  port (

  V                : in  bit_vector (  7 downto 0);

  c                : in  bit_vector (  7 downto 0);

  w                : out bit_vector (  7 downto 0)

  );

end mulx;

architecture phy of mulx is

begin

--MULx(V,c)        == (      V<<1          ) xor c when MSB(V) = 1 else

  w                <= (V(6 downto 0) & '0' ) xor c when V(7) = '1' else

                      (V(6 downto 0) & '0' );

end phy;