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[/] [nfcc/] [trunk/] [snow/] [sboxs2.vhdl] - Blame information for rev 2

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1 2 arif_endro
-- ------------------------------------------------------------------------
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-- Copyright (C) 2010 Arif Endro Nugroho
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-- All rights reserved.
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-- 
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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-- 
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-- 1. Redistributions of source code must retain the above copyright
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--    notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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--    notice, this list of conditions and the following disclaimer in the
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--    documentation and/or other materials provided with the distribution.
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-- 
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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- 
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-- End Of License.
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-- ------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity sboxs2 is
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  port (
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  w                : in  bit_vector ( 31 downto 0);
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  r                : out bit_vector ( 31 downto 0)
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  );
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end sboxs2;
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architecture phy of sboxs2 is
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  signal w0        :     bit_vector (  7 downto 0);
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  signal w1        :     bit_vector (  7 downto 0);
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  signal w2        :     bit_vector (  7 downto 0);
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  signal w3        :     bit_vector (  7 downto 0);
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  signal r0        :     bit_vector (  7 downto 0);
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  signal r1        :     bit_vector (  7 downto 0);
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  signal r2        :     bit_vector (  7 downto 0);
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  signal r3        :     bit_vector (  7 downto 0);
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  signal sq0i      :     bit_vector (  7 downto 0);
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  signal sq1i      :     bit_vector (  7 downto 0);
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  signal sq2i      :     bit_vector (  7 downto 0);
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  signal sq3i      :     bit_vector (  7 downto 0);
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  signal sq0o      :     bit_vector (  7 downto 0);
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  signal sq1o      :     bit_vector (  7 downto 0);
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  signal sq2o      :     bit_vector (  7 downto 0);
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  signal sq3o      :     bit_vector (  7 downto 0);
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  signal mlx0vi    :     bit_vector (  7 downto 0);
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  signal mlx0ci    :     bit_vector (  7 downto 0);
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  signal mlx0wo    :     bit_vector (  7 downto 0);
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  signal mlx1vi    :     bit_vector (  7 downto 0);
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  signal mlx1ci    :     bit_vector (  7 downto 0);
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  signal mlx1wo    :     bit_vector (  7 downto 0);
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  signal mlx2vi    :     bit_vector (  7 downto 0);
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  signal mlx2ci    :     bit_vector (  7 downto 0);
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  signal mlx2wo    :     bit_vector (  7 downto 0);
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  signal mlx3vi    :     bit_vector (  7 downto 0);
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  signal mlx3ci    :     bit_vector (  7 downto 0);
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  signal mlx3wo    :     bit_vector (  7 downto 0);
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  component sboxq
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  port (
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  di               : in  bit_vector (  7 downto 0);
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  do               : out bit_vector (  7 downto 0)
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  );
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  end component;
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  component mulx
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  port (
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  V                : in  bit_vector (  7 downto 0);
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  c                : in  bit_vector (  7 downto 0);
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  w                : out bit_Vector (  7 downto 0)
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  );
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  end component;
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begin
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  sq0              : sboxq
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  port map (
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  di               => sq0i,
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  do               => sq0o
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  );
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  sq1              : sboxq
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  port map (
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  di               => sq1i,
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  do               => sq1o
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  );
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  sq2              : sboxq
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  port map (
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  di               => sq2i,
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  do               => sq2o
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  );
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  sq3              : sboxq
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  port map (
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  di               => sq3i,
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  do               => sq3o
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  );
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  mlx0             : mulx
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  port map (
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  V                => mlx0vi,
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  c                => mlx0ci,
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  w                => mlx0wo
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  );
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  mlx1             : mulx
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  port map (
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  V                => mlx1vi,
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  c                => mlx1ci,
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  w                => mlx1wo
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  );
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  mlx2             : mulx
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  port map (
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  V                => mlx2vi,
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  c                => mlx2ci,
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  w                => mlx2wo
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  );
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  mlx3             : mulx
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  port map (
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  V                => mlx3vi,
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  c                => mlx3ci,
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  w                => mlx3wo
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  );
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--persistent connection
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  w0               <= w ( 31 downto 24);
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  w1               <= w ( 23 downto 16);
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  w2               <= w ( 15 downto  8);
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  w3               <= w (  7 downto  0);
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  sq0i             <= w0;
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  sq1i             <= w1;
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  sq2i             <= w2;
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  sq3i             <= w3;
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  mlx0vi           <= sq0o; --SQ(w0)
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  mlx1vi           <= sq1o; --SQ(w1)
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  mlx2vi           <= sq2o; --SQ(w2)
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  mlx3vi           <= sq3o; --SQ(w3)
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  mlx0ci           <= X"69";
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  mlx1ci           <= X"69";
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  mlx2ci           <= X"69";
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  mlx3ci           <= X"69";
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  r0               <= mlx0wo xor sq1o xor sq2o xor mlx3wo xor sq3o;
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  r1               <= mlx0wo xor sq0o xor mlx1wo xor sq2o xor sq3o;
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  r2               <= sq0o xor mlx1wo xor sq1o xor mlx2wo xor sq3o;
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  r3               <= sq0o xor sq1o xor mlx2wo xor sq2o xor mlx3wo;
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  r ( 31 downto 24)<= r0;
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  r ( 23 downto 16)<= r1;
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  r ( 15 downto  8)<= r2;
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  r (  7 downto  0)<= r3;
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--persistent connection
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end phy;

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