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arif_endro |
-- ------------------------------------------------------------------------
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-- Copyright (C) 2010 Arif Endro Nugroho
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- End Of License.
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-- ------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity snow is
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port (
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key : in bit_vector ( 31 downto 0);
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IV : in bit_vector ( 31 downto 0);
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n : in bit_vector ( 31 downto 0);
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zt : out bit_vector ( 31 downto 0);
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ld : in bit;
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init : in bit;
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shift : in bit;
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clk : in bit;
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rst : in bit
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);
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end snow;
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architecture phy of snow is
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signal lsfr : bit_vector (511 downto 0);
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signal s0 : bit_vector ( 31 downto 0);
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signal s1 : bit_vector ( 31 downto 0);
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signal s2 : bit_vector ( 31 downto 0);
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signal s3 : bit_vector ( 31 downto 0);
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signal s4 : bit_vector ( 31 downto 0);
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signal s5 : bit_vector ( 31 downto 0);
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signal s6 : bit_vector ( 31 downto 0);
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signal s7 : bit_vector ( 31 downto 0);
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signal s8 : bit_vector ( 31 downto 0);
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signal s9 : bit_vector ( 31 downto 0);
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signal sa : bit_vector ( 31 downto 0);
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signal sb : bit_vector ( 31 downto 0);
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signal sc : bit_vector ( 31 downto 0);
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signal sd : bit_vector ( 31 downto 0);
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signal se : bit_vector ( 31 downto 0);
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signal sf : bit_vector ( 31 downto 0);
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signal v : bit_vector ( 31 downto 0);
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signal ss1i : bit_vector ( 31 downto 0); -- S1
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signal ss1o : bit_vector ( 31 downto 0); -- S1
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signal ss2i : bit_vector ( 31 downto 0); -- S2
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signal ss2o : bit_vector ( 31 downto 0); -- S2
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signal F : bit_vector ( 31 downto 0); -- F = (sf +) xor R2
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signal r : bit_vector ( 31 downto 0); -- r = R2 + (R3 xor s5)
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signal R1 : bit_vector ( 31 downto 0); -- R1 = r
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signal R2 : bit_vector ( 31 downto 0); -- R2 = S1(R1)
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signal R3 : bit_vector ( 31 downto 0); -- R3 = S2(R2)
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signal mli : bit_vector ( 7 downto 0);
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signal mlo : bit_vector ( 31 downto 0);
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signal dvi : bit_vector ( 7 downto 0);
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signal dvo : bit_vector ( 31 downto 0);
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signal ivma : bit_vector (127 downto 0) := X"ffffffffffffffff0000000000000000";
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signal ivmb : bit_vector (127 downto 0) := X"0000000000000000ffffffff00000000";
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signal ivmc : bit_vector (127 downto 0) := X"000000000000000000000000ffffffff";
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component sboxs1
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port (
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w : bit_vector ( 31 downto 0);
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r : bit_vector ( 31 downto 0)
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);
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end component;
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component sboxs2
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port (
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w : bit_vector ( 31 downto 0);
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r : bit_vector ( 31 downto 0)
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);
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end component;
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component mula
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port (
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c : bit_vector ( 7 downto 0);
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w : bit_vector ( 31 downto 0)
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);
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end component;
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component diva
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port (
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c : bit_vector ( 7 downto 0);
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w : bit_vector ( 31 downto 0)
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);
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end component;
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begin
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ss1 : sboxs1
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port map (
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w => ss1i,
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r => ss1o
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);
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ss2 : sboxs2
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port map (
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w => ss2i,
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r => ss2o
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);
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ml : mula
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port map (
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c => mli,
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w => mlo
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);
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dv : diva
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port map (
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c => dvi,
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w => dvo
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);
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--persistent connection
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s0 <= lsfr(511 downto 480);
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s1 <= lsfr(479 downto 448);
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s2 <= lsfr(447 downto 416);
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s3 <= lsfr(415 downto 384);
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s4 <= lsfr(383 downto 352);
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s5 <= lsfr(351 downto 320);
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s6 <= lsfr(319 downto 288);
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s7 <= lsfr(287 downto 256);
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s8 <= lsfr(255 downto 224);
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s9 <= lsfr(223 downto 192);
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sa <= lsfr(191 downto 160);
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sb <= lsfr(159 downto 128);
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sc <= lsfr(127 downto 96);
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sd <= lsfr( 95 downto 64);
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se <= lsfr( 63 downto 32);
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sf <= lsfr( 31 downto 0);
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--persistent connection
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--FSM-Network
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F <= (sf + R1) xor R2 ; -- CAVEATS: THIS LINE IS NOT PORTABLE CODE
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r <= R2 + (R3 xor s5); -- CAVEATS: THIS LINE IS NOT PORTABLE CODE
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R1 <= r;
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ss1i <= R1;
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R2 <= ss1o;
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ss2i <= R2;
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R3 <= ss2o;
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--FSM-Network
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mli <= s0(31 downto 24);
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dvi <= sb( 7 downto 0);
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--v == (S0,1||S0,2||S0,3||0x00) xor MULa(S0,0) xor S2 xor (0x00||S11,0||S11,1||S11,2) xor DIVa(S11,3)
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v <= (s0(23 downto 0) & X"00") xor mlo xor s2 xor (X"00" & sb(31 downto 8)) xor dvo xor F when init = '1' else
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(s0(23 downto 0) & X"00") xor mlo xor s2 xor (X"00" & sb(31 downto 8)) xor dvo;
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process (clk)
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begin
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if((clk = '1') and clk'event) then
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if (rst = '1') then
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lsfr <= (others => '0');
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ivma <= X"ffffffffffffffff0000000000000000";
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ivmb <= X"0000000000000000ffffffff00000000";
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ivmc <= X"000000000000000000000000ffffffff";
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elsif (ld = '1') then
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ivma(127 downto 0) <= ivma( 95 downto 0) & ivma(127 downto 96); -- IV mask a
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ivmb(127 downto 0) <= ivmb( 95 downto 0) & ivmb(127 downto 96); -- IV mask b
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ivmc(127 downto 0) <= ivmc( 95 downto 0) & ivmc(127 downto 96); -- IV mask c
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--rotate in each block
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lsfr(127 downto 0) <= lsfr( 95 downto 0) & lsfr(127 downto 96); -- sc...sf
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lsfr(255 downto 128) <= lsfr(223 downto 128) & lsfr(255 downto 224); -- s8...sb
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lsfr(383 downto 256) <= lsfr(351 downto 256) & lsfr(383 downto 352); -- s4...s7
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lsfr(511 downto 384) <= lsfr(479 downto 384) & lsfr(511 downto 448); -- s0...s3
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--key
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lsfr(127 downto 96) <= key; -- sc == key
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lsfr(255 downto 224) <= key xor X"ffffffff"; -- s8 == key xor 1
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lsfr(383 downto 352) <= key; -- s4 == key
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lsfr(511 downto 448) <= key xor X"ffffffff"; -- s0 == key xor 1
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--special cases for IV, the sequences is quite peculiar: sf, sc, and sa, s9
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lsfr( 31 downto 0) <= IV and ivma(127 downto 96); -- first 2 clock go to sf then sc
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lsfr(255 downto 224) <= IV and ivmb(127 downto 96); -- next 1 clock go to sa
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lsfr(191 downto 160) <= IV and ivmc(127 downto 96); -- last 1 clock go to s9
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elsif (shift = '1') then
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lsfr <= lsfr(479 downto 0) & v;
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end if;
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end if;
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end process;
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zt <= F xor s0;
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end phy;
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