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[/] [nlprg/] [trunk/] [nlprg/] [tb/] [nlprg11_tb.v] - Blame information for rev 4

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`include "../rtl/nlprg11.v"
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module prng11_tb ();
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parameter N = 11;
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reg ck;
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reg rst;
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wire [N-1:0] o ;
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nlprg11 nlprg11_u (
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  .ck(ck),
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  .rst(rst),
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  .o(o)
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);
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// dump variables
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initial begin
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        $dumpfile( "./wave/prng11_tb.vcd");
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        $dumpvars( 0, prng11_tb );
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end
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integer f = -1 ; // file handler
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// generate clocks and reset
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initial begin
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        f = $fopen("./log/prng11_tb.log","w+");
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        rst = 1'b1     ;
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        #5 rst = ~ rst ;
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                #5 rst = ~ rst ;
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                #5 rst = ~ rst ;
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        ck  = 1'b1     ;
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forever #5 ck  = ~ ck  ;
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end
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// generate counter
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reg [N-1:0] cnt;
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always@ ( posedge ck or posedge rst ) begin : cnt_process
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  if ( rst ) cnt <= {N{1'b0}}  ;
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  else       cnt <= cnt + 1'b1 ;
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end
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// delay reset
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reg rst_d0;
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reg rst_d1;
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always@ ( posedge ck or posedge rst ) begin : reset_delay_process
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  if ( rst ) begin
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    rst_d0 <= 1'b1   ;
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    rst_d1 <= 1'b1   ;
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  end else begin
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    rst_d0 <= 1'b0   ;
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    rst_d1 <= rst_d0 ;
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  end
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end
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// generate endsim
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reg endsim;
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reg pass;
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wire prng_start_state = ( o   == {N{1'b0}});
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wire cnt_start_state  = ( cnt == {N{1'b0}});
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always@ ( posedge ck or posedge rst ) begin : lock_process
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  if      ( rst                                                   ) begin
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    endsim <= 1'b0 ;
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    pass   <= 1'b0 ;
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  end else if ( prng_start_state & ( ! rst_d1 )                   ) begin
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    endsim <= 1'b1 ;
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    pass   <= 1'b0 ;
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  end else if ( cnt_start_state  & prng_start_state & ( ! rst_d1 ) ) begin
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    endsim <= 1'b1 ;
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    pass   <= 1'b1 ;
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  end else if ( cnt_start_state  & ( ! rst_d1 )                   ) begin
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    endsim <= 1'b1 ;
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    pass   <= 1'b0 ;
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  end
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end
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// display and finish
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always@ ( posedge ck or posedge rst ) begin : display_process
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  if          (( ! endsim ) && ( ! rst ))  begin
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    $fdisplay(f,"%10d %10b", cnt , o) ;
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  end else if ( endsim                  )  begin
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    $fclose(f);
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    $finish ;
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  end
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end
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endmodule

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