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[/] [noekeoncore/] [trunk/] [rtl/] [noekeon.vhd] - Blame information for rev 2

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1 2 entactogen 
 
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-- Copyright (c) 2013 Antonio de la Piedra
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity noekeon is
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        port(clk     : in std_logic;
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                  rst     : in std_logic;
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                  enc     : in std_logic; -- (enc, 0) / (dec, 1)
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                  a_0_in  : in std_logic_vector(31 downto 0);
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                  a_1_in  : in std_logic_vector(31 downto 0);
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                  a_2_in  : in std_logic_vector(31 downto 0);
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                  a_3_in  : in std_logic_vector(31 downto 0);
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                  k_0_in  : in std_logic_vector(31 downto 0);
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                  k_1_in  : in std_logic_vector(31 downto 0);
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                  k_2_in  : in std_logic_vector(31 downto 0);
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                  k_3_in  : in std_logic_vector(31 downto 0);
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                  a_0_out : out std_logic_vector(31 downto 0);
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                  a_1_out : out std_logic_vector(31 downto 0);
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                  a_2_out : out std_logic_vector(31 downto 0);
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                  a_3_out : out std_logic_vector(31 downto 0));
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end noekeon;
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architecture Behavioral of noekeon is
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        component round_f is
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        port(clk     : in std_logic;
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             enc : in std_logic;
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                  rc_in   : in std_logic_vector(31 downto 0);
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                  a_0_in  : in std_logic_vector(31 downto 0);
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                  a_1_in  : in std_logic_vector(31 downto 0);
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                  a_2_in  : in std_logic_vector(31 downto 0);
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                  a_3_in  : in std_logic_vector(31 downto 0);
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                  k_0_in  : in std_logic_vector(31 downto 0);
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                  k_1_in  : in std_logic_vector(31 downto 0);
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                  k_2_in  : in std_logic_vector(31 downto 0);
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                  k_3_in  : in std_logic_vector(31 downto 0);
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                  a_0_out : out std_logic_vector(31 downto 0);
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                  a_1_out : out std_logic_vector(31 downto 0);
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                  a_2_out : out std_logic_vector(31 downto 0);
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                  a_3_out : out std_logic_vector(31 downto 0));
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        end component;
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        component rc_gen is
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        port(clk : in std_logic;
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             rst : in std_logic;
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                  enc : in std_logic; -- (enc, 0) / (dec, 1)
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                  rc_out : out std_logic_vector(7 downto 0));
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        end component;
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        component output_trans is
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        port(clk     : in std_logic;
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                  enc            : in std_logic; -- (enc, 0) / (dec, 1)
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                  rc_in   : in std_logic_vector(31 downto 0);
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                  a_0_in  : in std_logic_vector(31 downto 0);
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                  a_1_in  : in std_logic_vector(31 downto 0);
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                  a_2_in  : in std_logic_vector(31 downto 0);
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                  a_3_in  : in std_logic_vector(31 downto 0);
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                  k_0_in  : in std_logic_vector(31 downto 0);
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                  k_1_in  : in std_logic_vector(31 downto 0);
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                  k_2_in  : in std_logic_vector(31 downto 0);
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                  k_3_in  : in std_logic_vector(31 downto 0);
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                  a_0_out : out std_logic_vector(31 downto 0);
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                  a_1_out : out std_logic_vector(31 downto 0);
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                  a_2_out : out std_logic_vector(31 downto 0);
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                  a_3_out : out std_logic_vector(31 downto 0));
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        end component;
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        component theta is
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        port(clk : in std_logic;
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             a_0_in : in std_logic_vector(31 downto 0);
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             a_1_in : in std_logic_vector(31 downto 0);
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             a_2_in : in std_logic_vector(31 downto 0);
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             a_3_in : in std_logic_vector(31 downto 0);
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             k_0_in : in std_logic_vector(31 downto 0);
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             k_1_in : in std_logic_vector(31 downto 0);
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             k_2_in : in std_logic_vector(31 downto 0);
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             k_3_in : in std_logic_vector(31 downto 0);
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             a_0_out : out std_logic_vector(31 downto 0);
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             a_1_out : out std_logic_vector(31 downto 0);
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             a_2_out : out std_logic_vector(31 downto 0);
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             a_3_out : out std_logic_vector(31 downto 0));
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        end component;
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        signal rc_s : std_logic_vector(7 downto 0);
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        signal rc_ext_s : std_logic_vector(31 downto 0);
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        signal a_0_in_s  : std_logic_vector(31 downto 0);
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        signal a_1_in_s  : std_logic_vector(31 downto 0);
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        signal a_2_in_s  : std_logic_vector(31 downto 0);
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        signal a_3_in_s  : std_logic_vector(31 downto 0);
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        signal out_t_a_0_in_s  : std_logic_vector(31 downto 0);
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        signal out_t_a_1_in_s  : std_logic_vector(31 downto 0);
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        signal out_t_a_2_in_s  : std_logic_vector(31 downto 0);
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        signal out_t_a_3_in_s  : std_logic_vector(31 downto 0);
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        signal a_0_out_s : std_logic_vector(31 downto 0);
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        signal a_1_out_s : std_logic_vector(31 downto 0);
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        signal a_2_out_s : std_logic_vector(31 downto 0);
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        signal a_3_out_s : std_logic_vector(31 downto 0);
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        signal k_0_d_s  : std_logic_vector(31 downto 0);
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        signal k_1_d_s  : std_logic_vector(31 downto 0);
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        signal k_2_d_s  : std_logic_vector(31 downto 0);
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        signal k_3_d_s  : std_logic_vector(31 downto 0);
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        signal k_0_mux_s  : std_logic_vector(31 downto 0);
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        signal k_1_mux_s  : std_logic_vector(31 downto 0);
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        signal k_2_mux_s  : std_logic_vector(31 downto 0);
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        signal k_3_mux_s  : std_logic_vector(31 downto 0);
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begin
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        RC_GEN_0 : rc_gen port map (clk, rst, enc, rc_s);
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        rc_ext_s <= X"000000" & rc_s;
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        ROUND_F_0 : round_f port map (clk,
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                                                                                   enc,
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                                                                                   rc_ext_s,
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                                                                                        a_0_in_s,
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                                                                                        a_1_in_s,
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                                                                                   a_2_in_s,
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                                                                                        a_3_in_s,
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                                                                                        k_0_mux_s,
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                                                                                        k_1_mux_s,
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                                                                                        k_2_mux_s,
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                                                                                        k_3_mux_s,
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                                                                                        a_0_out_s,
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                                                                                        a_1_out_s,
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                                                                                        a_2_out_s,
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                                                                                        a_3_out_s);
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        pr_noe: process(clk, rst, enc)
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        begin
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                if rising_edge(clk) then
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                        if rst = '1' then
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                                a_0_in_s <= a_0_in;
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                                a_1_in_s <= a_1_in;
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                                a_2_in_s <= a_2_in;
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                                a_3_in_s <= a_3_in;
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                        else
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                                a_0_in_s <= a_0_out_s;
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                                a_1_in_s <= a_1_out_s;
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                                a_2_in_s <= a_2_out_s;
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                                a_3_in_s <= a_3_out_s;
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                        end if;
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                end if;
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        end process;
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--      a_0_out <= a_0_out_s;
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--      a_1_out <= a_1_out_s;
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--      a_2_out <= a_2_out_s;
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--      a_3_out <= a_3_out_s;
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        out_trans_pr: process(clk, rst, a_0_out_s, a_1_out_s, a_2_out_s, a_3_out_s)
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        begin
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                if rising_edge(clk) then
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                        out_t_a_0_in_s <= a_0_out_s;
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                        out_t_a_1_in_s <= a_1_out_s;
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                        out_t_a_2_in_s <= a_2_out_s;
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                        out_t_a_3_in_s <= a_3_out_s;
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                end if;
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        end process;
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        OUT_TRANS_0 : output_trans port map (clk, enc, rc_ext_s,
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                        out_t_a_0_in_s,
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                        out_t_a_1_in_s,
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                        out_t_a_2_in_s,
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                        out_t_a_3_in_s,
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                        k_0_mux_s,
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                        k_1_mux_s,
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                        k_2_mux_s,
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                        k_3_mux_s,
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                        a_0_out,
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                        a_1_out,
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                        a_2_out,
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                        a_3_out);
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        -- key decrypt
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        THETA_DECRYPT_0 : theta port map (clk,
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                        k_0_in,
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                        k_1_in,
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                        k_2_in,
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                        k_3_in,
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                        (others => '0'),
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                        (others => '0'),
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                        (others => '0'),
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                        (others => '0'),
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                        k_0_d_s,
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              k_1_d_s,
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              k_2_d_s,
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              k_3_d_s);
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                        k_0_mux_s <= k_0_in when enc = '0' else k_0_d_s;
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                        k_1_mux_s <= k_1_in when enc = '0' else k_1_d_s;
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                        k_2_mux_s <= k_2_in when enc = '0' else k_2_d_s;
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                        k_3_mux_s <= k_3_in when enc = '0' else k_3_d_s;
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end Behavioral;
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