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[/] [noekeoncore/] [trunk/] [rtl/] [pi_2.vhd] - Blame information for rev 2

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1 2 entactogen
 
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-- Copyright (c) 2013 Antonio de la Piedra
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Copyright (c) 2013 Antonio de la Piedra
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
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entity pi_2 is
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        port(a_1_in     : in std_logic_vector(31 downto 0);
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                  a_2_in        : in std_logic_vector(31 downto 0);
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                  a_3_in        : in std_logic_vector(31 downto 0);
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                  a_1_out       : out std_logic_vector(31 downto 0);
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                  a_2_out       : out std_logic_vector(31 downto 0);
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                  a_3_out       : out std_logic_vector(31 downto 0));
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end pi_2;
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architecture Behavioral of pi_2 is
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begin
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        a_1_out <= a_1_in(0) & a_1_in(31 downto 1);
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        a_2_out <= a_2_in(4 downto 0) & a_2_in(31 downto 5);
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        a_3_out <= a_3_in(1 downto 0) & a_3_in(31 downto 2);
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end Behavioral;
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