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[/] [noekeoncore/] [trunk/] [rtl/] [round_f.vhd] - Blame information for rev 2

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-- Copyright (c) 2013 Antonio de la Piedra
 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
 
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity round_f is
        port(clk     : in std_logic;
             enc : in std_logic;
                  rc_in   : in std_logic_vector(31 downto 0);
                  a_0_in  : in std_logic_vector(31 downto 0);
                  a_1_in  : in std_logic_vector(31 downto 0);
                  a_2_in  : in std_logic_vector(31 downto 0);
                  a_3_in  : in std_logic_vector(31 downto 0);
                  k_0_in  : in std_logic_vector(31 downto 0);
                  k_1_in  : in std_logic_vector(31 downto 0);
                  k_2_in  : in std_logic_vector(31 downto 0);
                  k_3_in  : in std_logic_vector(31 downto 0);
                  a_0_out : out std_logic_vector(31 downto 0);
                  a_1_out : out std_logic_vector(31 downto 0);
                  a_2_out : out std_logic_vector(31 downto 0);
                  a_3_out : out std_logic_vector(31 downto 0));
end round_f;
 
architecture Behavioral of round_f is
 
        signal a_0_in_s : std_logic_vector(31 downto 0);
 
        signal theta_0_s : std_logic_vector(31 downto 0);
        signal theta_1_s : std_logic_vector(31 downto 0);
        signal theta_2_s : std_logic_vector(31 downto 0);
        signal theta_3_s : std_logic_vector(31 downto 0);
 
        signal pi_1_1_s : std_logic_vector(31 downto 0);
        signal pi_1_2_s : std_logic_vector(31 downto 0);
        signal pi_1_3_s : std_logic_vector(31 downto 0);
 
        signal gamma_0_s : std_logic_vector(31 downto 0);
        signal gamma_1_s : std_logic_vector(31 downto 0);
        signal gamma_2_s : std_logic_vector(31 downto 0);
        signal gamma_3_s : std_logic_vector(31 downto 0);
 
        signal pi_2_1_s : std_logic_vector(31 downto 0);
        signal pi_2_2_s : std_logic_vector(31 downto 0);
        signal pi_2_3_s : std_logic_vector(31 downto 0);
 
        component theta is
        port(clk : in std_logic;
 
             a_0_in : in std_logic_vector(31 downto 0);
             a_1_in : in std_logic_vector(31 downto 0);
             a_2_in : in std_logic_vector(31 downto 0);
             a_3_in : in std_logic_vector(31 downto 0);
 
             k_0_in : in std_logic_vector(31 downto 0);
             k_1_in : in std_logic_vector(31 downto 0);
             k_2_in : in std_logic_vector(31 downto 0);
             k_3_in : in std_logic_vector(31 downto 0);
 
             a_0_out : out std_logic_vector(31 downto 0);
             a_1_out : out std_logic_vector(31 downto 0);
             a_2_out : out std_logic_vector(31 downto 0);
             a_3_out : out std_logic_vector(31 downto 0));
        end component;
 
        component pi_1 is
        port(a_1_in     : in std_logic_vector(31 downto 0);
                  a_2_in        : in std_logic_vector(31 downto 0);
                  a_3_in        : in std_logic_vector(31 downto 0);
                  a_1_out       : out std_logic_vector(31 downto 0);
                  a_2_out       : out std_logic_vector(31 downto 0);
                  a_3_out       : out std_logic_vector(31 downto 0));
        end component;
 
        component gamma is
        port(clk : in std_logic;
                  a_0_in : in std_logic_vector(31 downto 0);
                  a_1_in : in std_logic_vector(31 downto 0);
                  a_2_in : in std_logic_vector(31 downto 0);
                  a_3_in : in std_logic_vector(31 downto 0);
 
                  a_0_out : out std_logic_vector(31 downto 0);
                  a_1_out : out std_logic_vector(31 downto 0);
                  a_2_out : out std_logic_vector(31 downto 0);
                  a_3_out : out std_logic_vector(31 downto 0));
        end component;
 
        component pi_2 is
        port(a_1_in     : in std_logic_vector(31 downto 0);
                  a_2_in        : in std_logic_vector(31 downto 0);
                  a_3_in        : in std_logic_vector(31 downto 0);
                  a_1_out       : out std_logic_vector(31 downto 0);
                  a_2_out       : out std_logic_vector(31 downto 0);
                  a_3_out       : out std_logic_vector(31 downto 0));
        end component;
 
        signal a_0_aux_s : std_logic_vector(31 downto 0);
 
begin
 
        a_0_in_s <= (a_0_in xor rc_in) when enc = '0' else a_0_in;
 
        THETA_0 : theta port map (clk,
                                                                          a_0_in_s,
                                                                          a_1_in,
                                                                          a_2_in,
                                                                          a_3_in,
                                                                          k_0_in,
                                                                          k_1_in,
                                                                          k_2_in,
                                                                          k_3_in,
                                                                          theta_0_s,
                                                                          theta_1_s,
                                                                          theta_2_s,
                                                                          theta_3_s);
 
        a_0_aux_s <= (theta_0_s xor rc_in) when enc = '1' else theta_0_s;
 
        PI_1_0 : pi_1 port map (theta_1_s,
                                                                        theta_2_s,
                                                                        theta_3_s,
                                                                        pi_1_1_s,
                                                                        pi_1_2_s,
                                                                        pi_1_3_s);
 
        GAMMA_0 : gamma port map (clk,
                                                                          a_0_aux_s,
                                                                          pi_1_1_s,
                                                                          pi_1_2_s,
                                                                          pi_1_3_s,
                                                                          gamma_0_s,
                                                                          gamma_1_s,
                                                                          gamma_2_s,
                                                                gamma_3_s);
 
        PI_2_0 : pi_2 port map (gamma_1_s,
                                                                        gamma_2_s,
                                                                        gamma_3_s,
                                                                        pi_2_1_s,
                                                                        pi_2_2_s,
                                                                        pi_2_3_s);
 
        a_0_out <= gamma_0_s;
        a_1_out <= pi_2_1_s;
        a_2_out <= pi_2_2_s;
        a_3_out <= pi_2_3_s;
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	2	entactogen
2			`-- Copyright (c) 2013 Antonio de la Piedra`
3
4			`-- This program is free software: you can redistribute it and/or modify`
5			`-- it under the terms of the GNU General Public License as published by`
6			`-- the Free Software Foundation, either version 3 of the License, or`
7			`-- (at your option) any later version.`
8
9			`-- This program is distributed in the hope that it will be useful,`
10			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
11			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
12			`-- GNU General Public License for more details.`
13
14			`-- You should have received a copy of the GNU General Public License`
15			`-- along with this program. If not, see <http://www.gnu.org/licenses/>.`
16
17			`library IEEE;`
18			`use IEEE.STD_LOGIC_1164.ALL;`
19
20			`entity round_f is`
21			`port(clk : in std_logic;`
22			`enc : in std_logic;`
23			`rc_in : in std_logic_vector(31 downto 0);`
24			`a_0_in : in std_logic_vector(31 downto 0);`
25			`a_1_in : in std_logic_vector(31 downto 0);`
26			`a_2_in : in std_logic_vector(31 downto 0);`
27			`a_3_in : in std_logic_vector(31 downto 0);`
28			`k_0_in : in std_logic_vector(31 downto 0);`
29			`k_1_in : in std_logic_vector(31 downto 0);`
30			`k_2_in : in std_logic_vector(31 downto 0);`
31			`k_3_in : in std_logic_vector(31 downto 0);`
32			`a_0_out : out std_logic_vector(31 downto 0);`
33			`a_1_out : out std_logic_vector(31 downto 0);`
34			`a_2_out : out std_logic_vector(31 downto 0);`
35			`a_3_out : out std_logic_vector(31 downto 0));`
36			`end round_f;`
37
38			`architecture Behavioral of round_f is`
39
40			`signal a_0_in_s : std_logic_vector(31 downto 0);`
41
42			`signal theta_0_s : std_logic_vector(31 downto 0);`
43			`signal theta_1_s : std_logic_vector(31 downto 0);`
44			`signal theta_2_s : std_logic_vector(31 downto 0);`
45			`signal theta_3_s : std_logic_vector(31 downto 0);`
46
47			`signal pi_1_1_s : std_logic_vector(31 downto 0);`
48			`signal pi_1_2_s : std_logic_vector(31 downto 0);`
49			`signal pi_1_3_s : std_logic_vector(31 downto 0);`
50
51			`signal gamma_0_s : std_logic_vector(31 downto 0);`
52			`signal gamma_1_s : std_logic_vector(31 downto 0);`
53			`signal gamma_2_s : std_logic_vector(31 downto 0);`
54			`signal gamma_3_s : std_logic_vector(31 downto 0);`
55
56			`signal pi_2_1_s : std_logic_vector(31 downto 0);`
57			`signal pi_2_2_s : std_logic_vector(31 downto 0);`
58			`signal pi_2_3_s : std_logic_vector(31 downto 0);`
59
60			`component theta is`
61			`port(clk : in std_logic;`
62
63			`a_0_in : in std_logic_vector(31 downto 0);`
64			`a_1_in : in std_logic_vector(31 downto 0);`
65			`a_2_in : in std_logic_vector(31 downto 0);`
66			`a_3_in : in std_logic_vector(31 downto 0);`
67
68			`k_0_in : in std_logic_vector(31 downto 0);`
69			`k_1_in : in std_logic_vector(31 downto 0);`
70			`k_2_in : in std_logic_vector(31 downto 0);`
71			`k_3_in : in std_logic_vector(31 downto 0);`
72
73			`a_0_out : out std_logic_vector(31 downto 0);`
74			`a_1_out : out std_logic_vector(31 downto 0);`
75			`a_2_out : out std_logic_vector(31 downto 0);`
76			`a_3_out : out std_logic_vector(31 downto 0));`
77			`end component;`
78
79			`component pi_1 is`
80			`port(a_1_in : in std_logic_vector(31 downto 0);`
81			`a_2_in : in std_logic_vector(31 downto 0);`
82			`a_3_in : in std_logic_vector(31 downto 0);`
83			`a_1_out : out std_logic_vector(31 downto 0);`
84			`a_2_out : out std_logic_vector(31 downto 0);`
85			`a_3_out : out std_logic_vector(31 downto 0));`
86			`end component;`
87
88			`component gamma is`
89			`port(clk : in std_logic;`
90			`a_0_in : in std_logic_vector(31 downto 0);`
91			`a_1_in : in std_logic_vector(31 downto 0);`
92			`a_2_in : in std_logic_vector(31 downto 0);`
93			`a_3_in : in std_logic_vector(31 downto 0);`
94
95			`a_0_out : out std_logic_vector(31 downto 0);`
96			`a_1_out : out std_logic_vector(31 downto 0);`
97			`a_2_out : out std_logic_vector(31 downto 0);`
98			`a_3_out : out std_logic_vector(31 downto 0));`
99			`end component;`
100
101			`component pi_2 is`
102			`port(a_1_in : in std_logic_vector(31 downto 0);`
103			`a_2_in : in std_logic_vector(31 downto 0);`
104			`a_3_in : in std_logic_vector(31 downto 0);`
105			`a_1_out : out std_logic_vector(31 downto 0);`
106			`a_2_out : out std_logic_vector(31 downto 0);`
107			`a_3_out : out std_logic_vector(31 downto 0));`
108			`end component;`
109
110			`signal a_0_aux_s : std_logic_vector(31 downto 0);`
111
112			`begin`
113
114			`a_0_in_s <= (a_0_in xor rc_in) when enc = '0' else a_0_in;`
115
116			`THETA_0 : theta port map (clk,`
117			`a_0_in_s,`
118			`a_1_in,`
119			`a_2_in,`
120			`a_3_in,`
121			`k_0_in,`
122			`k_1_in,`
123			`k_2_in,`
124			`k_3_in,`
125			`theta_0_s,`
126			`theta_1_s,`
127			`theta_2_s,`
128			`theta_3_s);`
129
130			`a_0_aux_s <= (theta_0_s xor rc_in) when enc = '1' else theta_0_s;`
131
132			`PI_1_0 : pi_1 port map (theta_1_s,`
133			`theta_2_s,`
134			`theta_3_s,`
135			`pi_1_1_s,`
136			`pi_1_2_s,`
137			`pi_1_3_s);`
138
139			`GAMMA_0 : gamma port map (clk,`
140			`a_0_aux_s,`
141			`pi_1_1_s,`
142			`pi_1_2_s,`
143			`pi_1_3_s,`
144			`gamma_0_s,`
145			`gamma_1_s,`
146			`gamma_2_s,`
147			`gamma_3_s);`
148
149			`PI_2_0 : pi_2 port map (gamma_1_s,`
150			`gamma_2_s,`
151			`gamma_3_s,`
152			`pi_2_1_s,`
153			`pi_2_2_s,`
154			`pi_2_3_s);`
155
156			`a_0_out <= gamma_0_s;`
157			`a_1_out <= pi_2_1_s;`
158			`a_2_out <= pi_2_2_s;`
159			`a_3_out <= pi_2_3_s;`
160
161			`end Behavioral;`
162

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[/] [noekeoncore/] [trunk/] [rtl/] [round_f.vhd] - Blame information for rev 2