URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

Subversion Repositories oms8051mini

[/] [oms8051mini/] [trunk/] [example/] [systemverilog/] [assertion/] [ovl/] [fifo/] [run_modelsim] - Blame information for rev 13

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#!/bin/csh -f
 
if(! -e work) then
   vlib work
else
   \rm -rf work
   vlib work
endif
 
#####################################################################################
# CHANGE these line to the appropriate command for your simulator
#####################################################################################
set VERILOG     = "vlog -work work +acc-rn +notimingchecks +nospecify +incdir+/tools/questasim/10.2b/questa_sim/verilog_src/std_ovl "
set ELAB        = "vsim -do run.do -c fifo_tb +notimingchecks +nospecify "
echo " Compiling with questsim "
 
 
$VERILOG  syn_fifo_assert.v fifo_tb.v ram_dp_ar_aw.v
$ELAB -voptargs="+acc-npr" -l ../run.sim.log
 
 

Line No.	Rev	Author	Line
1	13	dinesha	`#!/bin/csh -f`
2
3			`if(! -e work) then`
4			`vlib work`
5			`else`
6			`\rm -rf work`
7			`vlib work`
8			`endif`
9
10			`#####################################################################################`
11			`# CHANGE these line to the appropriate command for your simulator`
12			`#####################################################################################`
13			`set VERILOG = "vlog -work work +acc-rn +notimingchecks +nospecify +incdir+/tools/questasim/10.2b/questa_sim/verilog_src/std_ovl "`
14			`set ELAB = "vsim -do run.do -c fifo_tb +notimingchecks +nospecify "`
15			`echo " Compiling with questsim "`
16
17
18			`$VERILOG syn_fifo_assert.v fifo_tb.v ram_dp_ar_aw.v`
19			`$ELAB -voptargs="+acc-npr" -l ../run.sim.log`
20
21

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Subversion Repositories oms8051mini

[/] [oms8051mini/] [trunk/] [example/] [systemverilog/] [assertion/] [ovl/] [fifo/] [run_modelsim] - Blame information for rev 13