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[/] [oms8051mini/] [trunk/] [example/] [systemverilog/] [assertion/] [test3/] [test.sv] - Blame information for rev 13

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1 13 dinesha
//+++++++++++++++++++++++++++++++++++++++++++++++++
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//   DUT With assertions
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//+++++++++++++++++++++++++++++++++++++++++++++++++
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module repetition_assertion();
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logic clk = 0;
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always #1 clk ++;
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logic req,busy,gnt;
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//=================================================
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// Sequence Layer
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//=================================================
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sequence boring_way_seq;
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  req ##1 busy ##1 busy ##1 busy ##1 gnt;
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endsequence
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sequence cool_way_seq;
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  req ##1 busy [*3] ##1 gnt;
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endsequence
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sequence range_seq;
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  req ##1 busy [*1:5] ##1 gnt;
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endsequence
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//=================================================
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// Property Specification Layer
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//=================================================
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property boring_way_prop;
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  @ (posedge clk)
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      req |-> boring_way_seq;
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endproperty
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property cool_way_prop;
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  @ (posedge clk)
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      req |-> cool_way_seq;
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endproperty
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//=================================================
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// Assertion Directive Layer
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//=================================================
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boring_way_assert : assert property (boring_way_prop);
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cool_way_assert   : assert property (cool_way_prop);
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//=================================================
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// Generate input vectors
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//=================================================
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initial begin
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  req <= 0; busy <= 0;gnt <= 0;
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  @ (posedge clk);
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  req <= 1;
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  @ (posedge clk);
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  busy <= 1;
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  req  <= 0;
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  repeat(3) @ (posedge clk);
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  busy <= 0;
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  gnt <= 1;
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  @ (posedge clk);
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  gnt <= 0;
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  // Now make the assertion fail
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  req <= 0; busy <= 0;gnt <= 0;
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  @ (posedge clk);
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  req <= 1;
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  @ (posedge clk);
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  busy <= 1;
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  req  <= 0;
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  repeat(4) @ (posedge clk);
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  busy <= 0;
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  gnt <= 1;
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  @ (posedge clk);
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  gnt <= 0;
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  #30 $finish;
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end
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`include "dump.v"
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endmodule

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