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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_ports.v] - Blame information for rev 37

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 port output                                            ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////   8051 special function registers: port 0:3 - output         ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, simont@opencores.org                  ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////   v0.0 - Dinesh A, 5th Jan 2017
////        1. Active edge of reset changed from High to Low
////   v0.1 - Dinesh A, 19th Jan 2017
////        1. Lint Warning fixes
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9  2003/04/10 12:43:19  simont
// defines for pherypherals added
//
// Revision 1.8  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.7  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.6  2002/09/30 17:33:59  simont
// prepared header
//
//
 
 
`include "top_defines.v"
 
 
module oc8051_ports (clk,
                    resetn,
                    bit_in,
                    data_in,
                    wr,
                    wr_bit,
                    wr_addr,
 
        `ifdef OC8051_PORT0
                    p0_out,
                    p0_in,
                    p0_data,
        `endif
 
        `ifdef OC8051_PORT1
                    p1_out,
                    p1_in,
                    p1_data,
 
        `endif
 
        `ifdef OC8051_PORT2
                    p2_out,
                    p2_in,
                    p2_data,
        `endif
 
        `ifdef OC8051_PORT3
                    p3_out,
                    p3_in,
                    p3_data,
        `endif
 
                    rmw);
 
input        clk,       //clock
             resetn,    //reset
             wr,        //write [oc8051_decoder.wr -r]
             wr_bit,    //write bit addresable [oc8051_decoder.bit_addr -r]
             bit_in,    //bit input [oc8051_alu.desCy]
             rmw;       //read modify write feature [oc8051_decoder.rmw]
input [7:0]  wr_addr,    //write address [oc8051_ram_wr_sel.out]
             data_in;   //data input (from alu destiantion 1) [oc8051_alu.des1]
 
`ifdef OC8051_PORT0
  input  [7:0] p0_in;
  output [7:0] p0_out,
               p0_data;
  reg    [7:0] p0_out;
 
  assign p0_data = rmw ? p0_out : p0_in;
`endif
 
 
`ifdef OC8051_PORT1
  input  [7:0] p1_in;
  output [7:0] p1_out,
               p1_data;
  reg    [7:0] p1_out;
 
  assign p1_data = rmw ? p1_out : p1_in;
`endif
 
 
`ifdef OC8051_PORT2
  input  [7:0] p2_in;
  output [7:0] p2_out,
               p2_data;
  reg    [7:0] p2_out;
 
  assign p2_data = rmw ? p2_out : p2_in;
`endif
 
 
`ifdef OC8051_PORT3
  input  [7:0] p3_in;
  output [7:0] p3_out,
               p3_data;
  reg    [7:0] p3_out;
 
  assign p3_data = rmw ? p3_out : p3_in;
`endif
 
//
// case of writing to port
always @(posedge clk or negedge resetn)
begin
  if (resetn == 1'b0) begin
`ifdef OC8051_PORT0
    p0_out <= `OC8051_RST_P0;
`endif
 
`ifdef OC8051_PORT1
    p1_out <= `OC8051_RST_P1;
`endif
 
`ifdef OC8051_PORT2
    p2_out <= `OC8051_RST_P2;
`endif
 
`ifdef OC8051_PORT3
    p3_out <= `OC8051_RST_P3;
`endif
  end else if (wr) begin
    if (!wr_bit) begin
      case (wr_addr) /* synopsys full_case parallel_case */
//
// bytaddresable
`ifdef OC8051_PORT0
        `OC8051_SFR_P0: begin p0_out <= data_in;
         end
`endif
 
`ifdef OC8051_PORT1
        `OC8051_SFR_P1: p1_out <= data_in;
`endif
 
`ifdef OC8051_PORT2
        `OC8051_SFR_P2: p2_out <= data_in;
`endif
 
`ifdef OC8051_PORT3
        `OC8051_SFR_P3: p3_out <= data_in;
`endif
      default : begin
        `ifdef OC8051_PORT0
            p0_out <= p0_out;
        `endif
 
        `ifdef OC8051_PORT1
            p1_out <= p1_out;
        `endif
 
        `ifdef OC8051_PORT2
            p2_out <= p2_out;
        `endif
 
        `ifdef OC8051_PORT3
            p3_out <= p3_out;
        `endif
 
      end
      endcase
    end else begin
      case (wr_addr[7:3]) /* synopsys full_case parallel_case */
 
//
// bit addressable
`ifdef OC8051_PORT0
        `OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= bit_in;
`endif
 
`ifdef OC8051_PORT1
        `OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= bit_in;
`endif
 
`ifdef OC8051_PORT2
        `OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= bit_in;
`endif
 
`ifdef OC8051_PORT3
        `OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= bit_in;
`endif
        default: begin
`ifdef OC8051_PORT0
    p0_out <= `OC8051_RST_P0;
`endif
 
`ifdef OC8051_PORT1
    p1_out <= `OC8051_RST_P1;
`endif
 
`ifdef OC8051_PORT2
    p2_out <= `OC8051_RST_P2;
`endif
 
`ifdef OC8051_PORT3
    p3_out <= `OC8051_RST_P3;
`endif
         end
      endcase
    end
  end
end
 
 
endmodule
 

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 port output ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 8051 special function registers: port 0:3 - output ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// - Dinesh Annayya, simont@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19	25	dinesha	`//// v0.0 - Dinesh A, 5th Jan 2017`
20			`//// 1. Active edge of reset changed from High to Low`
21	36	dinesha	`//// v0.1 - Dinesh A, 19th Jan 2017`
22			`//// 1. Lint Warning fixes`
23	25	dinesha	`//////////////////////////////////////////////////////////////////////`
24	2	dinesha	`//// ////`
25			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`// CVS Revision History`
51			`//`
52			`// $Log: not supported by cvs2svn $`
53			`// Revision 1.9 2003/04/10 12:43:19 simont`
54			`// defines for pherypherals added`
55			`//`
56			`// Revision 1.8 2003/04/07 14:58:02 simont`
57			`// change sfr's interface.`
58			`//`
59			`// Revision 1.7 2003/01/13 14:14:41 simont`
60			`// replace some modules`
61			`//`
62			`// Revision 1.6 2002/09/30 17:33:59 simont`
63			`// prepared header`
64			`//`
65			`//`
66
67
68			`include "top_defines.v"
69
70
71			`module oc8051_ports (clk,`
72	25	dinesha	`resetn,`
73	2	dinesha	`bit_in,`
74			`data_in,`
75			`wr,`
76			`wr_bit,`
77			`wr_addr,`
78
79			`ifdef OC8051_PORT0
80			`p0_out,`
81			`p0_in,`
82			`p0_data,`
83			`endif
84
85			`ifdef OC8051_PORT1
86			`p1_out,`
87			`p1_in,`
88			`p1_data,`
89
90			`endif
91
92			`ifdef OC8051_PORT2
93			`p2_out,`
94			`p2_in,`
95			`p2_data,`
96			`endif
97
98			`ifdef OC8051_PORT3
99			`p3_out,`
100			`p3_in,`
101			`p3_data,`
102			`endif
103
104			`rmw);`
105
106			`input clk, //clock`
107	25	dinesha	`resetn, //reset`
108	2	dinesha	`wr, //write [oc8051_decoder.wr -r]`
109			`wr_bit, //write bit addresable [oc8051_decoder.bit_addr -r]`
110			`bit_in, //bit input [oc8051_alu.desCy]`
111			`rmw; //read modify write feature [oc8051_decoder.rmw]`
112			`input [7:0] wr_addr, //write address [oc8051_ram_wr_sel.out]`
113			`data_in; //data input (from alu destiantion 1) [oc8051_alu.des1]`
114
115			`ifdef OC8051_PORT0
116			`input [7:0] p0_in;`
117			`output [7:0] p0_out,`
118			`p0_data;`
119			`reg [7:0] p0_out;`
120
121			`assign p0_data = rmw ? p0_out : p0_in;`
122			`endif
123
124
125			`ifdef OC8051_PORT1
126			`input [7:0] p1_in;`
127			`output [7:0] p1_out,`
128			`p1_data;`
129			`reg [7:0] p1_out;`
130
131			`assign p1_data = rmw ? p1_out : p1_in;`
132			`endif
133
134
135			`ifdef OC8051_PORT2
136			`input [7:0] p2_in;`
137			`output [7:0] p2_out,`
138			`p2_data;`
139			`reg [7:0] p2_out;`
140
141			`assign p2_data = rmw ? p2_out : p2_in;`
142			`endif
143
144
145			`ifdef OC8051_PORT3
146			`input [7:0] p3_in;`
147			`output [7:0] p3_out,`
148			`p3_data;`
149			`reg [7:0] p3_out;`
150
151			`assign p3_data = rmw ? p3_out : p3_in;`
152			`endif
153
154			`//`
155			`// case of writing to port`
156	25	dinesha	`always @(posedge clk or negedge resetn)`
157	2	dinesha	`begin`
158	25	dinesha	`if (resetn == 1'b0) begin`
159	2	dinesha	`ifdef OC8051_PORT0
160	36	dinesha	p0_out <= `OC8051_RST_P0;
161	2	dinesha	`endif
162
163			`ifdef OC8051_PORT1
164	36	dinesha	p1_out <= `OC8051_RST_P1;
165	2	dinesha	`endif
166
167			`ifdef OC8051_PORT2
168	36	dinesha	p2_out <= `OC8051_RST_P2;
169	2	dinesha	`endif
170
171			`ifdef OC8051_PORT3
172	36	dinesha	p3_out <= `OC8051_RST_P3;
173	2	dinesha	`endif
174			`end else if (wr) begin`
175			`if (!wr_bit) begin`
176			`case (wr_addr) /* synopsys full_case parallel_case */`
177			`//`
178			`// bytaddresable`
179			`ifdef OC8051_PORT0
180	36	dinesha	`OC8051_SFR_P0: begin p0_out <= data_in;
181	2	dinesha	`end`
182			`endif
183
184			`ifdef OC8051_PORT1
185	36	dinesha	`OC8051_SFR_P1: p1_out <= data_in;
186	2	dinesha	`endif
187
188			`ifdef OC8051_PORT2
189	36	dinesha	`OC8051_SFR_P2: p2_out <= data_in;
190	2	dinesha	`endif
191
192			`ifdef OC8051_PORT3
193	36	dinesha	`OC8051_SFR_P3: p3_out <= data_in;
194	2	dinesha	`endif
195	37	dinesha	`default : begin`
196			`ifdef OC8051_PORT0
197			`p0_out <= p0_out;`
198			`endif
199
200			`ifdef OC8051_PORT1
201			`p1_out <= p1_out;`
202			`endif
203
204			`ifdef OC8051_PORT2
205			`p2_out <= p2_out;`
206			`endif
207
208			`ifdef OC8051_PORT3
209			`p3_out <= p3_out;`
210			`endif
211
212			`end`
213	2	dinesha	`endcase`
214			`end else begin`
215			`case (wr_addr[7:3]) /* synopsys full_case parallel_case */`
216
217			`//`
218			`// bit addressable`
219			`ifdef OC8051_PORT0
220	36	dinesha	`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= bit_in;
221	2	dinesha	`endif
222
223			`ifdef OC8051_PORT1
224	36	dinesha	`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= bit_in;
225	2	dinesha	`endif
226
227			`ifdef OC8051_PORT2
228	36	dinesha	`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= bit_in;
229	2	dinesha	`endif
230
231			`ifdef OC8051_PORT3
232	36	dinesha	`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= bit_in;
233	2	dinesha	`endif
234	36	dinesha	`default: begin`
235			`ifdef OC8051_PORT0
236			p0_out <= `OC8051_RST_P0;
237			`endif
238
239			`ifdef OC8051_PORT1
240			p1_out <= `OC8051_RST_P1;
241			`endif
242
243			`ifdef OC8051_PORT2
244			p2_out <= `OC8051_RST_P2;
245			`endif
246
247			`ifdef OC8051_PORT3
248			p3_out <= `OC8051_RST_P3;
249			`endif
250			`end`
251	2	dinesha	`endcase`
252			`end`
253			`end`
254			`end`
255
256
257			`endmodule`
258

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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_ports.v] - Blame information for rev 37