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[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_uart.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores serial interface                                 ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////   uart for 8051 core                                         ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2003/04/29 11:25:42  simont
// prepared start of receiving if ren is not active.
//
// Revision 1.13  2003/04/10 08:57:16  simont
// remove signal sbuf_txd [12:11]
//
// Revision 1.12  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.11  2003/04/07 13:29:16  simont
// change uart to meet timing.
//
// Revision 1.10  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.9  2002/09/30 17:33:59  simont
// prepared header
//
//
 
`include "top_defines.v"
 
module oc8051_uart (rst, clk,
             bit_in, data_in,
             wr_addr,
             wr, wr_bit,
             rxd, txd,
             intr,
             brate2, t1_ow, pres_ow,
             rclk, tclk,
//registers
             scon, pcon, sbuf);
 
input        rst,
             clk,
             bit_in,
             wr,
             rxd,
             wr_bit,
             t1_ow,
             brate2,
             pres_ow,
             rclk,
             tclk;
input [7:0]  data_in,
             wr_addr;
 
output       txd,
             intr;
output [7:0] scon,
             pcon,
             sbuf;
 
 
reg t1_ow_buf;
//
reg [7:0] scon, pcon;
 
 
reg        txd,
           trans,
           receive,
           tx_done,
           rx_done,
           rxd_r,
           shift_tr,
           shift_re;
reg [1:0]  rx_sam;
reg [3:0]  tr_count,
           re_count;
reg [7:0]  sbuf_rxd;
reg [11:0] sbuf_rxd_tmp;
reg [10:0] sbuf_txd;
 
assign sbuf = sbuf_rxd;
assign intr = scon[1] | scon [0];
 
//
//serial port control register
//
wire ren, tb8, rb8, ri;
assign ren = scon[4];
assign tb8 = scon[3];
assign rb8 = scon[2];
assign ri  = scon[0];
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    scon <= #1 `OC8051_RST_SCON;
  else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
    scon <= #1 data_in;
  else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
    scon[wr_addr[2:0]] <= #1 bit_in;
  else if (tx_done)
    scon[1] <= #1 1'b1;
  else if (!rx_done) begin
    if (scon[7:6]==2'b00) begin
      scon[0] <= #1 1'b1;
    end else if ((sbuf_rxd_tmp[11]) | !(scon[5])) begin
      scon[0] <= #1 1'b1;
      scon[2] <= #1 sbuf_rxd_tmp[11];
    end else
      scon[2] <= #1 sbuf_rxd_tmp[11];
  end
end
 
//
//power control register
//
wire smod;
assign smod = pcon[7];
always @(posedge clk or posedge rst)
begin
  if (rst)
  begin
    pcon <= #1 `OC8051_RST_PCON;
  end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
    pcon <= #1 data_in;
end
 
 
//
//serial port buffer (transmit)
//
 
wire wr_sbuf;
assign wr_sbuf = (wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit);
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    txd      <= #1 1'b1;
    tr_count <= #1 4'd0;
    trans    <= #1 1'b0;
    sbuf_txd <= #1 11'h00;
    tx_done  <= #1 1'b0;
//
// start transmiting
//
  end else if (wr_sbuf) begin
    case (scon[7:6]) /* synopsys parallel_case */
      2'b00: begin  // mode 0
        sbuf_txd <= #1 {3'b001, data_in};
      end
      2'b01: begin // mode 1
        sbuf_txd <= #1 {2'b01, data_in, 1'b0};
      end
      default: begin  // mode 2 and mode 3
        sbuf_txd <= #1 {1'b1, tb8, data_in, 1'b0};
      end
    endcase
    trans    <= #1 1'b1;
    tr_count <= #1 4'd0;
    tx_done  <= #1 1'b0;
//
// transmiting
//
  end else if (trans & (scon[7:6] == 2'b00) & pres_ow) // mode 0
  begin
    if (~|sbuf_txd[10:1]) begin
      trans   <= #1 1'b0;
      tx_done <= #1 1'b1;
    end else begin
      {sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};
      tx_done         <= #1 1'b0;
    end
  end else if (trans & (scon[7:6] != 2'b00) & shift_tr) begin // mode 1, 2, 3
    tr_count <= #1 tr_count + 4'd1;
    if (~|tr_count) begin
      if (~|sbuf_txd[10:0]) begin
        trans   <= #1 1'b0;
        tx_done <= #1 1'b1;
        txd <= #1 1'b1;
      end else begin
        {sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};
        tx_done         <= #1 1'b0;
      end
    end
  end else if (!trans) begin
    txd     <= #1 1'b1;
    tx_done <= #1 1'b0;
  end
end
 
//
//
reg sc_clk_tr, smod_clk_tr;
always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or tclk)
begin
  if (scon[7:6]==8'b10) begin //mode 2
    sc_clk_tr = 1'b1;
  end else if (tclk) begin //
    sc_clk_tr = brate2;
  end else begin //
    sc_clk_tr = !t1_ow_buf & t1_ow;
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    smod_clk_tr <= #1 1'b0;
    shift_tr    <= #1 1'b0;
  end else if (sc_clk_tr) begin
    if (smod) begin
      shift_tr <= #1 1'b1;
    end else begin
      shift_tr    <= #1  smod_clk_tr;
      smod_clk_tr <= #1 !smod_clk_tr;
    end
  end else begin
    shift_tr <= #1 1'b0;
  end
end
 
 
//
//serial port buffer (receive)
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    re_count     <= #1 4'd0;
    receive      <= #1 1'b0;
    sbuf_rxd     <= #1 8'h00;
    sbuf_rxd_tmp <= #1 12'd0;
    rx_done      <= #1 1'b1;
    rxd_r        <= #1 1'b1;
    rx_sam       <= #1 2'b00;
  end else if (!rx_done) begin
    receive <= #1 1'b0;
    rx_done <= #1 1'b1;
    sbuf_rxd <= #1 sbuf_rxd_tmp[10:3];
  end else if (receive & (scon[7:6]==2'b00) & pres_ow) begin //mode 0
    {sbuf_rxd_tmp, rx_done} <= #1 {rxd, sbuf_rxd_tmp};
  end else if (receive & (scon[7:6]!=2'b00) & shift_re) begin //mode 1, 2, 3
    re_count <= #1 re_count + 4'd1;
    case (re_count) /* synopsys full_case parallel_case */
      4'h7: rx_sam[0] <= #1 rxd;
      4'h8: rx_sam[1] <= #1 rxd;
      4'h9: begin
        {sbuf_rxd_tmp, rx_done} <= #1 {(rxd==rx_sam[0] ? rxd : rx_sam[1]), sbuf_rxd_tmp};
      end
    endcase
//
//start receiving
//
  end else if (scon[7:6]==2'b00) begin //start mode 0
    rx_done <= #1 1'b1;
    if (ren && !ri && !receive) begin
      receive      <= #1 1'b1;
      sbuf_rxd_tmp <= #1 10'h0ff;
    end
  end else if (ren & shift_re) begin
    rxd_r <= #1 rxd;
    rx_done <= #1 1'b1;
    re_count <= #1 4'h0;
    receive <= #1 (rxd_r & !rxd);
    sbuf_rxd_tmp <= #1 10'h1ff;
  end else if (!ren) begin
    rxd_r <= #1 rxd;
  end else
    rx_done <= #1 1'b1;
end
 
//
//
reg sc_clk_re, smod_clk_re;
always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or rclk)
begin
  if (scon[7:6]==8'b10) begin //mode 2
    sc_clk_re = 1'b1;
  end else if (rclk) begin //
    sc_clk_re = brate2;
  end else begin //
    sc_clk_re = !t1_ow_buf & t1_ow;
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    smod_clk_re <= #1 1'b0;
    shift_re    <= #1 1'b0;
  end else if (sc_clk_re) begin
    if (smod) begin
      shift_re <= #1 1'b1;
    end else begin
      shift_re    <= #1  smod_clk_re;
      smod_clk_re <= #1 !smod_clk_re;
    end
  end else begin
    shift_re <= #1 1'b0;
  end
end
 
 
 
//
//
//
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    t1_ow_buf <= #1 1'b0;
  end else begin
    t1_ow_buf <= #1 t1_ow;
  end
end
 
 
 
endmodule
 

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Subversion Repositories oms8051mini

[/] [oms8051mini/] [trunk/] [rtl/] [8051/] [oc8051_uart.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores serial interface ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// uart for 8051 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// - Dinesh Annayya, dinesha@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.14 2003/04/29 11:25:42 simont`
49			`// prepared start of receiving if ren is not active.`
50			`//`
51			`// Revision 1.13 2003/04/10 08:57:16 simont`
52			`// remove signal sbuf_txd [12:11]`
53			`//`
54			`// Revision 1.12 2003/04/07 14:58:02 simont`
55			`// change sfr's interface.`
56			`//`
57			`// Revision 1.11 2003/04/07 13:29:16 simont`
58			`// change uart to meet timing.`
59			`//`
60			`// Revision 1.10 2003/01/13 14:14:41 simont`
61			`// replace some modules`
62			`//`
63			`// Revision 1.9 2002/09/30 17:33:59 simont`
64			`// prepared header`
65			`//`
66			`//`
67
68			`include "top_defines.v"
69
70			`module oc8051_uart (rst, clk,`
71			`bit_in, data_in,`
72			`wr_addr,`
73			`wr, wr_bit,`
74			`rxd, txd,`
75			`intr,`
76			`brate2, t1_ow, pres_ow,`
77			`rclk, tclk,`
78			`//registers`
79			`scon, pcon, sbuf);`
80
81			`input rst,`
82			`clk,`
83			`bit_in,`
84			`wr,`
85			`rxd,`
86			`wr_bit,`
87			`t1_ow,`
88			`brate2,`
89			`pres_ow,`
90			`rclk,`
91			`tclk;`
92			`input [7:0] data_in,`
93			`wr_addr;`
94
95			`output txd,`
96			`intr;`
97			`output [7:0] scon,`
98			`pcon,`
99			`sbuf;`
100
101
102			`reg t1_ow_buf;`
103			`//`
104			`reg [7:0] scon, pcon;`
105
106
107			`reg txd,`
108			`trans,`
109			`receive,`
110			`tx_done,`
111			`rx_done,`
112			`rxd_r,`
113			`shift_tr,`
114			`shift_re;`
115			`reg [1:0] rx_sam;`
116			`reg [3:0] tr_count,`
117			`re_count;`
118			`reg [7:0] sbuf_rxd;`
119			`reg [11:0] sbuf_rxd_tmp;`
120			`reg [10:0] sbuf_txd;`
121
122			`assign sbuf = sbuf_rxd;`
123			`assign intr = scon[1] \| scon [0];`
124
125			`//`
126			`//serial port control register`
127			`//`
128			`wire ren, tb8, rb8, ri;`
129			`assign ren = scon[4];`
130			`assign tb8 = scon[3];`
131			`assign rb8 = scon[2];`
132			`assign ri = scon[0];`
133
134			`always @(posedge clk or posedge rst)`
135			`begin`
136			`if (rst)`
137			scon <= #1 `OC8051_RST_SCON;
138			else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
139			`scon <= #1 data_in;`
140			else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
141			`scon[wr_addr[2:0]] <= #1 bit_in;`
142			`else if (tx_done)`
143			`scon[1] <= #1 1'b1;`
144			`else if (!rx_done) begin`
145			`if (scon[7:6]==2'b00) begin`
146			`scon[0] <= #1 1'b1;`
147			`end else if ((sbuf_rxd_tmp[11]) \| !(scon[5])) begin`
148			`scon[0] <= #1 1'b1;`
149			`scon[2] <= #1 sbuf_rxd_tmp[11];`
150			`end else`
151			`scon[2] <= #1 sbuf_rxd_tmp[11];`
152			`end`
153			`end`
154
155			`//`
156			`//power control register`
157			`//`
158			`wire smod;`
159			`assign smod = pcon[7];`
160			`always @(posedge clk or posedge rst)`
161			`begin`
162			`if (rst)`
163			`begin`
164			pcon <= #1 `OC8051_RST_PCON;
165			end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
166			`pcon <= #1 data_in;`
167			`end`
168
169
170			`//`
171			`//serial port buffer (transmit)`
172			`//`
173
174			`wire wr_sbuf;`
175			assign wr_sbuf = (wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit);
176
177			`always @(posedge clk or posedge rst)`
178			`begin`
179			`if (rst) begin`
180			`txd <= #1 1'b1;`
181			`tr_count <= #1 4'd0;`
182			`trans <= #1 1'b0;`
183			`sbuf_txd <= #1 11'h00;`
184			`tx_done <= #1 1'b0;`
185			`//`
186			`// start transmiting`
187			`//`
188			`end else if (wr_sbuf) begin`
189			`case (scon[7:6]) /* synopsys parallel_case */`
190			`2'b00: begin // mode 0`
191			`sbuf_txd <= #1 {3'b001, data_in};`
192			`end`
193			`2'b01: begin // mode 1`
194			`sbuf_txd <= #1 {2'b01, data_in, 1'b0};`
195			`end`
196			`default: begin // mode 2 and mode 3`
197			`sbuf_txd <= #1 {1'b1, tb8, data_in, 1'b0};`
198			`end`
199			`endcase`
200			`trans <= #1 1'b1;`
201			`tr_count <= #1 4'd0;`
202			`tx_done <= #1 1'b0;`
203			`//`
204			`// transmiting`
205			`//`
206			`end else if (trans & (scon[7:6] == 2'b00) & pres_ow) // mode 0`
207			`begin`
208			`if (~\|sbuf_txd[10:1]) begin`
209			`trans <= #1 1'b0;`
210			`tx_done <= #1 1'b1;`
211			`end else begin`
212			`{sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};`
213			`tx_done <= #1 1'b0;`
214			`end`
215			`end else if (trans & (scon[7:6] != 2'b00) & shift_tr) begin // mode 1, 2, 3`
216			`tr_count <= #1 tr_count + 4'd1;`
217			`if (~\|tr_count) begin`
218			`if (~\|sbuf_txd[10:0]) begin`
219			`trans <= #1 1'b0;`
220			`tx_done <= #1 1'b1;`
221			`txd <= #1 1'b1;`
222			`end else begin`
223			`{sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};`
224			`tx_done <= #1 1'b0;`
225			`end`
226			`end`
227			`end else if (!trans) begin`
228			`txd <= #1 1'b1;`
229			`tx_done <= #1 1'b0;`
230			`end`
231			`end`
232
233			`//`
234			`//`
235			`reg sc_clk_tr, smod_clk_tr;`
236			`always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or tclk)`
237			`begin`
238			`if (scon[7:6]==8'b10) begin //mode 2`
239			`sc_clk_tr = 1'b1;`
240			`end else if (tclk) begin //`
241			`sc_clk_tr = brate2;`
242			`end else begin //`
243			`sc_clk_tr = !t1_ow_buf & t1_ow;`
244			`end`
245			`end`
246
247			`always @(posedge clk or posedge rst)`
248			`begin`
249			`if (rst) begin`
250			`smod_clk_tr <= #1 1'b0;`
251			`shift_tr <= #1 1'b0;`
252			`end else if (sc_clk_tr) begin`
253			`if (smod) begin`
254			`shift_tr <= #1 1'b1;`
255			`end else begin`
256			`shift_tr <= #1 smod_clk_tr;`
257			`smod_clk_tr <= #1 !smod_clk_tr;`
258			`end`
259			`end else begin`
260			`shift_tr <= #1 1'b0;`
261			`end`
262			`end`
263
264
265			`//`
266			`//serial port buffer (receive)`
267			`//`
268			`always @(posedge clk or posedge rst)`
269			`begin`
270			`if (rst) begin`
271			`re_count <= #1 4'd0;`
272			`receive <= #1 1'b0;`
273			`sbuf_rxd <= #1 8'h00;`
274			`sbuf_rxd_tmp <= #1 12'd0;`
275			`rx_done <= #1 1'b1;`
276			`rxd_r <= #1 1'b1;`
277			`rx_sam <= #1 2'b00;`
278			`end else if (!rx_done) begin`
279			`receive <= #1 1'b0;`
280			`rx_done <= #1 1'b1;`
281			`sbuf_rxd <= #1 sbuf_rxd_tmp[10:3];`
282			`end else if (receive & (scon[7:6]==2'b00) & pres_ow) begin //mode 0`
283			`{sbuf_rxd_tmp, rx_done} <= #1 {rxd, sbuf_rxd_tmp};`
284			`end else if (receive & (scon[7:6]!=2'b00) & shift_re) begin //mode 1, 2, 3`
285			`re_count <= #1 re_count + 4'd1;`
286			`case (re_count) /* synopsys full_case parallel_case */`
287			`4'h7: rx_sam[0] <= #1 rxd;`
288			`4'h8: rx_sam[1] <= #1 rxd;`
289			`4'h9: begin`
290			`{sbuf_rxd_tmp, rx_done} <= #1 {(rxd==rx_sam[0] ? rxd : rx_sam[1]), sbuf_rxd_tmp};`
291			`end`
292			`endcase`
293			`//`
294			`//start receiving`
295			`//`
296			`end else if (scon[7:6]==2'b00) begin //start mode 0`
297			`rx_done <= #1 1'b1;`
298			`if (ren && !ri && !receive) begin`
299			`receive <= #1 1'b1;`
300			`sbuf_rxd_tmp <= #1 10'h0ff;`
301			`end`
302			`end else if (ren & shift_re) begin`
303			`rxd_r <= #1 rxd;`
304			`rx_done <= #1 1'b1;`
305			`re_count <= #1 4'h0;`
306			`receive <= #1 (rxd_r & !rxd);`
307			`sbuf_rxd_tmp <= #1 10'h1ff;`
308			`end else if (!ren) begin`
309			`rxd_r <= #1 rxd;`
310			`end else`
311			`rx_done <= #1 1'b1;`
312			`end`
313
314			`//`
315			`//`
316			`reg sc_clk_re, smod_clk_re;`
317			`always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or rclk)`
318			`begin`
319			`if (scon[7:6]==8'b10) begin //mode 2`
320			`sc_clk_re = 1'b1;`
321			`end else if (rclk) begin //`
322			`sc_clk_re = brate2;`
323			`end else begin //`
324			`sc_clk_re = !t1_ow_buf & t1_ow;`
325			`end`
326			`end`
327
328			`always @(posedge clk or posedge rst)`
329			`begin`
330			`if (rst) begin`
331			`smod_clk_re <= #1 1'b0;`
332			`shift_re <= #1 1'b0;`
333			`end else if (sc_clk_re) begin`
334			`if (smod) begin`
335			`shift_re <= #1 1'b1;`
336			`end else begin`
337			`shift_re <= #1 smod_clk_re;`
338			`smod_clk_re <= #1 !smod_clk_re;`
339			`end`
340			`end else begin`
341			`shift_re <= #1 1'b0;`
342			`end`
343			`end`
344
345
346
347			`//`
348			`//`
349			`//`
350
351			`always @(posedge clk or posedge rst)`
352			`begin`
353			`if (rst) begin`
354			`t1_ow_buf <= #1 1'b0;`
355			`end else begin`
356			`t1_ow_buf <= #1 t1_ow;`
357			`end`
358			`end`
359
360
361
362			`endmodule`
363