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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OMS 8051 Digital core Module                                ////
////                                                              ////
////  This file is part of the OMS 8051 cores project             ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////  OMS 8051 definitions.                                       ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision : Nov 26, 2016                                     //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////
//     v0.0 - Dinesh A, 26th Nov 2016
//          1. MAC related logic are remved
//     v0.1 - Dinesh A, 1st Dec 2016
//          1. RAM and ROM are internally connected to interconnect
//          2. Memory Map Change
//          3. Remove the External ROM Option & Enabled Internal ROM
//     v0.2 - Dinesh A, 9st Dec 2016
//          1. Bus interface is changed from 32 bit to 8 bit
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "top_defines.v"
module digital_core  (
 
             reset_n                ,
             scan_mode              ,
             scan_enable             ,
             fastsim_mode           ,
             mastermode             ,
             xtal_clk               ,
             clkout                 ,
             reset_out_n            ,
             ea_in                  ,
 
        // Reg Bus Interface Signal
             ext_reg_cs             ,
             ext_reg_tid            ,
             ext_reg_wr             ,
             ext_reg_addr           ,
             ext_reg_wdata          ,
 
            // Outputs
             ext_reg_rdata          ,
             ext_reg_ack            ,
 
 
 
       // UART Line Interface
             si                     ,
             so                     ,
 
 
             spi_sck                ,
             spi_so                 ,
             spi_si                 ,
             spi_cs_n
 
 
 
 
 
        );
 
 
//----------------------------------------
// Global Clock Defination
//----------------------------------------
input            reset_n               ; // Active Low Reset           
input            scan_mode             ; // scan mode
input            scan_enable           ; // scan enable
input            fastsim_mode          ; // Fast Sim Mode
input            mastermode            ; // 1 : Risc master mode
input            ea_in                  ; // input for external access (ea signal)
                                          // ea=0 program is in external rom
                                          // ea=1 program is in internal rom
 
input            xtal_clk              ; // xtal clock 25Mhz
output           clkout                ; // clock output
output           reset_out_n           ; // clock output
 
//---------------------------------
// Reg Bus Interface Signal
//---------------------------------
input            ext_reg_cs            ;
input            ext_reg_wr            ;
input [3:0]      ext_reg_tid           ;
input [14:0]     ext_reg_addr          ;
input [7:0]      ext_reg_wdata         ;
 
// Outputs
output [7:0]     ext_reg_rdata         ;
output           ext_reg_ack           ;
 
 
 
//----------------------------------------
// UART Line Interface
//----------------------------------------
input            si                     ; // serial in
output           so                     ; // serial out
 
//----------------------------------------
// SPI Line Interface
//----------------------------------------
 
output           spi_sck                ; // clock
output           spi_so                 ; // data out
input            spi_si                 ; // data in
output  [3:0]    spi_cs_n               ; // chip select
 
 
//----------------------------------------
// 8051 core RAM related signals
//---------------------------------------
wire [15:0]      wb_xram_adr            ; // data-ram address
wire             wb_xram_ack            ; // data-ram acknowlage
wire             wb_xram_err            ; // data-ram error
wire             wb_xram_wr             ; // data-ram error
wire [7:0]       wb_xram_rdata          ; // ram data input
wire [7:0]       wb_xram_wdata          ; // ram data input
 
wire             wb_xram_stb            ; // data-ram strobe
wire             wb_xram_cyc            ; // data-ram cycle
 
 
 
//-----------------------------
// wire Decleration
//-----------------------------
wire             gen_resetn             ;
 
 
//---------------------------------------------
// 8051 Instruction RAM interface
//---------------------------------------------
wire    [15:0]   wbd_risc_adr           ;
wire    [7:0]    wbd_risc_rdata         ;
wire    [7:0]    wbd_risc_wdata         ;
 
 
wire    [14:0]   reg_uart_addr          ;
wire    [7:0]    reg_uart_wdata         ;
wire    [7:0]    reg_uart_rdata         ;
wire             reg_uart_ack           ;
 
wire    [14:0]   reg_spi_addr           ;
wire    [7:0]    reg_spi_wdata          ;
wire    [7:0]    reg_spi_rdata          ;
wire             reg_spi_ack            ;
 
 
wire    [7:0]    p0              ;
wire    [7:0]    p1              ;
wire    [7:0]    p2              ;
wire    [7:0]    p3              ;
 
 
wire [7:0] reg_rdata = (reg_uart_ack) ? reg_uart_rdata :
                        (reg_spi_ack)  ? reg_spi_rdata : 'h0;
 
wire reg_ack = reg_uart_ack | reg_spi_ack;
 
 
assign reset_out_n = gen_resetn;
 
assign wb_xram_adr[15]    = 0;
 
//-------------------------------------------
// clock-gen  instantiation
//-------------------------------------------
clkgen u_clkgen (
               . reset_n                (reset_n               ),
               . fastsim_mode           (fastsim_mode          ),
               . mastermode             (mastermode            ),
               . xtal_clk               (xtal_clk              ),
               . clkout                 (clkout                ),
               . gen_resetn             (gen_resetn            ),
               . risc_reset             (risc_reset            ),
               . app_clk                (app_clk               ),
               . uart_ref_clk           (uart_clk_16x          )
 
              );
 
 
 
wire [7:0] wb_master2_rdata;
 
assign     wbd_risc_rdata = wb_master2_rdata[7:0];
 
//------------------------------
// 8051 Data Memory Map
// 0x0000 to 0x7FFFF  - Data Memory
// 0x8000 to 0x8FFF   - SPI 
// 0x9000 to 0x9FFF   - UART
//--------------------------------------------------------------
// Target ID Mapping
// 4'b0010 -- UART
// 4'b0001 -- SPI core
// 4'b0000 -- External RAM
//--------------------------------------------------------------
// 
wire [3:0] wbd_tar_id     = (wbd_risc_adr[15]    == 1'b0 ) ? 4'b0000 :
                            (wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :
                            (wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;
 
wb_crossbar #(.WB_MASTER(2),
              .WB_SLAVE(3),
              .D_WD(8),
              .BE_WD(1),
              .ADR_WD(15),
              .TAR_WD(4))
              u_wb_crossbar (
 
              .rst_n                    (gen_resetn           ),
              .clk                      (app_clk              ),
 
 
    // Master Interface Signal
              .wbd_taddr_master         ({ wbd_tar_id,
                                          ext_reg_tid }),
 
              .wbd_din_master           ({wbd_risc_wdata[7:0],
                                          ext_reg_wdata }
                                         ),
 
              .wbd_dout_master          ({wb_master2_rdata,
                                          ext_reg_rdata}),
 
              .wbd_adr_master           ({wbd_risc_adr[14:0],
                                          ext_reg_addr[14:0]}),
 
              .wbd_be_master            ({1'b1,1'b1}),
 
              .wbd_we_master            ({wbd_risc_we,ext_reg_wr }   ),
 
              .wbd_ack_master           ({wbd_risc_ack,
                                          ext_reg_ack } ),
 
              .wbd_stb_master           ({wbd_risc_stb,
                                          ext_reg_cs} ),
 
              .wbd_cyc_master           ({wbd_risc_stb|wbd_risc_ack,
                                          ext_reg_cs|ext_reg_ack }),
 
              .wbd_err_master           (),
              .wbd_rty_master           (),
 
    // Slave Interface Signal
              .wbd_din_slave            ({reg_uart_wdata,
                                          reg_spi_wdata,
                                          wb_xram_wdata
                                          }),
 
              .wbd_dout_slave           ({reg_uart_rdata,
                                          reg_spi_rdata,
                                          wb_xram_rdata
                                         }),
 
              .wbd_adr_slave            ({reg_uart_addr[14:0],
                                          reg_spi_addr[14:0],
                                          wb_xram_adr[14:0]}
                                        ),
 
              .wbd_be_slave             (),
 
              .wbd_we_slave             ({reg_uart_wr,
                                          reg_spi_wr,
                                          wb_xram_wr
                                          }),
 
              .wbd_ack_slave            ({reg_uart_ack,
                                          reg_spi_ack,
                                          wb_xram_ack
                                         }),
              .wbd_stb_slave            ({reg_uart_cs,
                                          reg_spi_cs,
                                          wb_xram_stb
                                         }),
 
              .wbd_cyc_slave            (),
              .wbd_err_slave            (),
              .wbd_rty_slave            ()
         );
 
 
 
//-------------------------------------
// UART core instantiation
//-------------------------------------
 
uart_core  u_uart_core
 
     (
          . app_reset_n                 (gen_resetn            ),
          . app_clk                     (app_clk               ),
 
 
        // Reg Bus Interface Signal
          . reg_cs                      (reg_uart_cs           ),
          . reg_wr                      (reg_uart_wr           ),
          . reg_addr                    (reg_uart_addr[3:0]    ),
          . reg_wdata                   (reg_uart_wdata        ),
          . reg_be                      (1'b1                  ),
 
            // Outputs
          . reg_rdata                   (reg_uart_rdata        ),
          . reg_ack                     (reg_uart_ack          ),
 
 
 
       // Line Interface
          . si                          (si                    ),
          . so                          (so                    )
 
     );
 
 
//--------------------------------
// SPI core instantiation
//--------------------------------
 
 
spi_core u_spi_core (
 
          . clk                         (app_clk               ),
          . reset_n                     (gen_resetn            ),
 
        // Reg Bus Interface Signal
          . reg_cs                      (reg_spi_cs            ),
          . reg_wr                      (reg_spi_wr            ),
          . reg_addr                    (reg_spi_addr[3:0]     ),
          . reg_wdata                   (reg_spi_wdata         ),
          . reg_be                      (1'b1                  ),
 
            // Outputs
          . reg_rdata                   (reg_spi_rdata         ),
          . reg_ack                     (reg_spi_ack           ),
 
 
          . sck                         (spi_sck               ),
          . so                          (spi_so                ),
          . si                          (spi_si                ),
          . cs_n                        (spi_cs_n              )
 
           );
 
 
 
oc8051_top u_8051_core (
          . wb_rst_i                    (risc_reset            ),
          . wb_clk_i                    (app_clk               ),
 
//interface to data ram
          . wbd_dat_i                   (wbd_risc_rdata        ),
          . wbd_dat_o                   (wbd_risc_wdata        ),
          . wbd_adr_o                   (wbd_risc_adr          ),
          . wbd_we_o                    (wbd_risc_we           ),
          . wbd_ack_i                   (wbd_risc_ack          ),
          . wbd_stb_o                   (wbd_risc_stb          ),
          . wbd_cyc_o                   (wbd_risc_cyc          ),
          . wbd_err_i                   (wbd_risc_err          ),
 
// interrupt interface
          . int0_i                      (                      ),
          . int1_i                      (                      ),
 
 
// port interface
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
          .p0_i                         ( p0                    ),
          .p0_o                         ( p0                    ),
        `endif
 
        `ifdef OC8051_PORT1
           .p1_i                        ( p1                    ),
           .p1_o                        ( p1                    ),
        `endif
 
        `ifdef OC8051_PORT2
           .p2_i                        ( p2                    ),
           .p2_o                        ( p2                    ),
        `endif
 
        `ifdef OC8051_PORT3
           .p3_i                        ( p3                    ),
           .p3_o                        ( p3                    ),
        `endif
  `endif
 
// serial interface
        `ifdef OC8051_UART
           .rxd_i                       (                      ),
           .txd_o                       (                      ),
        `endif
 
// counter interface
        `ifdef OC8051_TC01
           .t0_i                        (                      ),
           .t1_i                        (                      ),
        `endif
 
        `ifdef OC8051_TC2
           .t2_i                        (                      ),
           .t2ex_i                      (                      ),
        `endif
 
// BIST
`ifdef OC8051_BIST
            .scanb_rst                  (                      ),
            .scanb_clk                  (                      ),
            .scanb_si                   (                      ),
            .scanb_so                   (                      ),
            .scanb_en                   (                      ),
`endif
// external access (active low)
            .ea_in                      (ea_in                 )
         );
 
//
// external data ram
//
oc8051_xram oc8051_xram1 (
          .clk               (app_clk       ),
          .rst               (!reset_n      ),
          .wr                (wb_xram_wr    ),
          .addr              (wb_xram_adr   ),
          .data_in           (wb_xram_wdata ),
          .data_out          (wb_xram_rdata ),
          .ack               (wb_xram_ack   ),
          .stb               (wb_xram_stb   )
      );
 
 
defparam oc8051_xram1.DELAY = 2;
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	11	dinesha	`//// OMS 8051 Digital core Module ////`
4	2	dinesha	`//// ////`
5			`//// This file is part of the OMS 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// OMS 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//// Revision : Nov 26, 2016 ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20	10	dinesha	`// v0.0 - Dinesh A, 26th Nov 2016`
21	2	dinesha	`// 1. MAC related logic are remved`
22	10	dinesha	`// v0.1 - Dinesh A, 1st Dec 2016`
23			`// 1. RAM and ROM are internally connected to interconnect`
24			`// 2. Memory Map Change`
25			`// 3. Remove the External ROM Option & Enabled Internal ROM`
26	11	dinesha	`// v0.2 - Dinesh A, 9st Dec 2016`
27			`// 1. Bus interface is changed from 32 bit to 8 bit`
28	2	dinesha	`//////////////////////////////////////////////////////////////////////`
29			`//// ////`
30			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
31			`//// ////`
32			`//// This source file may be used and distributed without ////`
33			`//// restriction provided that this copyright statement is not ////`
34			`//// removed from the file and that any derivative work contains ////`
35			`//// the original copyright notice and the associated disclaimer. ////`
36			`//// ////`
37			`//// This source file is free software; you can redistribute it ////`
38			`//// and/or modify it under the terms of the GNU Lesser General ////`
39			`//// Public License as published by the Free Software Foundation; ////`
40			`//// either version 2.1 of the License, or (at your option) any ////`
41			`//// later version. ////`
42			`//// ////`
43			`//// This source is distributed in the hope that it will be ////`
44			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
45			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
46			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
47			`//// details. ////`
48			`//// ////`
49			`//// You should have received a copy of the GNU Lesser General ////`
50			`//// Public License along with this source; if not, download it ////`
51			`//// from http://www.opencores.org/lgpl.shtml ////`
52			`//// ////`
53			`//////////////////////////////////////////////////////////////////////`
54
55			`include "top_defines.v"
56			`module digital_core (`
57
58			`reset_n ,`
59			`scan_mode ,`
60			`scan_enable ,`
61			`fastsim_mode ,`
62			`mastermode ,`
63			`xtal_clk ,`
64			`clkout ,`
65			`reset_out_n ,`
66	10	dinesha	`ea_in ,`
67	2	dinesha
68			`// Reg Bus Interface Signal`
69			`ext_reg_cs ,`
70			`ext_reg_tid ,`
71			`ext_reg_wr ,`
72			`ext_reg_addr ,`
73			`ext_reg_wdata ,`
74
75			`// Outputs`
76			`ext_reg_rdata ,`
77			`ext_reg_ack ,`
78
79
80
81			`// UART Line Interface`
82			`si ,`
83			`so ,`
84
85
86			`spi_sck ,`
87			`spi_so ,`
88			`spi_si ,`
89	10	dinesha	`spi_cs_n`
90	2	dinesha
91
92
93
94
95			`);`
96
97
98			`//----------------------------------------`
99			`// Global Clock Defination`
100			`//----------------------------------------`
101			`input reset_n ; // Active Low Reset`
102			`input scan_mode ; // scan mode`
103			`input scan_enable ; // scan enable`
104			`input fastsim_mode ; // Fast Sim Mode`
105			`input mastermode ; // 1 : Risc master mode`
106	10	dinesha	`input ea_in ; // input for external access (ea signal)`
107			`// ea=0 program is in external rom`
108			`// ea=1 program is in internal rom`
109	2	dinesha
110			`input xtal_clk ; // xtal clock 25Mhz`
111			`output clkout ; // clock output`
112			`output reset_out_n ; // clock output`
113
114			`//---------------------------------`
115			`// Reg Bus Interface Signal`
116			`//---------------------------------`
117			`input ext_reg_cs ;`
118			`input ext_reg_wr ;`
119			`input [3:0] ext_reg_tid ;`
120			`input [14:0] ext_reg_addr ;`
121	11	dinesha	`input [7:0] ext_reg_wdata ;`
122	2	dinesha
123			`// Outputs`
124	11	dinesha	`output [7:0] ext_reg_rdata ;`
125	2	dinesha	`output ext_reg_ack ;`
126
127
128
129			`//----------------------------------------`
130			`// UART Line Interface`
131			`//----------------------------------------`
132			`input si ; // serial in`
133			`output so ; // serial out`
134
135			`//----------------------------------------`
136			`// SPI Line Interface`
137			`//----------------------------------------`
138
139			`output spi_sck ; // clock`
140			`output spi_so ; // data out`
141			`input spi_si ; // data in`
142			`output [3:0] spi_cs_n ; // chip select`
143
144
145			`//----------------------------------------`
146			`// 8051 core RAM related signals`
147			`//---------------------------------------`
148	10	dinesha	`wire [15:0] wb_xram_adr ; // data-ram address`
149			`wire wb_xram_ack ; // data-ram acknowlage`
150			`wire wb_xram_err ; // data-ram error`
151			`wire wb_xram_wr ; // data-ram error`
152	11	dinesha	`wire [7:0] wb_xram_rdata ; // ram data input`
153			`wire [7:0] wb_xram_wdata ; // ram data input`
154	2	dinesha
155	10	dinesha	`wire wb_xram_stb ; // data-ram strobe`
156			`wire wb_xram_cyc ; // data-ram cycle`
157	2	dinesha
158
159
160			`//-----------------------------`
161			`// wire Decleration`
162			`//-----------------------------`
163			`wire gen_resetn ;`
164
165
166			`//---------------------------------------------`
167			`// 8051 Instruction RAM interface`
168			`//---------------------------------------------`
169			`wire [15:0] wbd_risc_adr ;`
170			`wire [7:0] wbd_risc_rdata ;`
171			`wire [7:0] wbd_risc_wdata ;`
172
173
174			`wire [14:0] reg_uart_addr ;`
175	11	dinesha	`wire [7:0] reg_uart_wdata ;`
176			`wire [7:0] reg_uart_rdata ;`
177	2	dinesha	`wire reg_uart_ack ;`
178
179			`wire [14:0] reg_spi_addr ;`
180	11	dinesha	`wire [7:0] reg_spi_wdata ;`
181			`wire [7:0] reg_spi_rdata ;`
182	2	dinesha	`wire reg_spi_ack ;`
183
184
185			`wire [7:0] p0 ;`
186			`wire [7:0] p1 ;`
187			`wire [7:0] p2 ;`
188			`wire [7:0] p3 ;`
189
190
191	11	dinesha	`wire [7:0] reg_rdata = (reg_uart_ack) ? reg_uart_rdata :`
192	2	dinesha	`(reg_spi_ack) ? reg_spi_rdata : 'h0;`
193
194			`wire reg_ack = reg_uart_ack \| reg_spi_ack;`
195
196
197			`assign reset_out_n = gen_resetn;`
198
199			`assign wb_xram_adr[15] = 0;`
200
201			`//-------------------------------------------`
202			`// clock-gen instantiation`
203			`//-------------------------------------------`
204			`clkgen u_clkgen (`
205			`. reset_n (reset_n ),`
206			`. fastsim_mode (fastsim_mode ),`
207			`. mastermode (mastermode ),`
208			`. xtal_clk (xtal_clk ),`
209			`. clkout (clkout ),`
210			`. gen_resetn (gen_resetn ),`
211			`. risc_reset (risc_reset ),`
212			`. app_clk (app_clk ),`
213			`. uart_ref_clk (uart_clk_16x )`
214
215			`);`
216
217
218
219	11	dinesha	`wire [7:0] wb_master2_rdata;`
220	2	dinesha
221	11	dinesha	`assign wbd_risc_rdata = wb_master2_rdata[7:0];`
222	2	dinesha
223			`//------------------------------`
224			`// 8051 Data Memory Map`
225			`// 0x0000 to 0x7FFFF - Data Memory`
226			`// 0x8000 to 0x8FFF - SPI`
227			`// 0x9000 to 0x9FFF - UART`
228			`//--------------------------------------------------------------`
229			`// Target ID Mapping`
230	10	dinesha	`// 4'b0010 -- UART`
231			`// 4'b0001 -- SPI core`
232			`// 4'b0000 -- External RAM`
233	2	dinesha	`//--------------------------------------------------------------`
234			`//`
235	10	dinesha	`wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0000 :`
236			`(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0001 :`
237			`(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0010 : 4'b0000;`
238	2	dinesha
239	14	dinesha	`wb_crossbar #(.WB_MASTER(2),`
240	10	dinesha	`.WB_SLAVE(3),`
241	11	dinesha	`.D_WD(8),`
242			`.BE_WD(1),`
243			`.ADR_WD(15),`
244	2	dinesha	`.TAR_WD(4))`
245			`u_wb_crossbar (`
246
247			`.rst_n (gen_resetn ),`
248			`.clk (app_clk ),`
249
250
251			`// Master Interface Signal`
252	14	dinesha	`.wbd_taddr_master ({ wbd_tar_id,`
253	2	dinesha	`ext_reg_tid }),`
254
255	14	dinesha	`.wbd_din_master ({wbd_risc_wdata[7:0],`
256	2	dinesha	`ext_reg_wdata }`
257			`),`
258
259	14	dinesha	`.wbd_dout_master ({wb_master2_rdata,`
260	2	dinesha	`ext_reg_rdata}),`
261
262	14	dinesha	`.wbd_adr_master ({wbd_risc_adr[14:0],`
263	11	dinesha	`ext_reg_addr[14:0]}),`
264	2	dinesha
265	14	dinesha	`.wbd_be_master ({1'b1,1'b1}),`
266	2	dinesha
267	14	dinesha	`.wbd_we_master ({wbd_risc_we,ext_reg_wr } ),`
268	2	dinesha
269	14	dinesha	`.wbd_ack_master ({wbd_risc_ack,`
270	2	dinesha	`ext_reg_ack } ),`
271
272	14	dinesha	`.wbd_stb_master ({wbd_risc_stb,`
273	2	dinesha	`ext_reg_cs} ),`
274
275	14	dinesha	`.wbd_cyc_master ({wbd_risc_stb\|wbd_risc_ack,`
276	2	dinesha	`ext_reg_cs\|ext_reg_ack }),`
277
278			`.wbd_err_master (),`
279			`.wbd_rty_master (),`
280
281			`// Slave Interface Signal`
282			`.wbd_din_slave ({reg_uart_wdata,`
283			`reg_spi_wdata,`
284	10	dinesha	`wb_xram_wdata`
285	2	dinesha	`}),`
286
287			`.wbd_dout_slave ({reg_uart_rdata,`
288			`reg_spi_rdata,`
289	11	dinesha	`wb_xram_rdata`
290	2	dinesha	`}),`
291
292	11	dinesha	`.wbd_adr_slave ({reg_uart_addr[14:0],`
293			`reg_spi_addr[14:0],`
294			`wb_xram_adr[14:0]}`
295	2	dinesha	`),`
296
297	11	dinesha	`.wbd_be_slave (),`
298	2	dinesha
299			`.wbd_we_slave ({reg_uart_wr,`
300			`reg_spi_wr,`
301	10	dinesha	`wb_xram_wr`
302	2	dinesha	`}),`
303
304			`.wbd_ack_slave ({reg_uart_ack,`
305			`reg_spi_ack,`
306	10	dinesha	`wb_xram_ack`
307	2	dinesha	`}),`
308			`.wbd_stb_slave ({reg_uart_cs,`
309			`reg_spi_cs,`
310	10	dinesha	`wb_xram_stb`
311	2	dinesha	`}),`
312
313			`.wbd_cyc_slave (),`
314			`.wbd_err_slave (),`
315			`.wbd_rty_slave ()`
316			`);`
317
318
319
320			`//-------------------------------------`
321			`// UART core instantiation`
322			`//-------------------------------------`
323
324			`uart_core u_uart_core`
325
326			`(`
327			`. app_reset_n (gen_resetn ),`
328			`. app_clk (app_clk ),`
329
330
331			`// Reg Bus Interface Signal`
332			`. reg_cs (reg_uart_cs ),`
333			`. reg_wr (reg_uart_wr ),`
334	11	dinesha	`. reg_addr (reg_uart_addr[3:0] ),`
335	2	dinesha	`. reg_wdata (reg_uart_wdata ),`
336	11	dinesha	`. reg_be (1'b1 ),`
337	2	dinesha
338			`// Outputs`
339			`. reg_rdata (reg_uart_rdata ),`
340			`. reg_ack (reg_uart_ack ),`
341
342
343
344			`// Line Interface`
345			`. si (si ),`
346			`. so (so )`
347
348			`);`
349
350
351			`//--------------------------------`
352			`// SPI core instantiation`
353			`//--------------------------------`
354
355
356			`spi_core u_spi_core (`
357
358			`. clk (app_clk ),`
359			`. reset_n (gen_resetn ),`
360
361			`// Reg Bus Interface Signal`
362			`. reg_cs (reg_spi_cs ),`
363			`. reg_wr (reg_spi_wr ),`
364	11	dinesha	`. reg_addr (reg_spi_addr[3:0] ),`
365	2	dinesha	`. reg_wdata (reg_spi_wdata ),`
366	11	dinesha	`. reg_be (1'b1 ),`
367	2	dinesha
368			`// Outputs`
369			`. reg_rdata (reg_spi_rdata ),`
370			`. reg_ack (reg_spi_ack ),`
371
372
373			`. sck (spi_sck ),`
374			`. so (spi_so ),`
375			`. si (spi_si ),`
376			`. cs_n (spi_cs_n )`
377
378			`);`
379
380
381
382			`oc8051_top u_8051_core (`
383			`. wb_rst_i (risc_reset ),`
384			`. wb_clk_i (app_clk ),`
385
386			`//interface to data ram`
387			`. wbd_dat_i (wbd_risc_rdata ),`
388			`. wbd_dat_o (wbd_risc_wdata ),`
389			`. wbd_adr_o (wbd_risc_adr ),`
390			`. wbd_we_o (wbd_risc_we ),`
391			`. wbd_ack_i (wbd_risc_ack ),`
392			`. wbd_stb_o (wbd_risc_stb ),`
393			`. wbd_cyc_o (wbd_risc_cyc ),`
394			`. wbd_err_i (wbd_risc_err ),`
395
396			`// interrupt interface`
397			`. int0_i ( ),`
398			`. int1_i ( ),`
399
400
401			`// port interface`
402			`ifdef OC8051_PORTS
403			`ifdef OC8051_PORT0
404			`.p0_i ( p0 ),`
405			`.p0_o ( p0 ),`
406			`endif
407
408			`ifdef OC8051_PORT1
409			`.p1_i ( p1 ),`
410			`.p1_o ( p1 ),`
411			`endif
412
413			`ifdef OC8051_PORT2
414			`.p2_i ( p2 ),`
415			`.p2_o ( p2 ),`
416			`endif
417
418			`ifdef OC8051_PORT3
419			`.p3_i ( p3 ),`
420			`.p3_o ( p3 ),`
421			`endif
422			`endif
423
424			`// serial interface`
425			`ifdef OC8051_UART
426			`.rxd_i ( ),`
427			`.txd_o ( ),`
428			`endif
429
430			`// counter interface`
431			`ifdef OC8051_TC01
432			`.t0_i ( ),`
433			`.t1_i ( ),`
434			`endif
435
436			`ifdef OC8051_TC2
437			`.t2_i ( ),`
438			`.t2ex_i ( ),`
439			`endif
440
441			`// BIST`
442			`ifdef OC8051_BIST
443			`.scanb_rst ( ),`
444			`.scanb_clk ( ),`
445			`.scanb_si ( ),`
446			`.scanb_so ( ),`
447			`.scanb_en ( ),`
448			`endif
449			`// external access (active low)`
450			`.ea_in (ea_in )`
451			`);`
452
453	10	dinesha	`//`
454			`// external data ram`
455			`//`
456			`oc8051_xram oc8051_xram1 (`
457			`.clk (app_clk ),`
458			`.rst (!reset_n ),`
459			`.wr (wb_xram_wr ),`
460			`.addr (wb_xram_adr ),`
461			`.data_in (wb_xram_wdata ),`
462			`.data_out (wb_xram_rdata ),`
463			`.ack (wb_xram_ack ),`
464			`.stb (wb_xram_stb )`
465			`);`
466
467
468			`defparam oc8051_xram1.DELAY = 2;`
469	2	dinesha	`endmodule`

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