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[/] [oms8051mini/] [trunk/] [rtl/] [core/] [digital_core.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OMS 8051 Dgital core Module                                 ////
////                                                              ////
////  This file is part of the OMS 8051 cores project             ////
////  http://www.opencores.org/cores/oms8051mini/                 ////
////                                                              ////
////  Description                                                 ////
////  OMS 8051 definitions.                                       ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision : Nov 26, 2016                                     //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////
//     v0 - Dinesh A, 26th Nov 2016
//          1. MAC related logic are remved
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "top_defines.v"
module digital_core  (
 
             reset_n                ,
             scan_mode              ,
             scan_enable             ,
             fastsim_mode           ,
             mastermode             ,
             xtal_clk               ,
             clkout                 ,
             reset_out_n            ,
 
        // Reg Bus Interface Signal
             ext_reg_cs             ,
             ext_reg_tid            ,
             ext_reg_wr             ,
             ext_reg_addr           ,
             ext_reg_wdata          ,
             ext_reg_be             ,
 
            // Outputs
             ext_reg_rdata          ,
             ext_reg_ack            ,
 
 
 
       // UART Line Interface
             si                     ,
             so                     ,
 
 
             spi_sck                ,
             spi_so                 ,
             spi_si                 ,
             spi_cs_n               ,
 
 
         // External ROM interface
             wb_xrom_adr            ,
             wb_xrom_ack            ,
             wb_xrom_err            ,
             wb_xrom_wr             ,
             wb_xrom_rdata          ,
             wb_xrom_wdata          ,
 
             wb_xrom_stb            ,
             wb_xrom_cyc            ,
 
         // External RAM interface
             wb_xram_adr            ,
             wb_xram_ack            ,
             wb_xram_err            ,
             wb_xram_wr             ,
             wb_xram_be             ,
             wb_xram_rdata          ,
             wb_xram_wdata          ,
 
             wb_xram_stb            ,
             wb_xram_cyc,
 
             ea_in
 
 
 
        );
 
 
//----------------------------------------
// Global Clock Defination
//----------------------------------------
input            reset_n               ; // Active Low Reset           
input            scan_mode             ; // scan mode
input            scan_enable           ; // scan enable
input            fastsim_mode          ; // Fast Sim Mode
input            mastermode            ; // 1 : Risc master mode
 
input            xtal_clk              ; // xtal clock 25Mhz
output           clkout                ; // clock output
output           reset_out_n           ; // clock output
 
//---------------------------------
// Reg Bus Interface Signal
//---------------------------------
input            ext_reg_cs            ;
input            ext_reg_wr            ;
input [3:0]      ext_reg_tid           ;
input [14:0]     ext_reg_addr          ;
input [31:0]     ext_reg_wdata         ;
input [3:0]      ext_reg_be            ;
 
// Outputs
output [31:0]    ext_reg_rdata         ;
output           ext_reg_ack           ;
 
 
 
//----------------------------------------
// UART Line Interface
//----------------------------------------
input            si                     ; // serial in
output           so                     ; // serial out
 
//----------------------------------------
// SPI Line Interface
//----------------------------------------
 
output           spi_sck                ; // clock
output           spi_so                 ; // data out
input            spi_si                 ; // data in
output  [3:0]    spi_cs_n               ; // chip select
 
//----------------------------------------
// 8051 core ROM related signals
//---------------------------------------
output [15:0]    wb_xrom_adr            ; // instruction address
input            wb_xrom_ack            ; // instruction acknowlage
output           wb_xrom_err            ; // instruction error
output           wb_xrom_wr             ; // instruction error
input  [31:0]    wb_xrom_rdata          ; // rom data input
output [31:0]    wb_xrom_wdata          ; // rom data input
 
output           wb_xrom_stb            ; // instruction strobe
output           wb_xrom_cyc            ; // instruction cycle
 
 
//----------------------------------------
// 8051 core RAM related signals
//---------------------------------------
output [15:0]    wb_xram_adr            ; // data-ram address
input            wb_xram_ack            ; // data-ram acknowlage
output           wb_xram_err            ; // data-ram error
output           wb_xram_wr             ; // data-ram error
output [3:0]     wb_xram_be             ; // Byte enable
input  [31:0]    wb_xram_rdata          ; // ram data input
output [31:0]    wb_xram_wdata          ; // ram data input
 
output           wb_xram_stb            ; // data-ram strobe
output           wb_xram_cyc            ; // data-ram cycle
 
 
input            ea_in                  ; // input for external access (ea signal)
                                          // ea=0 program is in external rom
                                          // ea=1 program is in internal rom
//---------------------------------------------
// 8051 Instruction ROM interface
//---------------------------------------------
wire    [15:0]   wbi_risc_adr;
wire    [31:0]   wbi_risc_rdata;
 
 
//-----------------------------
// wire Decleration
//-----------------------------
wire             gen_resetn             ;
 
 
//---------------------------------------------
// 8051 Instruction RAM interface
//---------------------------------------------
wire    [15:0]   wbd_risc_adr           ;
wire    [7:0]    wbd_risc_rdata         ;
wire    [7:0]    wbd_risc_wdata         ;
 
 
wire    [14:0]   reg_uart_addr          ;
wire    [31:0]   reg_uart_wdata         ;
wire    [3:0]    reg_uart_be            ;
wire    [31:0]   reg_uart_rdata         ;
wire             reg_uart_ack           ;
 
wire    [14:0]   reg_spi_addr           ;
wire    [31:0]   reg_spi_wdata          ;
wire    [3:0]    reg_spi_be             ;
wire    [31:0]   reg_spi_rdata          ;
wire             reg_spi_ack            ;
 
wire    [3:0]    wb_xrom_be            ;
wire    [3:0]    wb_xram_be            ;
 
wire    [7:0]    p0              ;
wire    [7:0]    p1              ;
wire    [7:0]    p2              ;
wire    [7:0]    p3              ;
 
 
wire [31:0] reg_rdata = (reg_uart_ack) ? reg_uart_rdata :
                        (reg_spi_ack)  ? reg_spi_rdata : 'h0;
 
wire reg_ack = reg_uart_ack | reg_spi_ack;
 
 
assign reset_out_n = gen_resetn;
 
 
assign wb_xram_adr[15]    = 0;
assign wb_xram_adr[1:0]   = 2'b00;
assign wb_xrom_adr[15:13] = 0;
 
wire [9:0] cfg_tx_buf_qbase_addr;
wire [9:0] cfg_rx_buf_qbase_addr;
 
 
assign reg_uart_addr[1:0] = 2'b0;
assign reg_spi_addr[1:0] = 2'b0;
//-------------------------------------------
// clock-gen  instantiation
//-------------------------------------------
clkgen u_clkgen (
               . reset_n                (reset_n               ),
               . fastsim_mode           (fastsim_mode          ),
               . mastermode             (mastermode            ),
               . xtal_clk               (xtal_clk              ),
               . clkout                 (clkout                ),
               . gen_resetn             (gen_resetn            ),
               . risc_reset             (risc_reset            ),
               . app_clk                (app_clk               ),
               . uart_ref_clk           (uart_clk_16x          )
 
              );
 
 
 
wire [31:0] wb_master2_rdata;
 
wire [3:0] wb_master2_be = (wbd_risc_adr[1:0] == 2'b00) ? 4'b0001:
                           (wbd_risc_adr[1:0] == 2'b01) ? 4'b0010:
                           (wbd_risc_adr[1:0] == 2'b10) ? 4'b0100: 4'b1000;
 
assign     wbd_risc_rdata = (wbd_risc_adr[1:0] == 2'b00) ? wb_master2_rdata[7:0]:
                            (wbd_risc_adr[1:0] == 2'b01) ? wb_master2_rdata[15:8]:
                            (wbd_risc_adr[1:0] == 2'b10) ? wb_master2_rdata[23:16]:
                            wb_master2_rdata[31:24];
 
//------------------------------
// 8051 Data Memory Map
// 0x0000 to 0x7FFFF  - Data Memory
// 0x8000 to 0x8FFF   - SPI 
// 0x9000 to 0x9FFF   - UART
// 0xA000 to 0xAFFF   - MAC Core
//--------------------------------------------------------------
// Target ID Mapping
// 4'b0100 -- MAC core
// 4'b0011 -- UART
// 4'b0010 -- SPI core
// 4'b0001 -- External RAM
// 4'b0000 -- External ROM
//--------------------------------------------------------------
// 
wire [3:0] wbd_tar_id     = (wbd_risc_adr[15]    == 1'b0 ) ? 4'b0001 :
                            (wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0010 :
                            (wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0011 : 4'b0100;
 
wb_crossbar #(.WB_MASTER(3),
              .WB_SLAVE(4),
              .D_WD(32),
              .BE_WD(4),
              .ADR_WD(13),
              .TAR_WD(4))
              u_wb_crossbar (
 
              .rst_n                    (gen_resetn           ),
              .clk                      (app_clk              ),
 
 
    // Master Interface Signal
              .wbd_taddr_master         ({4'b0000,
                                          wbd_tar_id,
                                          ext_reg_tid }),
 
              .wbd_din_master           ({32'h0 ,
                                          {wbd_risc_wdata[7:0],
                                          wbd_risc_wdata[7:0],
                                          wbd_risc_wdata[7:0],
                                          wbd_risc_wdata[7:0]},
                                          ext_reg_wdata }
                                         ),
 
              .wbd_dout_master          ({wbi_risc_rdata,
                                          wb_master2_rdata,
                                          ext_reg_rdata}),
 
              .wbd_adr_master           ({wbi_risc_adr[12:0],
                                          wbd_risc_adr[14:2],
                                          ext_reg_addr[14:2]}),
 
              .wbd_be_master            ({4'b1111,
                                          wb_master2_be,
                                          ext_reg_be }
                                           ),
 
              .wbd_we_master            ({1'b0,wbd_risc_we,ext_reg_wr }   ),
 
              .wbd_ack_master           ({wbi_risc_ack,
                                          wbd_risc_ack,
                                          ext_reg_ack } ),
 
              .wbd_stb_master           ({wbi_risc_stb,
                                          wbd_risc_stb,
                                          ext_reg_cs} ),
 
              .wbd_cyc_master           ({wbi_risc_stb|wbi_risc_ack,
                                          wbd_risc_stb|wbd_risc_ack,
                                          ext_reg_cs|ext_reg_ack }),
 
              .wbd_err_master           (),
              .wbd_rty_master           (),
 
    // Slave Interface Signal
              .wbd_din_slave            ({reg_uart_wdata,
                                          reg_spi_wdata,
                                          wb_xram_wdata,
                                          wb_xrom_wdata
                                          }),
 
              .wbd_dout_slave           ({reg_uart_rdata,
                                          reg_spi_rdata,
                                          {wb_xram_rdata},
                                          wb_xrom_rdata
                                         }),
 
              .wbd_adr_slave            ({reg_uart_addr[14:2],
                                          reg_spi_addr[14:2],
                                          wb_xram_adr[14:2],
                                          wb_xrom_adr[12:0]}
                                        ),
 
              .wbd_be_slave             ({reg_uart_be,
                                          reg_spi_be,
                                          wb_xram_be,
                                          wb_xrom_be}
                                        ),
 
              .wbd_we_slave             ({reg_uart_wr,
                                          reg_spi_wr,
                                          wb_xram_wr,
                                          wb_xrom_wr
                                          }),
 
              .wbd_ack_slave            ({reg_uart_ack,
                                          reg_spi_ack,
                                          wb_xram_ack,
                                          wb_xrom_ack
                                         }),
              .wbd_stb_slave            ({reg_uart_cs,
                                          reg_spi_cs,
                                          wb_xram_stb,
                                          wb_xrom_stb
                                         }),
 
              .wbd_cyc_slave            (),
              .wbd_err_slave            (),
              .wbd_rty_slave            ()
         );
 
 
 
//-------------------------------------
// UART core instantiation
//-------------------------------------
 
uart_core  u_uart_core
 
     (
          . line_reset_n                (gen_resetn            ),
          . line_clk_16x                (uart_clk_16x          ),
 
          . app_reset_n                 (gen_resetn            ),
          . app_clk                     (app_clk               ),
 
 
        // Reg Bus Interface Signal
          . reg_cs                      (reg_uart_cs           ),
          . reg_wr                      (reg_uart_wr           ),
          . reg_addr                    (reg_uart_addr[5:2]    ),
          . reg_wdata                   (reg_uart_wdata        ),
          . reg_be                      (reg_uart_be           ),
 
            // Outputs
          . reg_rdata                   (reg_uart_rdata        ),
          . reg_ack                     (reg_uart_ack          ),
 
 
 
       // Line Interface
          . si                          (si                    ),
          . so                          (so                    )
 
     );
 
 
//--------------------------------
// SPI core instantiation
//--------------------------------
 
 
spi_core u_spi_core (
 
          . clk                         (app_clk               ),
          . reset_n                     (gen_resetn            ),
 
        // Reg Bus Interface Signal
          . reg_cs                      (reg_spi_cs            ),
          . reg_wr                      (reg_spi_wr            ),
          . reg_addr                    (reg_spi_addr[5:2]     ),
          . reg_wdata                   (reg_spi_wdata         ),
          . reg_be                      (reg_spi_be            ),
 
            // Outputs
          . reg_rdata                   (reg_spi_rdata         ),
          . reg_ack                     (reg_spi_ack           ),
 
 
          . sck                         (spi_sck               ),
          . so                          (spi_so                ),
          . si                          (spi_si                ),
          . cs_n                        (spi_cs_n              )
 
           );
 
 
 
oc8051_top u_8051_core (
          . wb_rst_i                    (risc_reset            ),
          . wb_clk_i                    (app_clk               ),
 
//interface to instruction rom
          . wbi_adr_o                   (wbi_risc_adr          ),
          . wbi_dat_i                   (wbi_risc_rdata        ),
          . wbi_stb_o                   (wbi_risc_stb          ),
          . wbi_ack_i                   (wbi_risc_ack          ),
          . wbi_cyc_o                   (wbi_risc_cyc          ),
          . wbi_err_i                   (wbi_risc_err          ),
 
//interface to data ram
          . wbd_dat_i                   (wbd_risc_rdata        ),
          . wbd_dat_o                   (wbd_risc_wdata        ),
          . wbd_adr_o                   (wbd_risc_adr          ),
          . wbd_we_o                    (wbd_risc_we           ),
          . wbd_ack_i                   (wbd_risc_ack          ),
          . wbd_stb_o                   (wbd_risc_stb          ),
          . wbd_cyc_o                   (wbd_risc_cyc          ),
          . wbd_err_i                   (wbd_risc_err          ),
 
// interrupt interface
          . int0_i                      (                      ),
          . int1_i                      (                      ),
 
 
// port interface
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
          .p0_i                         ( p0                    ),
          .p0_o                         ( p0                    ),
        `endif
 
        `ifdef OC8051_PORT1
           .p1_i                        ( p1                    ),
           .p1_o                        ( p1                    ),
        `endif
 
        `ifdef OC8051_PORT2
           .p2_i                        ( p2                    ),
           .p2_o                        ( p2                    ),
        `endif
 
        `ifdef OC8051_PORT3
           .p3_i                        ( p3                    ),
           .p3_o                        ( p3                    ),
        `endif
  `endif
 
// serial interface
        `ifdef OC8051_UART
           .rxd_i                       (                      ),
           .txd_o                       (                      ),
        `endif
 
// counter interface
        `ifdef OC8051_TC01
           .t0_i                        (                      ),
           .t1_i                        (                      ),
        `endif
 
        `ifdef OC8051_TC2
           .t2_i                        (                      ),
           .t2ex_i                      (                      ),
        `endif
 
// BIST
`ifdef OC8051_BIST
            .scanb_rst                  (                      ),
            .scanb_clk                  (                      ),
            .scanb_si                   (                      ),
            .scanb_so                   (                      ),
            .scanb_en                   (                      ),
`endif
// external access (active low)
            .ea_in                      (ea_in                 )
         );
 
endmodule

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[/] [oms8051mini/] [trunk/] [rtl/] [core/] [digital_core.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OMS 8051 Dgital core Module ////`
4			`//// ////`
5			`//// This file is part of the OMS 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051mini/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// OMS 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//// Revision : Nov 26, 2016 ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`// v0 - Dinesh A, 26th Nov 2016`
21			`// 1. MAC related logic are remved`
22			`//////////////////////////////////////////////////////////////////////`
23			`//// ////`
24			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
25			`//// ////`
26			`//// This source file may be used and distributed without ////`
27			`//// restriction provided that this copyright statement is not ////`
28			`//// removed from the file and that any derivative work contains ////`
29			`//// the original copyright notice and the associated disclaimer. ////`
30			`//// ////`
31			`//// This source file is free software; you can redistribute it ////`
32			`//// and/or modify it under the terms of the GNU Lesser General ////`
33			`//// Public License as published by the Free Software Foundation; ////`
34			`//// either version 2.1 of the License, or (at your option) any ////`
35			`//// later version. ////`
36			`//// ////`
37			`//// This source is distributed in the hope that it will be ////`
38			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
39			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
40			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
41			`//// details. ////`
42			`//// ////`
43			`//// You should have received a copy of the GNU Lesser General ////`
44			`//// Public License along with this source; if not, download it ////`
45			`//// from http://www.opencores.org/lgpl.shtml ////`
46			`//// ////`
47			`//////////////////////////////////////////////////////////////////////`
48
49			`include "top_defines.v"
50			`module digital_core (`
51
52			`reset_n ,`
53			`scan_mode ,`
54			`scan_enable ,`
55			`fastsim_mode ,`
56			`mastermode ,`
57			`xtal_clk ,`
58			`clkout ,`
59			`reset_out_n ,`
60
61			`// Reg Bus Interface Signal`
62			`ext_reg_cs ,`
63			`ext_reg_tid ,`
64			`ext_reg_wr ,`
65			`ext_reg_addr ,`
66			`ext_reg_wdata ,`
67			`ext_reg_be ,`
68
69			`// Outputs`
70			`ext_reg_rdata ,`
71			`ext_reg_ack ,`
72
73
74
75			`// UART Line Interface`
76			`si ,`
77			`so ,`
78
79
80			`spi_sck ,`
81			`spi_so ,`
82			`spi_si ,`
83			`spi_cs_n ,`
84
85
86			`// External ROM interface`
87			`wb_xrom_adr ,`
88			`wb_xrom_ack ,`
89			`wb_xrom_err ,`
90			`wb_xrom_wr ,`
91			`wb_xrom_rdata ,`
92			`wb_xrom_wdata ,`
93
94			`wb_xrom_stb ,`
95			`wb_xrom_cyc ,`
96
97			`// External RAM interface`
98			`wb_xram_adr ,`
99			`wb_xram_ack ,`
100			`wb_xram_err ,`
101			`wb_xram_wr ,`
102			`wb_xram_be ,`
103			`wb_xram_rdata ,`
104			`wb_xram_wdata ,`
105
106			`wb_xram_stb ,`
107			`wb_xram_cyc,`
108
109			`ea_in`
110
111
112
113			`);`
114
115
116			`//----------------------------------------`
117			`// Global Clock Defination`
118			`//----------------------------------------`
119			`input reset_n ; // Active Low Reset`
120			`input scan_mode ; // scan mode`
121			`input scan_enable ; // scan enable`
122			`input fastsim_mode ; // Fast Sim Mode`
123			`input mastermode ; // 1 : Risc master mode`
124
125			`input xtal_clk ; // xtal clock 25Mhz`
126			`output clkout ; // clock output`
127			`output reset_out_n ; // clock output`
128
129			`//---------------------------------`
130			`// Reg Bus Interface Signal`
131			`//---------------------------------`
132			`input ext_reg_cs ;`
133			`input ext_reg_wr ;`
134			`input [3:0] ext_reg_tid ;`
135			`input [14:0] ext_reg_addr ;`
136			`input [31:0] ext_reg_wdata ;`
137			`input [3:0] ext_reg_be ;`
138
139			`// Outputs`
140			`output [31:0] ext_reg_rdata ;`
141			`output ext_reg_ack ;`
142
143
144
145			`//----------------------------------------`
146			`// UART Line Interface`
147			`//----------------------------------------`
148			`input si ; // serial in`
149			`output so ; // serial out`
150
151			`//----------------------------------------`
152			`// SPI Line Interface`
153			`//----------------------------------------`
154
155			`output spi_sck ; // clock`
156			`output spi_so ; // data out`
157			`input spi_si ; // data in`
158			`output [3:0] spi_cs_n ; // chip select`
159
160			`//----------------------------------------`
161			`// 8051 core ROM related signals`
162			`//---------------------------------------`
163			`output [15:0] wb_xrom_adr ; // instruction address`
164			`input wb_xrom_ack ; // instruction acknowlage`
165			`output wb_xrom_err ; // instruction error`
166			`output wb_xrom_wr ; // instruction error`
167			`input [31:0] wb_xrom_rdata ; // rom data input`
168			`output [31:0] wb_xrom_wdata ; // rom data input`
169
170			`output wb_xrom_stb ; // instruction strobe`
171			`output wb_xrom_cyc ; // instruction cycle`
172
173
174			`//----------------------------------------`
175			`// 8051 core RAM related signals`
176			`//---------------------------------------`
177			`output [15:0] wb_xram_adr ; // data-ram address`
178			`input wb_xram_ack ; // data-ram acknowlage`
179			`output wb_xram_err ; // data-ram error`
180			`output wb_xram_wr ; // data-ram error`
181			`output [3:0] wb_xram_be ; // Byte enable`
182			`input [31:0] wb_xram_rdata ; // ram data input`
183			`output [31:0] wb_xram_wdata ; // ram data input`
184
185			`output wb_xram_stb ; // data-ram strobe`
186			`output wb_xram_cyc ; // data-ram cycle`
187
188
189			`input ea_in ; // input for external access (ea signal)`
190			`// ea=0 program is in external rom`
191			`// ea=1 program is in internal rom`
192			`//---------------------------------------------`
193			`// 8051 Instruction ROM interface`
194			`//---------------------------------------------`
195			`wire [15:0] wbi_risc_adr;`
196			`wire [31:0] wbi_risc_rdata;`
197
198
199			`//-----------------------------`
200			`// wire Decleration`
201			`//-----------------------------`
202			`wire gen_resetn ;`
203
204
205			`//---------------------------------------------`
206			`// 8051 Instruction RAM interface`
207			`//---------------------------------------------`
208			`wire [15:0] wbd_risc_adr ;`
209			`wire [7:0] wbd_risc_rdata ;`
210			`wire [7:0] wbd_risc_wdata ;`
211
212
213			`wire [14:0] reg_uart_addr ;`
214			`wire [31:0] reg_uart_wdata ;`
215			`wire [3:0] reg_uart_be ;`
216			`wire [31:0] reg_uart_rdata ;`
217			`wire reg_uart_ack ;`
218
219			`wire [14:0] reg_spi_addr ;`
220			`wire [31:0] reg_spi_wdata ;`
221			`wire [3:0] reg_spi_be ;`
222			`wire [31:0] reg_spi_rdata ;`
223			`wire reg_spi_ack ;`
224
225			`wire [3:0] wb_xrom_be ;`
226			`wire [3:0] wb_xram_be ;`
227
228			`wire [7:0] p0 ;`
229			`wire [7:0] p1 ;`
230			`wire [7:0] p2 ;`
231			`wire [7:0] p3 ;`
232
233
234			`wire [31:0] reg_rdata = (reg_uart_ack) ? reg_uart_rdata :`
235			`(reg_spi_ack) ? reg_spi_rdata : 'h0;`
236
237			`wire reg_ack = reg_uart_ack \| reg_spi_ack;`
238
239
240			`assign reset_out_n = gen_resetn;`
241
242
243			`assign wb_xram_adr[15] = 0;`
244			`assign wb_xram_adr[1:0] = 2'b00;`
245			`assign wb_xrom_adr[15:13] = 0;`
246
247			`wire [9:0] cfg_tx_buf_qbase_addr;`
248			`wire [9:0] cfg_rx_buf_qbase_addr;`
249
250
251			`assign reg_uart_addr[1:0] = 2'b0;`
252			`assign reg_spi_addr[1:0] = 2'b0;`
253			`//-------------------------------------------`
254			`// clock-gen instantiation`
255			`//-------------------------------------------`
256			`clkgen u_clkgen (`
257			`. reset_n (reset_n ),`
258			`. fastsim_mode (fastsim_mode ),`
259			`. mastermode (mastermode ),`
260			`. xtal_clk (xtal_clk ),`
261			`. clkout (clkout ),`
262			`. gen_resetn (gen_resetn ),`
263			`. risc_reset (risc_reset ),`
264			`. app_clk (app_clk ),`
265			`. uart_ref_clk (uart_clk_16x )`
266
267			`);`
268
269
270
271			`wire [31:0] wb_master2_rdata;`
272
273			`wire [3:0] wb_master2_be = (wbd_risc_adr[1:0] == 2'b00) ? 4'b0001:`
274			`(wbd_risc_adr[1:0] == 2'b01) ? 4'b0010:`
275			`(wbd_risc_adr[1:0] == 2'b10) ? 4'b0100: 4'b1000;`
276
277			`assign wbd_risc_rdata = (wbd_risc_adr[1:0] == 2'b00) ? wb_master2_rdata[7:0]:`
278			`(wbd_risc_adr[1:0] == 2'b01) ? wb_master2_rdata[15:8]:`
279			`(wbd_risc_adr[1:0] == 2'b10) ? wb_master2_rdata[23:16]:`
280			`wb_master2_rdata[31:24];`
281
282			`//------------------------------`
283			`// 8051 Data Memory Map`
284			`// 0x0000 to 0x7FFFF - Data Memory`
285			`// 0x8000 to 0x8FFF - SPI`
286			`// 0x9000 to 0x9FFF - UART`
287			`// 0xA000 to 0xAFFF - MAC Core`
288			`//--------------------------------------------------------------`
289			`// Target ID Mapping`
290			`// 4'b0100 -- MAC core`
291			`// 4'b0011 -- UART`
292			`// 4'b0010 -- SPI core`
293			`// 4'b0001 -- External RAM`
294			`// 4'b0000 -- External ROM`
295			`//--------------------------------------------------------------`
296			`//`
297			`wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0001 :`
298			`(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0010 :`
299			`(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0011 : 4'b0100;`
300
301			`wb_crossbar #(.WB_MASTER(3),`
302			`.WB_SLAVE(4),`
303			`.D_WD(32),`
304			`.BE_WD(4),`
305			`.ADR_WD(13),`
306			`.TAR_WD(4))`
307			`u_wb_crossbar (`
308
309			`.rst_n (gen_resetn ),`
310			`.clk (app_clk ),`
311
312
313			`// Master Interface Signal`
314			`.wbd_taddr_master ({4'b0000,`
315			`wbd_tar_id,`
316			`ext_reg_tid }),`
317
318			`.wbd_din_master ({32'h0 ,`
319			`{wbd_risc_wdata[7:0],`
320			`wbd_risc_wdata[7:0],`
321			`wbd_risc_wdata[7:0],`
322			`wbd_risc_wdata[7:0]},`
323			`ext_reg_wdata }`
324			`),`
325
326			`.wbd_dout_master ({wbi_risc_rdata,`
327			`wb_master2_rdata,`
328			`ext_reg_rdata}),`
329
330			`.wbd_adr_master ({wbi_risc_adr[12:0],`
331			`wbd_risc_adr[14:2],`
332			`ext_reg_addr[14:2]}),`
333
334			`.wbd_be_master ({4'b1111,`
335			`wb_master2_be,`
336			`ext_reg_be }`
337			`),`
338
339			`.wbd_we_master ({1'b0,wbd_risc_we,ext_reg_wr } ),`
340
341			`.wbd_ack_master ({wbi_risc_ack,`
342			`wbd_risc_ack,`
343			`ext_reg_ack } ),`
344
345			`.wbd_stb_master ({wbi_risc_stb,`
346			`wbd_risc_stb,`
347			`ext_reg_cs} ),`
348
349			`.wbd_cyc_master ({wbi_risc_stb\|wbi_risc_ack,`
350			`wbd_risc_stb\|wbd_risc_ack,`
351			`ext_reg_cs\|ext_reg_ack }),`
352
353			`.wbd_err_master (),`
354			`.wbd_rty_master (),`
355
356			`// Slave Interface Signal`
357			`.wbd_din_slave ({reg_uart_wdata,`
358			`reg_spi_wdata,`
359			`wb_xram_wdata,`
360			`wb_xrom_wdata`
361			`}),`
362
363			`.wbd_dout_slave ({reg_uart_rdata,`
364			`reg_spi_rdata,`
365			`{wb_xram_rdata},`
366			`wb_xrom_rdata`
367			`}),`
368
369			`.wbd_adr_slave ({reg_uart_addr[14:2],`
370			`reg_spi_addr[14:2],`
371			`wb_xram_adr[14:2],`
372			`wb_xrom_adr[12:0]}`
373			`),`
374
375			`.wbd_be_slave ({reg_uart_be,`
376			`reg_spi_be,`
377			`wb_xram_be,`
378			`wb_xrom_be}`
379			`),`
380
381			`.wbd_we_slave ({reg_uart_wr,`
382			`reg_spi_wr,`
383			`wb_xram_wr,`
384			`wb_xrom_wr`
385			`}),`
386
387			`.wbd_ack_slave ({reg_uart_ack,`
388			`reg_spi_ack,`
389			`wb_xram_ack,`
390			`wb_xrom_ack`
391			`}),`
392			`.wbd_stb_slave ({reg_uart_cs,`
393			`reg_spi_cs,`
394			`wb_xram_stb,`
395			`wb_xrom_stb`
396			`}),`
397
398			`.wbd_cyc_slave (),`
399			`.wbd_err_slave (),`
400			`.wbd_rty_slave ()`
401			`);`
402
403
404
405			`//-------------------------------------`
406			`// UART core instantiation`
407			`//-------------------------------------`
408
409			`uart_core u_uart_core`
410
411			`(`
412			`. line_reset_n (gen_resetn ),`
413			`. line_clk_16x (uart_clk_16x ),`
414
415			`. app_reset_n (gen_resetn ),`
416			`. app_clk (app_clk ),`
417
418
419			`// Reg Bus Interface Signal`
420			`. reg_cs (reg_uart_cs ),`
421			`. reg_wr (reg_uart_wr ),`
422			`. reg_addr (reg_uart_addr[5:2] ),`
423			`. reg_wdata (reg_uart_wdata ),`
424			`. reg_be (reg_uart_be ),`
425
426			`// Outputs`
427			`. reg_rdata (reg_uart_rdata ),`
428			`. reg_ack (reg_uart_ack ),`
429
430
431
432			`// Line Interface`
433			`. si (si ),`
434			`. so (so )`
435
436			`);`
437
438
439			`//--------------------------------`
440			`// SPI core instantiation`
441			`//--------------------------------`
442
443
444			`spi_core u_spi_core (`
445
446			`. clk (app_clk ),`
447			`. reset_n (gen_resetn ),`
448
449			`// Reg Bus Interface Signal`
450			`. reg_cs (reg_spi_cs ),`
451			`. reg_wr (reg_spi_wr ),`
452			`. reg_addr (reg_spi_addr[5:2] ),`
453			`. reg_wdata (reg_spi_wdata ),`
454			`. reg_be (reg_spi_be ),`
455
456			`// Outputs`
457			`. reg_rdata (reg_spi_rdata ),`
458			`. reg_ack (reg_spi_ack ),`
459
460
461			`. sck (spi_sck ),`
462			`. so (spi_so ),`
463			`. si (spi_si ),`
464			`. cs_n (spi_cs_n )`
465
466			`);`
467
468
469
470			`oc8051_top u_8051_core (`
471			`. wb_rst_i (risc_reset ),`
472			`. wb_clk_i (app_clk ),`
473
474			`//interface to instruction rom`
475			`. wbi_adr_o (wbi_risc_adr ),`
476			`. wbi_dat_i (wbi_risc_rdata ),`
477			`. wbi_stb_o (wbi_risc_stb ),`
478			`. wbi_ack_i (wbi_risc_ack ),`
479			`. wbi_cyc_o (wbi_risc_cyc ),`
480			`. wbi_err_i (wbi_risc_err ),`
481
482			`//interface to data ram`
483			`. wbd_dat_i (wbd_risc_rdata ),`
484			`. wbd_dat_o (wbd_risc_wdata ),`
485			`. wbd_adr_o (wbd_risc_adr ),`
486			`. wbd_we_o (wbd_risc_we ),`
487			`. wbd_ack_i (wbd_risc_ack ),`
488			`. wbd_stb_o (wbd_risc_stb ),`
489			`. wbd_cyc_o (wbd_risc_cyc ),`
490			`. wbd_err_i (wbd_risc_err ),`
491
492			`// interrupt interface`
493			`. int0_i ( ),`
494			`. int1_i ( ),`
495
496
497			`// port interface`
498			`ifdef OC8051_PORTS
499			`ifdef OC8051_PORT0
500			`.p0_i ( p0 ),`
501			`.p0_o ( p0 ),`
502			`endif
503
504			`ifdef OC8051_PORT1
505			`.p1_i ( p1 ),`
506			`.p1_o ( p1 ),`
507			`endif
508
509			`ifdef OC8051_PORT2
510			`.p2_i ( p2 ),`
511			`.p2_o ( p2 ),`
512			`endif
513
514			`ifdef OC8051_PORT3
515			`.p3_i ( p3 ),`
516			`.p3_o ( p3 ),`
517			`endif
518			`endif
519
520			`// serial interface`
521			`ifdef OC8051_UART
522			`.rxd_i ( ),`
523			`.txd_o ( ),`
524			`endif
525
526			`// counter interface`
527			`ifdef OC8051_TC01
528			`.t0_i ( ),`
529			`.t1_i ( ),`
530			`endif
531
532			`ifdef OC8051_TC2
533			`.t2_i ( ),`
534			`.t2ex_i ( ),`
535			`endif
536
537			`// BIST`
538			`ifdef OC8051_BIST
539			`.scanb_rst ( ),`
540			`.scanb_clk ( ),`
541			`.scanb_si ( ),`
542			`.scanb_so ( ),`
543			`.scanb_en ( ),`
544			`endif
545			`// external access (active low)`
546			`.ea_in (ea_in )`
547			`);`
548
549			`endmodule`