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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OMS 8051 cores SPI Interface Module                         ////
////                                                              ////
////  This file is part of the OMS 8051 cores project             ////
////  http://www.opencores.org/cores/oms8051/                     ////
////                                                              ////
////  Description                                                 ////
////  OMS 8051 definitions.                                       ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision : Nov 26, 2016                                      //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
 
module spi_cfg (
 
             mclk,
             reset_n,
 
        // Reg Bus Interface Signal
             reg_cs,
             reg_wr,
             reg_addr,
             reg_wdata,
             reg_be,
 
            // Outputs
            reg_rdata,
            reg_ack,
 
 
           // configuration signal
           cfg_tgt_sel        ,
           cfg_op_req         , // SPI operation request
           cfg_op_type        , // SPI operation type
           cfg_transfer_size  , // SPI transfer size
           cfg_sck_period     , // sck clock period
           cfg_sck_cs_period  , // cs setup/hold period
           cfg_cs_byte        , // cs bit information
           cfg_datain         , // data for transfer
           cfg_dataout        , // data for received
           hware_op_done      // operation done
 
        );
 
 
 
input         mclk;
input         reset_n;
 
output [1:0]  cfg_tgt_sel        ;
 
output        cfg_op_req         ; // SPI operation request
output [1:0]  cfg_op_type        ; // SPI operation type
output [1:0]  cfg_transfer_size  ; // SPI transfer size
output [5:0]  cfg_sck_period     ; // sck clock period
output [4:0]  cfg_sck_cs_period  ; // cs setup/hold period
output [7:0]  cfg_cs_byte        ; // cs bit information
output [31:0] cfg_datain         ; // data for transfer
input  [31:0] cfg_dataout        ; // data for received
input         hware_op_done      ; // operation done
 
//---------------------------------
// Reg Bus Interface Signal
//---------------------------------
input             reg_cs         ;
input             reg_wr         ;
input [3:0]       reg_addr       ;
input [7:0]       reg_wdata      ;
input             reg_be         ;
 
// Outputs
output [7:0]      reg_rdata      ;
output            reg_ack        ;
 
 
 
//-----------------------------------------------------------------------
// Internal Wire Declarations
//-----------------------------------------------------------------------
 
wire           sw_rd_en;
wire           sw_wr_en;
wire  [3:0]    sw_addr ; // addressing 16 registers
wire           wr_be   ;
 
reg   [7:0]   reg_rdata;
reg           reg_ack  ;
 
wire [31:0]   spi_ctrl; // Software-Reg_12
wire [7:0]    reg_12; // Software-Reg_12
wire [7:0]    reg_13; // Software-Reg_13
wire [7:0]    reg_14; // Software-Reg_14
wire [7:0]    reg_15; // Software-Reg_15
reg  [7:0]    reg_out;
 
//-----------------------------------------------------------------------
// Main code starts here
//-----------------------------------------------------------------------
 
//-----------------------------------------------------------------------
// Internal Logic Starts here
//-----------------------------------------------------------------------
    assign sw_addr       = reg_addr [3:0];
    assign sw_rd_en      = reg_cs & !reg_wr;
    assign sw_wr_en      = reg_cs & reg_wr;
    assign wr_be         = reg_be;
 
 
//-----------------------------------------------------------------------
// Read path mux
//-----------------------------------------------------------------------
 
always @ (posedge mclk or negedge reset_n)
begin : preg_out_Seq
   if (reset_n == 1'b0)
   begin
      reg_rdata [7:0]  <= 8'h00;
      reg_ack           <= 1'b0;
   end
   else if (sw_rd_en && !reg_ack)
   begin
      reg_rdata [7:0]  <= reg_out [7:0];
      reg_ack           <= 1'b1;
   end
   else if (sw_wr_en && !reg_ack)
      reg_ack           <= 1'b1;
   else
   begin
      reg_ack        <= 1'b0;
   end
end
 
 
//-----------------------------------------------------------------------
// register read enable and write enable decoding logic
//-----------------------------------------------------------------------
wire   sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);
wire   sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0);
wire   sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);
wire   sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1);
wire   sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);
wire   sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2);
wire   sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);
wire   sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3);
wire   sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4);
wire   sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4);
wire   sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5);
wire   sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5);
wire   sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6);
wire   sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6);
wire   sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7);
wire   sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7);
wire   sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8);
wire   sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8);
wire   sw_wr_en_9 = sw_wr_en & (sw_addr == 4'h9);
wire   sw_rd_en_9 = sw_rd_en & (sw_addr == 4'h9);
wire   sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA);
wire   sw_rd_en_10 = sw_rd_en & (sw_addr == 4'hA);
wire   sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB);
wire   sw_rd_en_11 = sw_rd_en & (sw_addr == 4'hB);
wire   sw_wr_en_12 = sw_wr_en & (sw_addr == 4'hC);
wire   sw_rd_en_12 = sw_rd_en & (sw_addr == 4'hC);
wire   sw_wr_en_13 = sw_wr_en & (sw_addr == 4'hD);
wire   sw_rd_en_13 = sw_rd_en & (sw_addr == 4'hD);
wire   sw_wr_en_14 = sw_wr_en & (sw_addr == 4'hE);
wire   sw_rd_en_14 = sw_rd_en & (sw_addr == 4'hE);
wire   sw_wr_en_15 = sw_wr_en & (sw_addr == 4'hF);
wire   sw_rd_en_15 = sw_rd_en & (sw_addr == 4'hF);
 
 
always @( *)
begin : preg_sel_Com
 
  reg_out [7:0] = 8'd0;
 
  case (sw_addr [3:0])
    4'b0000 : reg_out [7:0] = spi_ctrl [7:0];
    4'b0001 : reg_out [7:0] = spi_ctrl [15:8];
    4'b0010 : reg_out [7:0] = spi_ctrl [23:16];
    4'b0011 : reg_out [7:0] = spi_ctrl [31:24];
    4'b0100 : reg_out [7:0] = cfg_datain [7:0];
    4'b0101 : reg_out [7:0] = cfg_datain [15:8];
    4'b0110 : reg_out [7:0] = cfg_datain [23:16];
    4'b0111 : reg_out [7:0] = cfg_datain [31:24];
    4'b1000 : reg_out [7:0] = cfg_dataout [7:0];
    4'b1001 : reg_out [7:0] = cfg_dataout [15:8];
    4'b1010 : reg_out [7:0] = cfg_dataout [23:16];
    4'b1011 : reg_out [7:0] = cfg_dataout [31:24];
    4'b1100 : reg_out [7:0] = reg_12 [7:0];
    4'b1101 : reg_out [7:0] = reg_13 [7:0];
    4'b1110 : reg_out [7:0] = reg_14 [7:0];
    4'b1111 : reg_out [7:0] = reg_15 [7:0];
  endcase
end
 
 
 
//-----------------------------------------------------------------------
// Individual register assignments
//-----------------------------------------------------------------------
// Logic for Register 0 : SPI Control Register
//-----------------------------------------------------------------------
wire         cfg_op_req         = spi_ctrl[31];    // cpu request
wire [1:0]   cfg_tgt_sel        = spi_ctrl[24:23]; // target chip select
wire [1:0]   cfg_op_type        = spi_ctrl[22:21]; // SPI operation type
wire [1:0]   cfg_transfer_size  = spi_ctrl[20:19]; // SPI transfer size
wire [5:0]   cfg_sck_period     = spi_ctrl[18:13]; // sck clock period
wire [4:0]   cfg_sck_cs_period  = spi_ctrl[12:8];  // cs setup/hold period
wire [7:0]   cfg_cs_byte        = spi_ctrl[7:0];   // cs bit information
 
 
generic_register #(8,0  ) u_spi_ctrl_be0 (
              .we            ({8{sw_wr_en_0 & wr_be   }}  ),
              .data_in       (reg_wdata[7:0]    ),
              .reset_n       (reset_n           ),
              .clk           (mclk              ),
 
              //List of Outs
              .data_out      (spi_ctrl[7:0]     )
          );
 
generic_register #(8,0  ) u_spi_ctrl_be1 (
              .we            ({8{sw_wr_en_1 & wr_be   }}   ),
              .data_in       (reg_wdata[7:0]    ),
              .reset_n       (reset_n           ),
              .clk           (mclk              ),
 
              //List of Outs
              .data_out      (spi_ctrl[15:8]    )
          );
 
generic_register #(8,0  ) u_spi_ctrl_be2 (
              .we            ({8{sw_wr_en_2 & wr_be}}  ),
              .data_in       (reg_wdata[7:0]    ),
              .reset_n       (reset_n           ),
              .clk           (mclk              ),
 
              //List of Outs
              .data_out      (spi_ctrl[23:16]   )
          );
 
assign spi_ctrl[30:24] = 7'h0;
 
req_register #(0  ) u_spi_ctrl_req (
              .cpu_we       ({sw_wr_en_3 & wr_be}),
              .cpu_req      (reg_wdata[7]       ),
              .hware_ack    (hware_op_done      ),
              .reset_n       (reset_n           ),
              .clk           (mclk              ),
 
              //List of Outs
              .data_out      (spi_ctrl[31]      )
          );
 
 
 
 
//-----------------------------------------------------------------------
// Logic for Register 1 : SPI Data In Register
//-----------------------------------------------------------------------
 
generic_register #(8,0  ) u_spi_din_be0 (
              .we            ({8{sw_wr_en_4 & wr_be   }}  ),
              .data_in       (reg_wdata[7:0]    ),
              .reset_n       (reset_n           ),
              .clk           (mclk              ),
 
              //List of Outs
              .data_out      (cfg_datain[7:0]   )
          );
 
generic_register #(8,0  ) u_spi_din_be1 (
              .we            ({8{sw_wr_en_5 & wr_be   }}  ),
              .data_in       (reg_wdata[7:0]    ),
              .reset_n       (reset_n           ),
              .clk           (mclk              ),
 
              //List of Outs
              .data_out      (cfg_datain[15:8]  )
          );
 
generic_register #(8,0  ) u_spi_din_be2 (
              .we            ({8{sw_wr_en_6 & wr_be   }}  ),
              .data_in       (reg_wdata[7:0]    ),
              .reset_n       (reset_n           ),
              .clk           (mclk              ),
 
              //List of Outs
              .data_out      (cfg_datain[23:16] )
          );
 
 
generic_register #(8,0  ) u_spi_din_be3 (
              .we            ({8{sw_wr_en_7 & wr_be   }}  ),
              .data_in       (reg_wdata[7:0]    ),
              .reset_n       (reset_n           ),
              .clk           (mclk              ),
 
              //List of Outs
              .data_out      (cfg_datain[31:24] )
          );
 
 
//-----------------------------------------------------------------------
// Logic for Register  : SPI Data output Register
//-----------------------------------------------------------------------
assign  reg_2 = cfg_dataout;
 
 
 
endmodule

Line No.	Rev	Author	Line
1	2	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OMS 8051 cores SPI Interface Module ////`
4			`//// ////`
5			`//// This file is part of the OMS 8051 cores project ////`
6			`//// http://www.opencores.org/cores/oms8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// OMS 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//// Revision : Nov 26, 2016 ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45
46
47
48			`module spi_cfg (`
49
50			`mclk,`
51			`reset_n,`
52
53			`// Reg Bus Interface Signal`
54			`reg_cs,`
55			`reg_wr,`
56			`reg_addr,`
57			`reg_wdata,`
58			`reg_be,`
59
60			`// Outputs`
61			`reg_rdata,`
62			`reg_ack,`
63
64
65			`// configuration signal`
66			`cfg_tgt_sel ,`
67			`cfg_op_req , // SPI operation request`
68			`cfg_op_type , // SPI operation type`
69			`cfg_transfer_size , // SPI transfer size`
70			`cfg_sck_period , // sck clock period`
71			`cfg_sck_cs_period , // cs setup/hold period`
72			`cfg_cs_byte , // cs bit information`
73			`cfg_datain , // data for transfer`
74			`cfg_dataout , // data for received`
75			`hware_op_done // operation done`
76
77			`);`
78
79
80
81			`input mclk;`
82			`input reset_n;`
83
84			`output [1:0] cfg_tgt_sel ;`
85
86			`output cfg_op_req ; // SPI operation request`
87			`output [1:0] cfg_op_type ; // SPI operation type`
88			`output [1:0] cfg_transfer_size ; // SPI transfer size`
89			`output [5:0] cfg_sck_period ; // sck clock period`
90			`output [4:0] cfg_sck_cs_period ; // cs setup/hold period`
91			`output [7:0] cfg_cs_byte ; // cs bit information`
92			`output [31:0] cfg_datain ; // data for transfer`
93			`input [31:0] cfg_dataout ; // data for received`
94			`input hware_op_done ; // operation done`
95
96			`//---------------------------------`
97			`// Reg Bus Interface Signal`
98			`//---------------------------------`
99			`input reg_cs ;`
100			`input reg_wr ;`
101			`input [3:0] reg_addr ;`
102	11	dinesha	`input [7:0] reg_wdata ;`
103			`input reg_be ;`
104	2	dinesha
105			`// Outputs`
106	11	dinesha	`output [7:0] reg_rdata ;`
107	2	dinesha	`output reg_ack ;`
108
109
110
111			`//-----------------------------------------------------------------------`
112			`// Internal Wire Declarations`
113			`//-----------------------------------------------------------------------`
114
115			`wire sw_rd_en;`
116			`wire sw_wr_en;`
117			`wire [3:0] sw_addr ; // addressing 16 registers`
118	11	dinesha	`wire wr_be ;`
119	2	dinesha
120	11	dinesha	`reg [7:0] reg_rdata;`
121			`reg reg_ack ;`
122	2	dinesha
123	11	dinesha	`wire [31:0] spi_ctrl; // Software-Reg_12`
124			`wire [7:0] reg_12; // Software-Reg_12`
125			`wire [7:0] reg_13; // Software-Reg_13`
126			`wire [7:0] reg_14; // Software-Reg_14`
127			`wire [7:0] reg_15; // Software-Reg_15`
128			`reg [7:0] reg_out;`
129	2	dinesha
130			`//-----------------------------------------------------------------------`
131			`// Main code starts here`
132			`//-----------------------------------------------------------------------`
133
134			`//-----------------------------------------------------------------------`
135			`// Internal Logic Starts here`
136			`//-----------------------------------------------------------------------`
137			`assign sw_addr = reg_addr [3:0];`
138			`assign sw_rd_en = reg_cs & !reg_wr;`
139			`assign sw_wr_en = reg_cs & reg_wr;`
140			`assign wr_be = reg_be;`
141
142
143			`//-----------------------------------------------------------------------`
144			`// Read path mux`
145			`//-----------------------------------------------------------------------`
146
147			`always @ (posedge mclk or negedge reset_n)`
148			`begin : preg_out_Seq`
149			`if (reset_n == 1'b0)`
150			`begin`
151	11	dinesha	`reg_rdata [7:0] <= 8'h00;`
152	2	dinesha	`reg_ack <= 1'b0;`
153			`end`
154			`else if (sw_rd_en && !reg_ack)`
155			`begin`
156	11	dinesha	`reg_rdata [7:0] <= reg_out [7:0];`
157	2	dinesha	`reg_ack <= 1'b1;`
158			`end`
159			`else if (sw_wr_en && !reg_ack)`
160			`reg_ack <= 1'b1;`
161			`else`
162			`begin`
163			`reg_ack <= 1'b0;`
164			`end`
165			`end`
166
167
168			`//-----------------------------------------------------------------------`
169			`// register read enable and write enable decoding logic`
170			`//-----------------------------------------------------------------------`
171			`wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);`
172			`wire sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0);`
173			`wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);`
174			`wire sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1);`
175			`wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);`
176			`wire sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2);`
177			`wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);`
178			`wire sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3);`
179			`wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4);`
180			`wire sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4);`
181			`wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5);`
182			`wire sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5);`
183			`wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6);`
184			`wire sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6);`
185			`wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7);`
186			`wire sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7);`
187			`wire sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8);`
188			`wire sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8);`
189			`wire sw_wr_en_9 = sw_wr_en & (sw_addr == 4'h9);`
190			`wire sw_rd_en_9 = sw_rd_en & (sw_addr == 4'h9);`
191			`wire sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA);`
192			`wire sw_rd_en_10 = sw_rd_en & (sw_addr == 4'hA);`
193			`wire sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB);`
194			`wire sw_rd_en_11 = sw_rd_en & (sw_addr == 4'hB);`
195			`wire sw_wr_en_12 = sw_wr_en & (sw_addr == 4'hC);`
196			`wire sw_rd_en_12 = sw_rd_en & (sw_addr == 4'hC);`
197			`wire sw_wr_en_13 = sw_wr_en & (sw_addr == 4'hD);`
198			`wire sw_rd_en_13 = sw_rd_en & (sw_addr == 4'hD);`
199			`wire sw_wr_en_14 = sw_wr_en & (sw_addr == 4'hE);`
200			`wire sw_rd_en_14 = sw_rd_en & (sw_addr == 4'hE);`
201			`wire sw_wr_en_15 = sw_wr_en & (sw_addr == 4'hF);`
202			`wire sw_rd_en_15 = sw_rd_en & (sw_addr == 4'hF);`
203
204
205			`always @( *)`
206			`begin : preg_sel_Com`
207
208	11	dinesha	`reg_out [7:0] = 8'd0;`
209	2	dinesha
210			`case (sw_addr [3:0])`
211	11	dinesha	`4'b0000 : reg_out [7:0] = spi_ctrl [7:0];`
212			`4'b0001 : reg_out [7:0] = spi_ctrl [15:8];`
213			`4'b0010 : reg_out [7:0] = spi_ctrl [23:16];`
214			`4'b0011 : reg_out [7:0] = spi_ctrl [31:24];`
215			`4'b0100 : reg_out [7:0] = cfg_datain [7:0];`
216			`4'b0101 : reg_out [7:0] = cfg_datain [15:8];`
217			`4'b0110 : reg_out [7:0] = cfg_datain [23:16];`
218			`4'b0111 : reg_out [7:0] = cfg_datain [31:24];`
219			`4'b1000 : reg_out [7:0] = cfg_dataout [7:0];`
220			`4'b1001 : reg_out [7:0] = cfg_dataout [15:8];`
221			`4'b1010 : reg_out [7:0] = cfg_dataout [23:16];`
222			`4'b1011 : reg_out [7:0] = cfg_dataout [31:24];`
223			`4'b1100 : reg_out [7:0] = reg_12 [7:0];`
224			`4'b1101 : reg_out [7:0] = reg_13 [7:0];`
225			`4'b1110 : reg_out [7:0] = reg_14 [7:0];`
226			`4'b1111 : reg_out [7:0] = reg_15 [7:0];`
227	2	dinesha	`endcase`
228			`end`
229
230
231
232			`//-----------------------------------------------------------------------`
233			`// Individual register assignments`
234			`//-----------------------------------------------------------------------`
235			`// Logic for Register 0 : SPI Control Register`
236			`//-----------------------------------------------------------------------`
237	11	dinesha	`wire cfg_op_req = spi_ctrl[31]; // cpu request`
238			`wire [1:0] cfg_tgt_sel = spi_ctrl[24:23]; // target chip select`
239			`wire [1:0] cfg_op_type = spi_ctrl[22:21]; // SPI operation type`
240			`wire [1:0] cfg_transfer_size = spi_ctrl[20:19]; // SPI transfer size`
241			`wire [5:0] cfg_sck_period = spi_ctrl[18:13]; // sck clock period`
242			`wire [4:0] cfg_sck_cs_period = spi_ctrl[12:8]; // cs setup/hold period`
243			`wire [7:0] cfg_cs_byte = spi_ctrl[7:0]; // cs bit information`
244	2	dinesha
245	11	dinesha
246	2	dinesha	`generic_register #(8,0 ) u_spi_ctrl_be0 (`
247	11	dinesha	`.we ({8{sw_wr_en_0 & wr_be }} ),`
248	2	dinesha	`.data_in (reg_wdata[7:0] ),`
249			`.reset_n (reset_n ),`
250			`.clk (mclk ),`
251
252			`//List of Outs`
253	11	dinesha	`.data_out (spi_ctrl[7:0] )`
254	2	dinesha	`);`
255
256			`generic_register #(8,0 ) u_spi_ctrl_be1 (`
257	11	dinesha	`.we ({8{sw_wr_en_1 & wr_be }} ),`
258			`.data_in (reg_wdata[7:0] ),`
259	2	dinesha	`.reset_n (reset_n ),`
260			`.clk (mclk ),`
261
262			`//List of Outs`
263	11	dinesha	`.data_out (spi_ctrl[15:8] )`
264	2	dinesha	`);`
265
266			`generic_register #(8,0 ) u_spi_ctrl_be2 (`
267	11	dinesha	`.we ({8{sw_wr_en_2 & wr_be}} ),`
268			`.data_in (reg_wdata[7:0] ),`
269	2	dinesha	`.reset_n (reset_n ),`
270			`.clk (mclk ),`
271
272			`//List of Outs`
273	11	dinesha	`.data_out (spi_ctrl[23:16] )`
274	2	dinesha	`);`
275
276	11	dinesha	`assign spi_ctrl[30:24] = 7'h0;`
277	2	dinesha
278			`req_register #(0 ) u_spi_ctrl_req (`
279	11	dinesha	`.cpu_we ({sw_wr_en_3 & wr_be}),`
280			`.cpu_req (reg_wdata[7] ),`
281	2	dinesha	`.hware_ack (hware_op_done ),`
282			`.reset_n (reset_n ),`
283			`.clk (mclk ),`
284
285			`//List of Outs`
286	11	dinesha	`.data_out (spi_ctrl[31] )`
287	2	dinesha	`);`
288
289
290
291
292			`//-----------------------------------------------------------------------`
293			`// Logic for Register 1 : SPI Data In Register`
294			`//-----------------------------------------------------------------------`
295
296			`generic_register #(8,0 ) u_spi_din_be0 (`
297	11	dinesha	`.we ({8{sw_wr_en_4 & wr_be }} ),`
298	2	dinesha	`.data_in (reg_wdata[7:0] ),`
299			`.reset_n (reset_n ),`
300			`.clk (mclk ),`
301
302			`//List of Outs`
303	11	dinesha	`.data_out (cfg_datain[7:0] )`
304	2	dinesha	`);`
305
306			`generic_register #(8,0 ) u_spi_din_be1 (`
307	11	dinesha	`.we ({8{sw_wr_en_5 & wr_be }} ),`
308			`.data_in (reg_wdata[7:0] ),`
309	2	dinesha	`.reset_n (reset_n ),`
310			`.clk (mclk ),`
311
312			`//List of Outs`
313	11	dinesha	`.data_out (cfg_datain[15:8] )`
314	2	dinesha	`);`
315
316			`generic_register #(8,0 ) u_spi_din_be2 (`
317	11	dinesha	`.we ({8{sw_wr_en_6 & wr_be }} ),`
318			`.data_in (reg_wdata[7:0] ),`
319	2	dinesha	`.reset_n (reset_n ),`
320			`.clk (mclk ),`
321
322			`//List of Outs`
323	11	dinesha	`.data_out (cfg_datain[23:16] )`
324	2	dinesha	`);`
325
326
327			`generic_register #(8,0 ) u_spi_din_be3 (`
328	11	dinesha	`.we ({8{sw_wr_en_7 & wr_be }} ),`
329			`.data_in (reg_wdata[7:0] ),`
330	2	dinesha	`.reset_n (reset_n ),`
331			`.clk (mclk ),`
332
333			`//List of Outs`
334	11	dinesha	`.data_out (cfg_datain[31:24] )`
335	2	dinesha	`);`
336
337
338			`//-----------------------------------------------------------------------`
339	11	dinesha	`// Logic for Register : SPI Data output Register`
340	2	dinesha	`//-----------------------------------------------------------------------`
341			`assign reg_2 = cfg_dataout;`
342
343
344
345			`endmodule`

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[/] [oms8051mini/] [trunk/] [rtl/] [spi/] [spi_cfg.v] - Blame information for rev 11