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URL https://opencores.org/ocsvn/oms8051mini/oms8051mini/trunk

Subversion Repositories oms8051mini

[/] [oms8051mini/] [trunk/] [verif/] [run/] [filelist_rtl.f] - Blame information for rev 10

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Line No. Rev Author Line
1 2 dinesha 
+incdir+../defs \
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+incdir+../../rtl/defs \
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+incdir+../../rtl/8051 \
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+incdir+../lib \
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-v ../../rtl/lib/registers.v \
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-v ../../rtl/lib/stat_counter.v \
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-v ../../rtl/lib/toggle_sync.v \
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-v ../../rtl/lib/double_sync_low.v \
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-v ../../rtl/lib/async_fifo.v  \
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../../rtl/core/digital_core.v \
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../../rtl/lib/async_fifo.v \
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../../rtl/lib/g_dpath_ctrl.v  \
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../../rtl/spi/spi_core.v  \
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../../rtl/spi/spi_ctl.v  \
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../../rtl/spi/spi_if.v \
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../../rtl/spi/spi_cfg.v \
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../../rtl/uart/uart_rxfsm.v \
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../../rtl/uart/uart_txfsm.v \
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../../rtl/uart/uart_core.v  \
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../../rtl/uart/uart_cfg.v  \
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../../rtl/clkgen/clkgen.v  \
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../../rtl/lib/clk_ctl.v  \
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../../rtl/lib/wb_crossbar.v  \
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../../rtl/lib/wb_rd_mem2mem.v \
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../../rtl/lib/wb_wr_mem2mem.v \
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../../rtl/8051/oc8051_top.v \
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../../rtl/8051/oc8051_rom.v \
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../../rtl/8051/oc8051_alu_src_sel.v \
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../../rtl/8051/oc8051_alu.v \
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../../rtl/8051/oc8051_decoder.v \
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../../rtl/8051/oc8051_divide.v \
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../../rtl/8051/oc8051_multiply.v \
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../../rtl/8051/oc8051_memory_interface.v \
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../../rtl/8051/oc8051_ram_top.v \
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../../rtl/8051/oc8051_acc.v \
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../../rtl/8051/oc8051_comp.v \
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../../rtl/8051/oc8051_sp.v \
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../../rtl/8051/oc8051_dptr.v \
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../../rtl/8051/oc8051_cy_select.v \
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../../rtl/8051/oc8051_psw.v \
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../../rtl/8051/oc8051_indi_addr.v \
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../../rtl/8051/oc8051_ports.v \
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../../rtl/8051/oc8051_b_register.v \
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../../rtl/8051/oc8051_uart.v \
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../../rtl/8051/oc8051_int.v \
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../../rtl/8051/oc8051_tc.v \
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../../rtl/8051/oc8051_tc2.v \
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../../rtl/8051/oc8051_sfr.v \
49 10 dinesha 
../../rtl/8051/oc8051_ram_256x8_two_bist.v \
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../../rtl/model/oc8051_xram.v \
51 
../../rtl/model/oc8051_xrom.v

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