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smjoshua |
/*
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Josh Smith
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File: oops_defs.v
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Description: File for the global defines
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*/
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`timescale 1ns/10ps
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`define SD #1
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// Common field widths
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`define ADDR_SZ 32 // Address width/size
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`define INSTR_SZ 32 // Instruction width/size
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`define DATA_SZ 32 // Data width/size
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`define IMM_SZ 16 // Immediate width/size
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// ROB defines
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`define ROB_ENTRIES 8 // Size of ReorderBuffer
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`define ROB_PTR_SZ 4 // Size of ROB ptr (1 extra bit for full/empty detection)
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// Register file and map table/free list defines
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`define ARCH_REGS 34 // GPR 0-31, HI/LO
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`define REG_IDX_SZ 6 // Architected register index size (6 bits to include HI/LO)
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`define TAG_SZ 6 // Register tag size
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`define TAGS (`ARCH_REGS+`ROB_ENTRIES) // 32 GPRs, HI/LO, and ROB size
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`define FL_SZ (`TAGS)
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`define FL_PTR_SZ `TAG_SZ
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`define LO_REG `TAG_SZ'd33
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`define ZERO_REG `TAG_SZ'd0
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`define CHKPT_NUM 4 // Number of RAT checkpoints
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`define CHKPT_PTR_SZ 2
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// CDB defines
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`define NUM_CDB 4 // 2 ALU, 1 LD/ST, 1 MULT/DIV
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`define CDB_SZ (1+`TAG_SZ+`REG_IDX_SZ+`ROB_PTR_SZ) // 1 valid bit, 1 tag, 1 architectural reg index, 1 ROB index
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`define CDB_VLD `TAG_SZ+`REG_IDX_SZ+`ROB_PTR_SZ // Valid field of CDB
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`define CDB_ROB_IDX `TAG_SZ+`REG_IDX_SZ+`ROB_PTR_SZ-1:`TAG_SZ+`REG_IDX_SZ
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`define CDB_TAG `REG_IDX_SZ+`TAG_SZ-1:`REG_IDX_SZ // Tag field of CDB
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`define CDB_REG_IDX `REG_IDX_SZ-1:0 // Arch. reg index field of CDB
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`define CDB_BUS_SZ (`NUM_CDB*`CDB_SZ) // `NUM_CDB valid bits and tags
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`define CDB_DATA_SZ (`NUM_CDB*`DATA_SZ)
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// Branch prediction defines
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`define BP_IDX_SZ 4 // Size of Index into branch predictor
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`define BP_ENTRIES (1 << `BP_IDX_SZ) // Number of branch predictor entries
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// System Bus defines
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`define SYS_BUS_SZ 64
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`define SYS_BUS_BE_SZ 8
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// Instruction Cache defines
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`define IC_LINE_SZ (2*`INSTR_SZ) // Size of instruction cache line
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`define IC_BO_SZ 3 // Block-offset size
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`define IC_SI_SZ 8 // Set index size
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`define IC_TAG_SZ (`ADDR_SZ-`IC_SI_SZ-`IC_BO_SZ) // Tag size
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`define IC_TAG `ADDR_SZ-1 -: `IC_TAG_SZ // Tag field of PC
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`define IC_SI `IC_SI_SZ+`IC_BO_SZ-1:`IC_BO_SZ // Set index field of PC
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`define IC_NUM_LINES (1<<`IC_SI_SZ) // Number of instruction cache lines
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`define IC_TAGRAM_SZ (1+1+`IC_TAG_SZ) // +2 bits for valid/dirty (dirty not used)
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`define IC_TAGRAM_VLD `IC_TAG_SZ+1 // Valid field
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`define IC_TAGRAM_DRT `IC_TAG_SZ // Dirty field
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`define IC_TAGRAM_TAG `IC_TAG_SZ-1:0 // tag field
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// Data Cache defines
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`define DC_LINE_SZ (2*`DATA_SZ) // Size of data cache line
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`define DC_BO_SZ 2 // Block-offset size
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`define DC_SI_SZ 8 // Set index size
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`define DC_TAG_SZ (`ADDR_SZ-`DC_SI_SZ-`DC_BO_SZ) // Tag size
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`define DC_TAG `ADDR_SZ-1 -: `DC_TAG_SZ // Tag field of PC
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`define DC_SI `ADDR_SZ-1-`DC_TAG_SZ -: `DC_SI_SZ // Set index field of PC
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`define DC_TAGRAM_SZ (1+1+`DC_TAG_SZ) // +2 bits for valid/dirty
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`define DC_NUM_LINES (1<<`DC_SI_SZ) // Number of data cache lines
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`define DC_TAGRAM_VLD `DC_TAG_SZ+1 // Valid field
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`define DC_TAGRAM_DRT `DC_TAG_SZ // Dirty field
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`define DC_TAGRAM_TAG `DC_TAG_SZ-1:0 // tag field
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`define RESET_ADDR 32'h0 // FPC reset address
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// Fields of branch prediction bus
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`define BP_SZ 34
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`define BP_TRGT 33:2
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`define BP_TKN 1
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`define BP_VLD 0
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// Fields of Decode bus
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/*
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`define DEC_BUS_SZ 84
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`define DEC_IMM_DATA 83:68 // Immediate data for ALU and MEM
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`define DEC_TYPE_INFO 67:65 // Instruction type info group
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`define DEC_TYPE_ALU 67 // ALU/Branch instruction type
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`define DEC_TYPE_MULT_DIV 66 // MULT/DIV instruction type
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`define DEC_TYPE_MEM 65 // Load/Store instruction type
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`define DEC_REG_INFO 64:44 // Register info group
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`define DEC_REG_D_WR 64 // Writes to dest register
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`define DEC_REG_T_NEED 63 // Need register T operand
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`define DEC_REG_S_NEED 62 // Need register S operand
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`define DEC_REG_D_INDX 61:56 // Destination register index
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`define DEC_REG_T_INDX 55:50 // Operand register T index
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`define DEC_REG_S_INDX 49:44 // Operand register S index
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`define DEC_MULTDIV_SZ 8 // MULT/DIV info group
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`define DEC_MULTDIV_INFO 43:36 // MULT/DIV info group
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`define DEC_MTLO 43 // Move to LO
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`define DEC_MTHI 42 // Move to HI
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`define DEC_MFLO 41 // Move from LO
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`define DEC_MFHI 40 // Move from HI
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`define DEC_MD_SIGNED 39 // Mult/Div signed
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`define DEC_DIV 38 // Divide
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`define DEC_MULT 37 // Multiply
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`define DEC_WR_HILO 36 // Write to HI and LO registers
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`define DEC_MEM_SZ 6
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`define DEC_MEM_INFO 35:30 // Load/Store info group
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`define DEC_MEM_W 35 // Word load/store
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`define DEC_MEM_HW 34 // Halfword load/store
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`define DEC_MEM_B 33 // Byte load/store
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`define DEC_MEM_ST 32 // Memory store
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`define DEC_MEM_SIGNED 31 // Load Signed
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`define DEC_MEM_LD 30 // Memory load
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`define DEC_CP_SZ 7
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`define DEC_CP_INFO 29:23 // Coprocessor info group
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`define DEC_CP_SEL 29:27 // Coprocessor Sel index
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`define DEC_CP_NUM 26:25 // Coprocessor number
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`define DEC_CP_TO 24 // Move To coprocessor (from if 0)
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`define DEC_CP_OP 23 // Coprocessor Operation
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`define DEC_BR_SZ 10
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`define DEC_BR_INFO 22:13 // Branch info group
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`define DEC_BR_SYS 22 // SYSCALL
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`define DEC_BR_BRK 21 // BREAK
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`define DEC_BR_LINK 20 // Branch/Jump and link
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`define DEC_BR_JR 19 // JR/JALR
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`define DEC_BR_J 18 // J/JAL
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`define DEC_BR_NEG 17 // Negate condition (to get the rest of the conditions)
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`define DEC_BR_BGT 16 // BGTZ condition
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`define DEC_BR_BGE 15 // BGEZ condition
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`define DEC_BR_BEQ 14 // BEQ condition
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`define DEC_BR_INST 13 // Branch instruction
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`define DEC_ALU_SZ 13
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`define DEC_ALU_INFO 12:0 // ALU info group
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`define DEC_ALU_SIGNED 12 // Signed operation
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`define DEC_ALU_IMM 11 // Use immediate instead of register
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`define DEC_ALU_LUI 10 // LUI (will treat as shift operation with immediate inputs)
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`define DEC_ALU_S_A 9 // Shift arithmetic (if 1, logical if 0)
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`define DEC_ALU_SR 8 // Shift right
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`define DEC_ALU_SL 7 // Shift left
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`define DEC_ALU_CMP 6 // Compare (SLT)
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`define DEC_ALU_OR 5 // Logical OR
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`define DEC_ALU_NOR 4 // Logical NOR
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`define DEC_ALU_XOR 3 // Logical XOR
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`define DEC_ALU_AND 2 // Logical AND
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`define DEC_ALU_SUB 1 // Subtraction
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`define DEC_ALU_ADD 0 // Addition
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*/
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// Fields of instruction decode bus from ID stage.
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// Note: to save on flops, ID stage will only determine basic instruction type
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// and register operand/destination information. Complete instruction decoding
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// will happen during last Dispatch cycle into Reservation Station.
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`define DEC_BUS_SZ 26
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`define DEC_REG_D_IDX 25:20 // Rd index
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`define DEC_REG_T_IDX 19:14 // Rt index
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`define DEC_REG_S_IDX 13:8 // Rs index
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`define DEC_REG_D_WR 7 // Writes to Rd
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`define DEC_REG_T_NEED 6 // Needs Rt operand
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`define DEC_REG_S_NEED 5 // Needs Rs operand
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`define DEC_TYPE_CP 4 // CP move instruction
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`define DEC_TYPE_BR 3 // Branch instruction
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`define DEC_TYPE_LDST 2 // Instruction handled by LDST unit
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`define DEC_TYPE_MULTDIV 1 // Instruction handled by MULT/DIV unit
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`define DEC_TYPE_ALU 0 // Instruction handled by ALU unit
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// ALU control bus for ALU operation.
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`define ALU_CTL_SZ 1
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// Fields of Branch/Jump operation bus
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`define BR_INFO_SZ 10
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`define BR_SYS 9 // SYSCALL
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`define BR_BRK 8 // BREAK
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`define BR_LINK 7 // Branch/Jump and link
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`define BR_JR 6 // JR/JALR
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`define BR_J 5 // J/JAL
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`define BR_NEG 4 // Negate condition (to get the rest of the conditions)
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`define BR_BGT 3 // BGTZ condition
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`define BR_BGE 2 // BGEZ condition
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`define BR_BEQ 1 // BEQ condition
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`define BR_INST 0 // Branch instruction
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// Fields of ALU information bus
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`define ALU_INFO_SZ 13
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`define ALU_SIGNED 12 // Signed operation
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`define ALU_IMM 11 // Use immediate instead of register
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`define ALU_LUI 10 // LUI (treated as shift op)
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`define ALU_S_A 9 // Shift arithmetic (if 1, logical if 0)
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`define ALU_SR 8 // Shift right
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`define ALU_SL 7 // Shift left
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`define ALU_CMP 6 // Compare (SLT)
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`define ALU_OR 5 // Logical OR
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`define ALU_NOR 4 // Logical NOR
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`define ALU_XOR 3 // Logical XOR
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`define ALU_AND 2 // Logical AND
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`define ALU_SUB 1 // Subtraction
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`define ALU_ADD 0 // Addition
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// Fields of rename information
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`define REN_BUS_SZ 35
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`define REN_DEST_IDX 34:29 // Destination (reg_d) index
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`define REN_DEST_VLD 28 // Writes to destination
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`define REN_DEST_TAG_OLD 27:22 // Destination (reg_d) old tag
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`define REN_DEST_TAG 21:16 // Destination (reg_d) tag
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`define REN_SRC2_VLD 15 // Source 2 data valid in register file
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`define REN_SRC2_NEED 14 // Need source 2 register data
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`define REN_SRC2_TAG 13:8 // Source 2 (reg_s) tag
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`define REN_SRC1_VLD 7 // Source 1 data valid in register file
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`define REN_SRC1_NEED 6 // Need source 1 register data
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`define REN_SRC1_TAG 5:0 // Source 1 (reg_s) tag
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// Reservation Station defines
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`define ALU_RS_ENTRIES 4 // Size of Reservation Station for ALU and branch
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`define ALU_RS_CNT_SZ 3 // Size of occupancy counter
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//`define ALU_RS_CNTL_SZ (`DEC_ALU_SZ+`DEC_BR_SZ+`DEC_CP_SZ+`ADDR_SZ+`IMM_SZ)
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`define MULTDIV_RS_ENTRIES 2 // Size of Reservation Station for MULT/DIV
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`define MULTDIV_RS_CNT_SZ 2 // Size of occupancy counter
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//`define MULTDIV_RS_CNTL_SZ (`DEC_MULTDIV_SZ)
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`define LDST_RS_ENTRIES 2 // Size of Reservation Station for Load/Store
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`define LDST_RS_CNT_SZ 2 // Size of occupancy counter
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//`define LDST_RS_CNTL_SZ (`DEC_MEM_SZ+`IMM_SZ)
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// CP0 Register fields
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`define CP0_STATUS_EXL 1
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// Feature ifdefs
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// Comment out define to remove feature from compilation
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//`define USE_PLL // Include PLL (exclude for simulation)
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`define USE_IC // include Instruction cache
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`define USE_DC // include Data cache
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//`define DYN_BPRD // TODO: Add back in later
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`define USE_IFB // Include instruction buffer between IF and ID stages
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`ifdef USE_IFB
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`define IFB_ENTRIES 4 // Number of fetch buffer entries
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`define IFB_ENTRY_SZ (`INSTR_SZ+`ADDR_SZ+`BP_SZ+1)
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`define IFB_PTR_SZ 2 // Fetch buffer pointer width
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`endif
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//`define TIMING_OPT // Use timing-optimized RTL in some portions (area affected)
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//`define ALTERA // Used to instantiate ALTERA megafunctions over generic logic
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