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[/] [opb_usblite/] [trunk/] [drivers/] [opb_usblite_v1_00_a/] [src/] [usblite_l.h] - Blame information for rev 6

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1 2 rehnmaak
/*
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--
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--    opb_usblite - opb_uartlite replacement
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--
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--    opb_usblite is using components from Rudolf Usselmann see
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--    http://www.opencores.org/cores/usb_phy/
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--    and Joris van Rantwijk see http://www.xs4all.nl/~rjoris/fpga/usb.html
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--
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--    Copyright (C) 2010 Ake Rehnman
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--
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--    This program is free software: you can redistribute it and/or modify
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--    it under the terms of the GNU Lesser General Public License as published by
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--    the Free Software Foundation, either version 3 of the License, or
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--    (at your option) any later version.
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--
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--    This program is distributed in the hope that it will be useful,
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--    but WITHOUT ANY WARRANTY; without even the implied warranty of
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--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--    GNU Lesser General Public License for more details.
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--
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--    You should have received a copy of the GNU Lesser General Public License
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--    along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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*/
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#ifndef USBLITE_L_H /* prevent circular inclusions */
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#define USBLITE_L_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* register offsets */
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#define XUL_RX_FIFO_OFFSET              0   /* receive FIFO, read only */
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#define XUL_TX_FIFO_OFFSET              4   /* transmit FIFO, write only */
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#define XUL_STATUS_REG_OFFSET           8   /* status register, read only */
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#define XUL_CONTROL_REG_OFFSET          12  /* control register, write only */
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/* control register bit positions */
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#define XUL_CR_ENABLE_INTR              0x10    /* enable interrupt */
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#define XUL_CR_FIFO_RX_RESET            0x02    /* reset receive FIFO */
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#define XUL_CR_FIFO_TX_RESET            0x01    /* reset transmit FIFO */
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/* status register bit positions */
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#define XUL_SR_INTR_ENABLED             0x10    /* interrupt enabled */
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#define XUL_SR_TX_FIFO_FULL             0x08    /* transmit FIFO full */
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#define XUL_SR_TX_FIFO_EMPTY            0x04    /* transmit FIFO empty */
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#define XUL_SR_RX_FIFO_FULL             0x02    /* receive FIFO full */
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#define XUL_SR_RX_FIFO_VALID_DATA       0x01    /* data in receive FIFO */
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/*****************************************************************************/
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#define usblite_out32(addr, data) *(unsigned int*)(addr)=(unsigned int)(data)
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#define usblite_in32(addr) *(unsigned int*)(addr)
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#define usblite_mSetControlReg(BaseAddress, Mask) \
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                    usblite_out32((BaseAddress) + XUL_CONTROL_REG_OFFSET, (Mask))
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#define usblite_mGetStatusReg(BaseAddress) \
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                    usblite_in32((BaseAddress) + XUL_STATUS_REG_OFFSET)
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#define usblite_mIsReceiveEmpty(BaseAddress) \
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  ((usblite_mGetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA) != \
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    XUL_SR_RX_FIFO_VALID_DATA)
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#define usblite_mIsTransmitFull(BaseAddress) \
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    ((usblite_mGetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) == \
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      XUL_SR_TX_FIFO_FULL)
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#define usblite_mIsIntrEnabled(BaseAddress) \
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    ((usblite_mGetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED) == \
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      XUL_SR_INTR_ENABLED)
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#define usblite_mEnableIntr(BaseAddress) \
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               usblite_mSetControlReg((BaseAddress), XUL_CR_ENABLE_INTR)
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#define usblite_mDisableIntr(BaseAddress) \
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              usblite_mSetControlReg((BaseAddress), 0)
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/************************** Function Prototypes *****************************/
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void usblite_SendByte(unsigned int base, unsigned char Data);
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unsigned char usblite_RecvByte(unsigned int base);
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#ifdef __cplusplus
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}
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#endif
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#endif            /* end of protection macro */
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