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[/] [opencpu32/] [trunk/] [hdl/] [opencpu32/] [testMultiplexer4_1.vhd] - Blame information for rev 42

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--! @file
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--! @brief Testbench for Multiplexer4_1
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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LIBRARY ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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--! Use CPU Definitions package
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use work.pkgOpenCPU32.all;
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ENTITY testMultiplexer4_1 IS
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END testMultiplexer4_1;
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--! @brief Multiplexer4_1 Testbench file
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--! @details Test multiplexer operations changing the selection signal
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--! for more information: http://en.wikipedia.org/wiki/Multiplexer
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ARCHITECTURE behavior OF testMultiplexer4_1 IS
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    --! Component declaration to instantiate the Multiplexer circuit
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    COMPONENT Multiplexer4_1
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    generic (n : integer := nBits - 1);                                 --! Generic value (Used to easily change the size of the Alu on the package)
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         Port ( A   : in  STD_LOGIC_VECTOR (n downto 0); --! First Input
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           B   : in  STD_LOGIC_VECTOR (n downto 0);      --! Second Input
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                          C   : in  STD_LOGIC_VECTOR (n downto 0);       --! Third Input
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                          D   : in  STD_LOGIC_VECTOR (n downto 0);       --! Forth Input
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                          E   : in  STD_LOGIC_VECTOR (n downto 0);       --! Fifth Input
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           sel : in  dpMuxInputs;                                                       --! Select inputs (1, 2, 3, 4, 5)
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           S   : out  STD_LOGIC_VECTOR (n downto 0));    --! Mux Output
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    END COMPONENT;
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   --Inputs
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   signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0');  --! Wire to connect Test signal to component
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   signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0');  --! Wire to connect Test signal to component
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        signal C : std_logic_vector((nBits - 1) downto 0) := (others => '0');     --! Wire to connect Test signal to component
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        signal D : std_logic_vector((nBits - 1) downto 0) := (others => '0');     --! Wire to connect Test signal to component
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        signal E : std_logic_vector((nBits - 1) downto 0) := (others => '0');     --! Wire to connect Test signal to component
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   signal sel : dpMuxInputs := fromMemory;                                                                                      --! Wire to connect Test signal to component
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        --Outputs
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   signal S : std_logic_vector((nBits - 1) downto 0);                                                    --! Wire to connect Test signal to component
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BEGIN
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        --!Instantiate the Unit Under Test (Multiplexer4_1) (Doxygen bug if it's not commented!)
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   uut: Multiplexer4_1 PORT MAP (
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          A => A,
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          B => B,
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                         C => C,
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                         D => D,
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                         E => E,
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          sel => sel,
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          S => S
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        );
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   --! Process that will change sel signal and verify the Mux outputs
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   stim_proc: process
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   begin
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      -- Sel 0 ---------------------------------------------------------------------------
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                wait for 1 ps;
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                REPORT "Select first channel" SEVERITY NOTE;
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                sel <= fromMemory;
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                A <= conv_std_logic_vector(0, nBits);
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                B <= conv_std_logic_vector(1000, nBits);
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                C <= conv_std_logic_vector(2000, nBits);
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                D <= conv_std_logic_vector(3000, nBits);
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                E <= conv_std_logic_vector(4000, nBits);
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                wait for 1 ns;  -- Wait to stabilize the response
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                assert S = (A) report "Could not select first channel" severity FAILURE;
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                -- Sel 1 ---------------------------------------------------------------------------
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                wait for 1 ns;
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                REPORT "Select second channel" SEVERITY NOTE;
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                sel <= fromImediate;
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                A <= conv_std_logic_vector(0, nBits);
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                B <= conv_std_logic_vector(1000, nBits);
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                C <= conv_std_logic_vector(2000, nBits);
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                D <= conv_std_logic_vector(3000, nBits);
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                E <= conv_std_logic_vector(4000, nBits);
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                wait for 1 ns;  -- Wait to stabilize the response
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                assert S = (B) report "Could not select second channel" severity FAILURE;
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                -- Sel 2 ---------------------------------------------------------------------------
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                wait for 1 ns;
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                REPORT "Select third channel" SEVERITY NOTE;
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                sel <= fromRegFileA;
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                A <= conv_std_logic_vector(0, nBits);
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                B <= conv_std_logic_vector(1000, nBits);
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                C <= conv_std_logic_vector(2000, nBits);
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                D <= conv_std_logic_vector(3000, nBits);
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                E <= conv_std_logic_vector(4000, nBits);
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                wait for 1 ns;  -- Wait to stabilize the response
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                assert S = (C) report "Could not select third channel" severity FAILURE;
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                -- Sel 3 ---------------------------------------------------------------------------
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                wait for 1 ns;
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                REPORT "Select forth channel" SEVERITY NOTE;
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                sel <= fromRegFileB;
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                A <= conv_std_logic_vector(0, nBits);
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                B <= conv_std_logic_vector(1000, nBits);
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                C <= conv_std_logic_vector(2000, nBits);
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                D <= conv_std_logic_vector(3000, nBits);
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                E <= conv_std_logic_vector(4000, nBits);
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                wait for 1 ns;  -- Wait to stabilize the response
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                assert S = (D) report "Could not select forth channel" severity FAILURE;
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                -- Sel 4 ---------------------------------------------------------------------------
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                wait for 1 ns;
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                REPORT "Select fifth channel" SEVERITY NOTE;
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                sel <= fromAlu;
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                A <= conv_std_logic_vector(0, nBits);
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                B <= conv_std_logic_vector(1000, nBits);
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                C <= conv_std_logic_vector(2000, nBits);
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                D <= conv_std_logic_vector(3000, nBits);
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                E <= conv_std_logic_vector(4000, nBits);
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                wait for 1 ns;  -- Wait to stabilize the response
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                assert S = (E) report "Could not select fifth channel" severity FAILURE;
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                -- Finish simulation
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                assert false report "NONE. End of simulation." severity failure;
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   end process;
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END;

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