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juko |
/*
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* .--------------. .----------------. .------------.
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* | .------------. | .--------------. | .----------. |
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* | | ____ ____ | | | ____ ____ | | | ______ | |
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* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
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* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
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* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
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* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
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* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
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* | | | | | | | | | | | |
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* |_| | '------------' | '--------------' | '----------' |
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* '--------------' '----------------' '------------'
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*
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* openHMC - An Open Source Hybrid Memory Cube Controller
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* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
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* www.ziti.uni-heidelberg.de
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* B6, 26
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* 68159 Mannheim
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* Germany
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*
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* Contact: openhmc@ziti.uni-heidelberg.de
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* http://ra.ziti.uni-heidelberg.de/openhmc
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*
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* This source file is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This source file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this source file. If not, see .
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*
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*
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*/
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`default_nettype none
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`timescale 100ps/10ps
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module dut #(
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//*************************Don't touch! Control the design with arguments when executing run.sh
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parameter LOG_NUM_LANES = `LOG_NUM_LANES,
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parameter NUM_LANES = 2**LOG_NUM_LANES,
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parameter LOG_FPW = `LOG_FPW,
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parameter FPW = `FPW,
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parameter DWIDTH = 128*FPW,
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parameter NUM_DATA_BYTES = 16*FPW,
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parameter LANE_WIDTH = DWIDTH / NUM_LANES
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//*************************
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)
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(
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//AXI4 user clock
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input wire clk_user,
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//125MHz reference clock
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input wire clk_hmc_refclk,
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//Global reset
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input wire res_n,
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//AXI4 interface ports
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axi4_stream_if axi4_req,
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axi4_stream_if axi4_rsp,
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//Register File interface
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cag_rgm_rfs_if rfs_hmc
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);
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//----------------------------- Wiring openHMC controller
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wire [DWIDTH-1:0] to_serializers;
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wire [DWIDTH-1:0] from_deserializers;
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wire [NUM_LANES-1:0] bit_slip;
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wire [NUM_LANES-1:0] phy_lane_polarity;
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bit P_RST_N;
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juko |
//If transceiver models are used, clk_hmc should be sourced from the transceiver outclock and res_n hmc can be set independently
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wire clk_hmc = clk_user;
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wire res_n_hmc = res_n;
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juko |
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// Wire the HMC BFM model
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wire LxRXPS; // HMC input
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wire LxTXPS; // HMC output
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wire FERR_N; // HMC output
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wire [16-1:0] LxRXP;
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wire [16-1:0] LxRXN;
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wire [16-1:0] LxTXP;
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wire [16-1:0] LxTXN;
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//----------------------------- Signal Routing from SerDes to HMC
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wire [NUM_LANES-1:0] serial_Rx;
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wire [NUM_LANES-1:0] serial_Txn;
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wire [NUM_LANES-1:0] serial_Txp;
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assign LxRXP = serial_Txp;
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assign LxRXN = ~LxRXP;
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assign serial_Rx = LxTXP[NUM_LANES-1:0];
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assign serial_Txn = ~serial_Txp;
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//----------------------------- Attach the Register File System interface
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assign rfs_hmc_if.clk = clk_hmc;
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juko |
assign rfs_hmc_if.res_n = res_n_hmc;
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juko |
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juko |
//Assign the AXI4 IF
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assign axi4_req.ACLK = (`OPENHMC_ASYNC_FIFOS==0) ? clk_hmc : clk_user;
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assign axi4_rsp.ACLK = (`OPENHMC_ASYNC_FIFOS==0) ? clk_hmc : clk_user;
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assign axi4_req.ARESET_N = (`OPENHMC_ASYNC_FIFOS==0) ? res_n_hmc : res_n;
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assign axi4_rsp.ARESET_N = (`OPENHMC_ASYNC_FIFOS==0) ? res_n_hmc : res_n;
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juko |
//----------------------------- Generate Clocks
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bit clk_10G;
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generate
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begin : clocking_gen
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initial clk_10G = 1'b1;
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always #0.05ns clk_10G = ~clk_10G;
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end
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endgenerate
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//----------------------------- Behavioral SerDes
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juko |
bit LxTXPS_synced;
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juko |
genvar lane;
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generate
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begin : serializers_gen
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for (lane=0; lane
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serializer #(
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.DWIDTH(LANE_WIDTH)
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) serializer_I (
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.clk(clk_hmc),
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juko |
.res_n(res_n),
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juko |
.fast_clk(clk_10G),
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.data_in(to_serializers[lane*LANE_WIDTH+LANE_WIDTH-1:lane*LANE_WIDTH]),
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.data_out(serial_Txp[lane])
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);
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deserializer #(
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.DWIDTH(LANE_WIDTH)
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) deserializer_I (
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.clk(clk_hmc),
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juko |
.res_n(LxTXPS_synced && res_n),
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.fast_clk(clk_10G),
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.bit_slip(bit_slip[lane]),
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.lane_polarity(phy_lane_polarity[lane]),
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.data_in(serial_Rx[lane]),
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.data_out(from_deserializers[lane*LANE_WIDTH+LANE_WIDTH-1:lane*LANE_WIDTH])
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);
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end
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end
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endgenerate
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juko |
always @(posedge clk_hmc) LxTXPS_synced <= LxTXPS;
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juko |
//=====================================================================================================
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//-----------------------------------------------------------------------------------------------------
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//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------------------
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//=====================================================================================================
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openhmc_top #(
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.LOG_FPW(LOG_FPW),
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.FPW(FPW),
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.LOG_NUM_LANES(LOG_NUM_LANES),
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//Configure the Functionality
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juko |
.LOG_MAX_RX_TOKENS(10),
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.LOG_MAX_HMC_TOKENS(10), //That is max 1023 Tokens
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juko |
.HMC_RX_AC_COUPLED(1),
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.CTRL_LANE_POLARITY(1),
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.CTRL_LANE_REVERSAL(1),
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.BITSLIP_SHIFT_RIGHT(1),
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juko |
.OPEN_RSP_MODE(`OPEN_RSP_MODE),
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.SYNC_AXI4_IF(`OPENHMC_ASYNC_FIFOS==0),
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juko |
//Debug Logic
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.DBG_RX_TOKEN_MON(1) //Required by the test check sequence
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)
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openhmc_instance
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(
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//----------------------------------
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//----SYSTEM INTERFACES
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//----------------------------------
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.clk_user(clk_user),
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.clk_hmc(clk_hmc),
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.res_n_user(res_n),
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.res_n_hmc(res_n),
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//----------------------------------
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//----Connect HMC Controller
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//----------------------------------
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//to TX
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.s_axis_tx_TVALID(axi4_req.TVALID),
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.s_axis_tx_TREADY(axi4_req.TREADY),
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.s_axis_tx_TDATA(axi4_req.TDATA),
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.s_axis_tx_TUSER(axi4_req.TUSER),
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//from RX
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.m_axis_rx_TVALID(axi4_rsp.TVALID),
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.m_axis_rx_TREADY(axi4_rsp.TREADY),
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.m_axis_rx_TDATA(axi4_rsp.TDATA),
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.m_axis_rx_TUSER(axi4_rsp.TUSER),
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//----------------------------------
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//----Connect Physical Link
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//----------------------------------
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.phy_data_tx_link2phy(to_serializers),
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.phy_data_rx_phy2link(from_deserializers),
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.phy_bit_slip(bit_slip),
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juko |
.phy_tx_ready(res_n),
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.phy_rx_ready(res_n),
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juko |
.phy_lane_polarity(phy_lane_polarity),
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juko |
.phy_init_cont_set(),
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juko |
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//----------------------------------
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//----Connect HMC
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//----------------------------------
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.P_RST_N(P_RST_N),
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juko |
.LXRXPS(LxRXPS),
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.LXTXPS(LxTXPS),
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juko |
.FERR_N(FERR_N),
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//----------------------------------
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//----Connect RF
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//----------------------------------
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.rf_address(rfs_hmc.address),
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.rf_read_data(rfs_hmc.read_data),
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.rf_invalid_address(rfs_hmc.invalid_address),
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.rf_access_complete(rfs_hmc.access_done),
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.rf_read_en(rfs_hmc.ren),
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.rf_write_en(rfs_hmc.wen),
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.rf_write_data(rfs_hmc.write_data)
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);
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//********************************************************************************
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// From MICRON's hmc_bfm_tb.sv
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//******************************************
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//BFM
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hmc_bfm #(
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.num_links_c (1)
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)
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hmc_bfm0 (
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.LxRXP (LxRXP),
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.LxRXN (LxRXN),
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.LxTXP (LxTXP),
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.LxTXN (LxTXN),
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.LxRXPS (LxRXPS),
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.LxTXPS (LxTXPS),
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.FERR_N (FERR_N),
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.REFCLKP (clk_hmc_refclk),
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.REFCLKN (~clk_hmc_refclk),
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.REFCLKSEL (1'b0),
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.P_RST_N (P_RST_N),
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.TRST_N (1'b0),
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.TCK (1'b0),
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.TMS (1'b0),
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.TDI (1'b0),
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.TDO (),
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.SCL (1'b0),
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.SDA (),
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.CUB (3'b0),
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.REFCLK_BOOT (2'b0),
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.EXTRESTP (),
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.EXTRESTN (),
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.EXTRESBP (),
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.EXTRESBN ()
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);
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endmodule : dut
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`default_nettype wire
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