OpenCores
URL https://opencores.org/ocsvn/openhmc/openhmc/trunk

Subversion Repositories openhmc

[/] [openhmc/] [trunk/] [openHMC/] [sim/] [tb/] [uvc/] [testlib/] [openhmc_init_seq.sv] - Blame information for rev 15

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 juko
/*
2
 *                              .--------------. .----------------. .------------.
3
 *                             | .------------. | .--------------. | .----------. |
4
 *                             | | ____  ____ | | | ____    ____ | | |   ______ | |
5
 *                             | ||_   ||   _|| | ||_   \  /   _|| | | .' ___  || |
6
 *       ___  _ __   ___ _ __  | |  | |__| |  | | |  |   \/   |  | | |/ .'   \_|| |
7
 *      / _ \| '_ \ / _ \ '_ \ | |  |  __  |  | | |  | |\  /| |  | | || |       | |
8
 *       (_) | |_) |  __/ | | || | _| |  | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
9
 *      \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
10
 *           | |               | |            | | |              | | |          | |
11
 *           |_|               | '------------' | '--------------' | '----------' |
12
 *                              '--------------' '----------------' '------------'
13
 *
14
 *  openHMC - An Open Source Hybrid Memory Cube Controller
15
 *  (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
16
 *  www.ziti.uni-heidelberg.de
17
 *  B6, 26
18
 *  68159 Mannheim
19
 *  Germany
20
 *
21
 *  Contact: openhmc@ziti.uni-heidelberg.de
22
 *  http://ra.ziti.uni-heidelberg.de/openhmc
23
 *
24
 *   This source file is free software: you can redistribute it and/or modify
25
 *   it under the terms of the GNU Lesser General Public License as published by
26
 *   the Free Software Foundation, either version 3 of the License, or
27
 *   (at your option) any later version.
28
 *
29
 *   This source file is distributed in the hope that it will be useful,
30
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
31
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
32
 *   GNU Lesser General Public License for more details.
33
 *
34
 *   You should have received a copy of the GNU Lesser General Public License
35
 *   along with this source file.  If not, see .
36
 *
37
 *
38
 */
39
 
40
`ifndef OPENHMC_INIT_SEQ
41
`define OPENHMC_INIT_SEQ
42
 
43
class openhmc_init_seq extends hmc_base_seq;
44
 
45
        // hmc_link_config link_config;
46
 
47
        function new(string name="openhmc_init_seq");
48
                super.new(name);
49
        endfunction : new
50
 
51
        `uvm_object_utils(openhmc_init_seq)
52
        `uvm_declare_p_sequencer(vseqr)
53
 
54
        bit phy_tx_ready        = 1'b0;
55
        bit phy_rx_ready        = 1'b0;
56
        bit link_up             = 1'b0;
57
        int timeout             = 0;
58
        int delay;
59
 
60
        task body();
61
 
62
                //-- configure the HMC controller
63
                reg_openhmc_rf_control_c                control;
64
                reg_openhmc_rf_status_general_c status;
65
                reg_openhmc_rf_status_init_c    status_init;
66
                reg_openhmc_rf_counter_reset_c  cnt_reset;
67
 
68
                `uvm_info(get_type_name(), "Running init sequence", UVM_NONE)
69
 
70
                $cast(control,p_sequencer.rf_seqr_hmc.get_by_name("control"));
71
                control.set_check_on_read(1'b0);
72
                p_sequencer.rf_seqr_hmc.read_reg(control);
73
 
74
                control.fields.rx_token_count_                   = p_sequencer.link_cfg.rx_tokens;
75
                control.fields.scrambler_disable_                = ~p_sequencer.link_cfg.scramblers_enabled;
76
                control.fields.bit_slip_time_                    = 40;
77
                control.fields.set_hmc_sleep_                    = 0;
78
                control.fields.run_length_enable_                = ~p_sequencer.link_cfg.scramblers_enabled;
79
                control.fields.irtry_to_send_                    = p_sequencer.link_cfg.requester.irtry_flit_count_to_send;
80
                control.fields.irtry_received_threshold_ = p_sequencer.link_cfg.requester.irtry_flit_count_received_threshold;
81
 
82
                p_sequencer.rf_seqr_hmc.write_reg(control);
83
 
84
                //Dummy Read to status init
85
                $cast(status_init,p_sequencer.rf_seqr_hmc.get_by_name("status_init"));
86
                status_init.set_check_on_read(1'b0);
87
                p_sequencer.rf_seqr_hmc.read_reg(status_init);
88
 
89
                //Dummy counter reset
90
                $cast(cnt_reset,p_sequencer.rf_seqr_hmc.get_by_name("counter_reset"));
91
                cnt_reset.fields.rreinit_ = 1;
92
                p_sequencer.rf_seqr_hmc.write_reg(cnt_reset);
93
 
94
                //-- Wait until the PHY is out of reset
95
                $cast(status,p_sequencer.rf_seqr_hmc.get_by_name("status_general"));
96
                status.set_check_on_read(1'b0);
97
                while (phy_tx_ready == 1'b0)
98
                begin
99
                        #1us;
100
                        p_sequencer.rf_seqr_hmc.read_reg(status);
101
                        phy_tx_ready = status.fields.phy_tx_ready_;
102
                        `uvm_info(get_type_name(), "Waiting for the PHY TX to get ready", UVM_NONE)
103
                end
104
                `uvm_info(get_type_name(), "Phy TX ready", UVM_NONE)
105
 
106
                //------------------------------------------------------- Set Reset and Init Continue
107
                control.fields.p_rst_n_ = 1;
108
                p_sequencer.rf_seqr_hmc.write_reg(control);
109
                #1us;
110
 
111
                control.fields.hmc_init_cont_set_ = 1;
112
                p_sequencer.rf_seqr_hmc.write_reg(control);
113
                `uvm_info(get_type_name(), "Init cont in RF set", UVM_NONE)
114
 
115
                //------------------------------------------------------- Wait for the PHY to get ready
116
                while (phy_rx_ready == 1'b0)
117
                begin
118
                        #1us;
119
                        p_sequencer.rf_seqr_hmc.read_reg(status);
120
                        phy_rx_ready = status.fields.phy_rx_ready_;
121
                        `uvm_info(get_type_name(), "Waiting for PHY RX to get ready", UVM_NONE)
122
                end
123
                `uvm_info(get_type_name(), "Phy RX is ready", UVM_NONE)
124
 
125
                //-- Poll on link_up to make sure that it comes up.
126
                while (link_up == 1'b0)
127
                begin
128
                        if (timeout == 8000) //-- Try Resetting it.
129
                        begin
130
                                `uvm_fatal(get_type_name(), "The link didn't come up...")
131
                        end
132
                        #4ns;
133
                        p_sequencer.rf_seqr_hmc.read_reg(status);
134
                        link_up = status.fields.link_up_;
135
                        timeout = timeout + 1;
136
                end
137
                `uvm_info(get_type_name(), "Link is UP !", UVM_NONE)
138
 
139
        endtask : body
140
 
141
endclass : openhmc_init_seq
142
 
143
`endif // OPENHMC_INIT_SEQ

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.