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[/] [openjtag-project/] [trunk/] [OpenJTAG/] [Quartus_II/] [tap_sm.vhd] - Blame information for rev 18

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-- Created by Ruben H. Mileca - May-16-2010
 
 
library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.all;
 
entity tap_sm IS
 
--      generic (
--              new_state: integer range 0 to 15 := 1
--      );
 
                port (
 
                clk:            in std_logic;                                           -- External 48 MHz oscillator
                rst:            in std_logic;                                           -- External reset, active high
                new_state:      in std_logic_vector(3 downto 0); -- New state
                tck:            out std_logic := '0';                            -- TCK Jtag pin
                tms:            out std_logic := '0';                            -- TMS Jtag pin
                wrk:            out std_logic := '0';                            -- SM working
 
                sm:                     out std_logic_vector(3 downto 0) -- Test output
 
        );
 
end tap_sm;
 
architecture rtl of tap_sm is
 
        signal state:           integer range 0 to 15 := 0;
        signal astate:          integer range 0 to 15 := 0;
        signal rclk:            integer range 0 to 1 := 0;
 
begin
 
 
changestate: process(clk, rst, state)
 
begin
 
        if (rising_edge(clk)) then
                if rclk = 1 then
                        rclk <= 0;
                else
                        rclk <= 1;
                end if;
 
                astate <= to_integer(unsigned(new_state));
                sm <= std_logic_vector(to_unsigned(state, sm'length));
 
--      TAP Change state machine
 
                if state /= astate then
                        wrk <= '1';
                        if rclk = 1 then
                                tms <= '0';
                        end if;
                        case state is
                                when 0 =>                                        -- Is in Test Logic Reset
                                        if rclk = 1 then
                                                tms <= '0';
                                                tck <= '0';
                                        else
                                                tck <= '1';
                                                state <= 1;
                                        end if;
                                when 1 =>                                       -- Is in Run Test Idle
                                        if rclk = 1 then
                                                tms <= '1';
                                                tck <= '0';
                                        else
                                                tck <= '1';
                                                state <= 2;
                                        end if;
--
-- DR way
--
                                when 2 =>                                       -- Is in Select DR Scan
                                        if rclk = 1 then
                                                if astate > 8 then      -- See if go to Select IR Scan
                                                        tms <= '1';
                                                else
                                                        tms <= '0';
                                                end if;
                                                tck <= '0';
                                        else
                                                if astate > 8 then      -- See if go to Select IR Scan
                                                        state <= 9;             -- Go to Select IR Scan
                                                else
                                                        state <= 3;             -- Go to Capture DR
                                                end if;
                                                tck <= '1';
                                        end if;
                                when 3 =>                                       -- Is in Capture DR
                                        if rclk = 1 then
                                                if astate > 4 then      -- See if go to Exit-1 DR
                                                        tms <= '1';
                                                else
                                                        tms <= '0';
                                                end if;
                                                tck <= '0';
                                        else
                                                tck <= '1';
                                                if astate > 4 then      -- See if go to Exit-1 DR
                                                        state <= 5;             -- Go to Exit-1 DR
                                                else
                                                        state <= 4;             -- Go to Capture DR
                                                end if;
                                        end if;
                                when 4 =>                                       -- Is in Capture DR
                                        if rclk = 1 then
                                                tms <= '1';
                                                tck <= '0';
                                        else
                                                tck <= '1';
                                                state <= 5;
                                        end if;
                                when 5 =>                                       -- Is in Exit-1 DR
                                        if rclk = 1 then
                                                if astate = 6 then      -- See if go to Pause DR
                                                        tms <= '0';
                                                else
                                                        tms <= '1';
                                                end if;
                                                tck <= '0';
                                        else
                                                tck <= '1';
                                                if astate = 6 then      -- See if go to Pause DR
                                                        state <= 6;             -- Go to Exit-1 DR
                                                else
                                                        state <= 8;             -- Go to Capture DR
                                                end if;
                                        end if;
                                when 6 =>                                       -- Is in Pause DR
                                        if rclk = 1 then
                                                tms <= '1';
                                                tck <= '0';
                                        else
                                                tck <= '1';
                                                state <= 7;
                                        end if;
                                when 7 =>                                       -- Is in Exit-2 DR
                                        if rclk = 1 then
                                                if astate = 4 then      -- See if go to Shift DR
                                                        tms <= '0';
                                                else
                                                        tms <= '1';
                                                end if;
                                                tck <= '0';
                                        else
                                                tck <= '1';
                                                if astate = 4 then      -- See if go to Pause DR
                                                        state <= 4;             -- Go to Pause DR
                                                else
                                                        state <= 8;             -- Go to Update DR
                                                end if;
                                        end if;
                                when 8 =>                                       -- Is in Exit-2 DR
                                        if rclk = 1 then
                                                if astate > 1 then      -- See if go to Select DR Scan
                                                        tms <= '1';
                                                else
                                                        tms <= '0';
                                                end if;
                                                tck <= '0';
                                        else
                                                tck <= '1';
                                                if astate > 1 then      -- See if go to Select DR Scan
                                                        state <= 2;             -- Go to Select DR Scan
                                                else
                                                        state <= 1;             -- Go to Run Test Idle
                                                end if;
                                        end if;
--
--      IR way
--
                                when 9 =>                                       -- Is in Select IR Scan
                                        if rclk = 1 then
                                                if astate = 1 then      -- See if go to Test Logic Reset
                                                        tms <= '1';
                                                else
                                                        tms <= '0';
                                                end if;
                                                tck <= '0';
                                        else
                                                tck <= '1';
                                                if astate = 1 then      -- See if go to Test Logic Reset
                                                        state <= 1;             -- Go to Test Logic Reset
                                                else
                                                        state <= 10;    -- Go to Capture IR
                                                end if;
                                        end if;
                                when 10 =>                                      -- Is in Capture IR
                                        if rclk = 1 then
                                                if astate = 11 then     -- See if go to Shift-IR
                                                        tms <= '0';
                                                else
                                                        tms <= '1';
                                                end if;
                                                tck <= '0';
                                        else
                                                tck <= '1';
                                                if astate = 11 then     -- See if go to Shift-IR
                                                        state <= 11;            -- Go to Shift-IR
                                                else
                                                        state <= 12;    -- Go to Exit 1-IR
                                                end if;
                                        end if;
                                when 11 =>                                      -- Is in Shift-IR
                                        if rclk = 1 then
                                                tms <= '1';
                                                tck <= '0';
                                        else
                                                tck <= '1';
                                                state <= 12;
                                        end if;
                                when 12 =>                                      -- Is in Exit 1-IR
                                        if rclk = 1 then
                                                if astate > 13 then     -- See if go to Update-IR
                                                        tms <= '1';
                                                else
                                                        tms <= '0';
                                                end if;
                                                tck <= '0';
                                        else
                                                tck <= '1';
                                                if astate > 13 then     -- See if go to Update-IR
                                                        state <= 15;            -- Go to Update-IR
                                                else
                                                        state <= 13;    -- Go to Pause-IR
                                                end if;
                                        end if;
                                when 13 =>                                      -- Is in Pause-IR
                                        if rclk = 1 then
                                                tms <= '1';
                                                tck <= '0';
                                        else
                                                tck <= '1';
                                                state <= 14;
                                        end if;
                                when 14 =>                                      -- Is in Exit 2-IR
                                        if rclk = 1 then
                                                if astate = 11 then     -- See if go to Shift-IR
                                                        tms <= '0';
                                                else
                                                        tms <= '0';
                                                end if;
                                                tck <= '0';
                                        else
                                                tck <= '1';
                                                if astate = 11 then     -- See if go to Shift-IR
                                                        state <= 11;            -- Go to Shift-IR
                                                else
                                                        state <= 15;            -- Go to Update-IR
                                                end if;
                                        end if;
                                when 15 =>                                      -- Is in Update-IR
                                        if rclk = 1 then
                                                if astate > 1 then      -- See if go to Select DR-Scan
                                                        tms <= '1';
                                                else
                                                        tms <= '0';
                                                end if;
                                                tck <= '0';
                                        else
                                                tck <= '1';
                                                if astate > 1 then      -- See if go to Select DR-Scan
                                                        state <= 2;             -- Go to Update-IR
                                                else
                                                        state <= 1;             -- Go to Run Test-Idle
                                                end if;
                                        end if;
                                when others =>
                                                tck <= '0';
                                                tms <= '0';
                        end case;
                else
                        astate <= to_integer(unsigned(new_state));
                        tck <= '0';
                        tms <= '0';
                        wrk <= '0';
                end if;
        end if;
end process changestate;
end rtl;

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[/] [openjtag-project/] [trunk/] [OpenJTAG/] [Quartus_II/] [tap_sm.vhd] - Blame information for rev 18

Line No.	Rev	Author	Line
1	18	rmileca	`-- Created by Ruben H. Mileca - May-16-2010`
2
3
4			`library ieee;`
5			`USE ieee.std_logic_1164.ALL;`
6			`USE ieee.numeric_std.all;`
7
8			`entity tap_sm IS`
9
10			`-- generic (`
11			`-- new_state: integer range 0 to 15 := 1`
12			`-- );`
13
14			`port (`
15
16			`clk: in std_logic; -- External 48 MHz oscillator`
17			`rst: in std_logic; -- External reset, active high`
18			`new_state: in std_logic_vector(3 downto 0); -- New state`
19			`tck: out std_logic := '0'; -- TCK Jtag pin`
20			`tms: out std_logic := '0'; -- TMS Jtag pin`
21			`wrk: out std_logic := '0'; -- SM working`
22
23			`sm: out std_logic_vector(3 downto 0) -- Test output`
24
25			`);`
26
27			`end tap_sm;`
28
29			`architecture rtl of tap_sm is`
30
31			`signal state: integer range 0 to 15 := 0;`
32			`signal astate: integer range 0 to 15 := 0;`
33			`signal rclk: integer range 0 to 1 := 0;`
34
35			`begin`
36
37
38			`changestate: process(clk, rst, state)`
39
40			`begin`
41
42			`if (rising_edge(clk)) then`
43			`if rclk = 1 then`
44			`rclk <= 0;`
45			`else`
46			`rclk <= 1;`
47			`end if;`
48
49			`astate <= to_integer(unsigned(new_state));`
50			`sm <= std_logic_vector(to_unsigned(state, sm'length));`
51
52			`-- TAP Change state machine`
53
54			`if state /= astate then`
55			`wrk <= '1';`
56			`if rclk = 1 then`
57			`tms <= '0';`
58			`end if;`
59			`case state is`
60			`when 0 => -- Is in Test Logic Reset`
61			`if rclk = 1 then`
62			`tms <= '0';`
63			`tck <= '0';`
64			`else`
65			`tck <= '1';`
66			`state <= 1;`
67			`end if;`
68			`when 1 => -- Is in Run Test Idle`
69			`if rclk = 1 then`
70			`tms <= '1';`
71			`tck <= '0';`
72			`else`
73			`tck <= '1';`
74			`state <= 2;`
75			`end if;`
76			`--`
77			`-- DR way`
78			`--`
79			`when 2 => -- Is in Select DR Scan`
80			`if rclk = 1 then`
81			`if astate > 8 then -- See if go to Select IR Scan`
82			`tms <= '1';`
83			`else`
84			`tms <= '0';`
85			`end if;`
86			`tck <= '0';`
87			`else`
88			`if astate > 8 then -- See if go to Select IR Scan`
89			`state <= 9; -- Go to Select IR Scan`
90			`else`
91			`state <= 3; -- Go to Capture DR`
92			`end if;`
93			`tck <= '1';`
94			`end if;`
95			`when 3 => -- Is in Capture DR`
96			`if rclk = 1 then`
97			`if astate > 4 then -- See if go to Exit-1 DR`
98			`tms <= '1';`
99			`else`
100			`tms <= '0';`
101			`end if;`
102			`tck <= '0';`
103			`else`
104			`tck <= '1';`
105			`if astate > 4 then -- See if go to Exit-1 DR`
106			`state <= 5; -- Go to Exit-1 DR`
107			`else`
108			`state <= 4; -- Go to Capture DR`
109			`end if;`
110			`end if;`
111			`when 4 => -- Is in Capture DR`
112			`if rclk = 1 then`
113			`tms <= '1';`
114			`tck <= '0';`
115			`else`
116			`tck <= '1';`
117			`state <= 5;`
118			`end if;`
119			`when 5 => -- Is in Exit-1 DR`
120			`if rclk = 1 then`
121			`if astate = 6 then -- See if go to Pause DR`
122			`tms <= '0';`
123			`else`
124			`tms <= '1';`
125			`end if;`
126			`tck <= '0';`
127			`else`
128			`tck <= '1';`
129			`if astate = 6 then -- See if go to Pause DR`
130			`state <= 6; -- Go to Exit-1 DR`
131			`else`
132			`state <= 8; -- Go to Capture DR`
133			`end if;`
134			`end if;`
135			`when 6 => -- Is in Pause DR`
136			`if rclk = 1 then`
137			`tms <= '1';`
138			`tck <= '0';`
139			`else`
140			`tck <= '1';`
141			`state <= 7;`
142			`end if;`
143			`when 7 => -- Is in Exit-2 DR`
144			`if rclk = 1 then`
145			`if astate = 4 then -- See if go to Shift DR`
146			`tms <= '0';`
147			`else`
148			`tms <= '1';`
149			`end if;`
150			`tck <= '0';`
151			`else`
152			`tck <= '1';`
153			`if astate = 4 then -- See if go to Pause DR`
154			`state <= 4; -- Go to Pause DR`
155			`else`
156			`state <= 8; -- Go to Update DR`
157			`end if;`
158			`end if;`
159			`when 8 => -- Is in Exit-2 DR`
160			`if rclk = 1 then`
161			`if astate > 1 then -- See if go to Select DR Scan`
162			`tms <= '1';`
163			`else`
164			`tms <= '0';`
165			`end if;`
166			`tck <= '0';`
167			`else`
168			`tck <= '1';`
169			`if astate > 1 then -- See if go to Select DR Scan`
170			`state <= 2; -- Go to Select DR Scan`
171			`else`
172			`state <= 1; -- Go to Run Test Idle`
173			`end if;`
174			`end if;`
175			`--`
176			`-- IR way`
177			`--`
178			`when 9 => -- Is in Select IR Scan`
179			`if rclk = 1 then`
180			`if astate = 1 then -- See if go to Test Logic Reset`
181			`tms <= '1';`
182			`else`
183			`tms <= '0';`
184			`end if;`
185			`tck <= '0';`
186			`else`
187			`tck <= '1';`
188			`if astate = 1 then -- See if go to Test Logic Reset`
189			`state <= 1; -- Go to Test Logic Reset`
190			`else`
191			`state <= 10; -- Go to Capture IR`
192			`end if;`
193			`end if;`
194			`when 10 => -- Is in Capture IR`
195			`if rclk = 1 then`
196			`if astate = 11 then -- See if go to Shift-IR`
197			`tms <= '0';`
198			`else`
199			`tms <= '1';`
200			`end if;`
201			`tck <= '0';`
202			`else`
203			`tck <= '1';`
204			`if astate = 11 then -- See if go to Shift-IR`
205			`state <= 11; -- Go to Shift-IR`
206			`else`
207			`state <= 12; -- Go to Exit 1-IR`
208			`end if;`
209			`end if;`
210			`when 11 => -- Is in Shift-IR`
211			`if rclk = 1 then`
212			`tms <= '1';`
213			`tck <= '0';`
214			`else`
215			`tck <= '1';`
216			`state <= 12;`
217			`end if;`
218			`when 12 => -- Is in Exit 1-IR`
219			`if rclk = 1 then`
220			`if astate > 13 then -- See if go to Update-IR`
221			`tms <= '1';`
222			`else`
223			`tms <= '0';`
224			`end if;`
225			`tck <= '0';`
226			`else`
227			`tck <= '1';`
228			`if astate > 13 then -- See if go to Update-IR`
229			`state <= 15; -- Go to Update-IR`
230			`else`
231			`state <= 13; -- Go to Pause-IR`
232			`end if;`
233			`end if;`
234			`when 13 => -- Is in Pause-IR`
235			`if rclk = 1 then`
236			`tms <= '1';`
237			`tck <= '0';`
238			`else`
239			`tck <= '1';`
240			`state <= 14;`
241			`end if;`
242			`when 14 => -- Is in Exit 2-IR`
243			`if rclk = 1 then`
244			`if astate = 11 then -- See if go to Shift-IR`
245			`tms <= '0';`
246			`else`
247			`tms <= '0';`
248			`end if;`
249			`tck <= '0';`
250			`else`
251			`tck <= '1';`
252			`if astate = 11 then -- See if go to Shift-IR`
253			`state <= 11; -- Go to Shift-IR`
254			`else`
255			`state <= 15; -- Go to Update-IR`
256			`end if;`
257			`end if;`
258			`when 15 => -- Is in Update-IR`
259			`if rclk = 1 then`
260			`if astate > 1 then -- See if go to Select DR-Scan`
261			`tms <= '1';`
262			`else`
263			`tms <= '0';`
264			`end if;`
265			`tck <= '0';`
266			`else`
267			`tck <= '1';`
268			`if astate > 1 then -- See if go to Select DR-Scan`
269			`state <= 2; -- Go to Update-IR`
270			`else`
271			`state <= 1; -- Go to Run Test-Idle`
272			`end if;`
273			`end if;`
274			`when others =>`
275			`tck <= '0';`
276			`tms <= '0';`
277			`end case;`
278			`else`
279			`astate <= to_integer(unsigned(new_state));`
280			`tck <= '0';`
281			`tms <= '0';`
282			`wrk <= '0';`
283			`end if;`
284			`end if;`
285			`end process changestate;`
286			`end rtl;`