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[/] [openrisc/] [trunk/] [or1k_startup/] [backend/] [ACTEL/] [smartgen/] [flash/] [flash.v] - Blame information for rev 2

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`timescale 1 ns/100 ps
// Version: 8.5 8.5.0.34
 
 
module flash(CLK,ADDR,DOUT);
input CLK;
input [6:0] ADDR;
output [7:0] DOUT;
 
    wire U_7_PIN2;
 
    GND GND_1_net(.Y(U_7_PIN2));
    UFROMH #( .MEMORYFILE("flash.mem"), .ACT_PROGFILE("flash.ufc")
         )  UFROM0(.CLK(CLK), .DO0(DOUT[0]), .DO1(DOUT[1]), .DO2(
        DOUT[2]), .DO3(DOUT[3]), .DO4(DOUT[4]), .DO5(DOUT[5]),
        .DO6(DOUT[6]), .DO7(DOUT[7]), .ADDR0(ADDR[0]), .ADDR1(
        ADDR[1]), .ADDR2(ADDR[2]), .ADDR3(ADDR[3]), .ADDR4(
        ADDR[4]), .ADDR5(ADDR[5]), .ADDR6(ADDR[6]));
 
endmodule

Line No.	Rev	Author	Line
1	2	marcus.erl	`timescale 1 ns/100 ps
2			`// Version: 8.5 8.5.0.34`
3
4
5			`module flash(CLK,ADDR,DOUT);`
6			`input CLK;`
7			`input [6:0] ADDR;`
8			`output [7:0] DOUT;`
9
10			`wire U_7_PIN2;`
11
12			`GND GND_1_net(.Y(U_7_PIN2));`
13			`UFROMH #( .MEMORYFILE("flash.mem"), .ACT_PROGFILE("flash.ufc")`
14			`) UFROM0(.CLK(CLK), .DO0(DOUT[0]), .DO1(DOUT[1]), .DO2(`
15			`DOUT[2]), .DO3(DOUT[3]), .DO4(DOUT[4]), .DO5(DOUT[5]),`
16			`.DO6(DOUT[6]), .DO7(DOUT[7]), .ADDR0(ADDR[0]), .ADDR1(`
17			`ADDR[1]), .ADDR2(ADDR[2]), .ADDR3(ADDR[3]), .ADDR4(`
18			`ADDR[4]), .ADDR5(ADDR[5]), .ADDR6(ADDR[6]));`
19
20			`endmodule`

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[/] [openrisc/] [trunk/] [or1k_startup/] [backend/] [ACTEL/] [smartgen/] [flash/] [flash.v] - Blame information for rev 2