OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [vpi/] [c/] [rsp-vpi.h] - Blame information for rev 46

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 40 julius
/*$$HEADER*/
2
/******************************************************************************/
3
/*                                                                            */
4
/*                    H E A D E R   I N F O R M A T I O N                     */
5
/*                                                                            */
6
/******************************************************************************/
7
 
8
// Project Name                   : ORPSoCv2
9
// File Name                      : rsp-vpi.h
10
// Prepared By                    : jb, jb@orsoc.se
11
// Project Start                  : 2009-05-01
12
 
13
/*$$COPYRIGHT NOTICE*/
14
/******************************************************************************/
15
/*                                                                            */
16
/*                      C O P Y R I G H T   N O T I C E                       */
17
/*                                                                            */
18
/******************************************************************************/
19
/*
20
  This library is free software; you can redistribute it and/or
21
  modify it under the terms of the GNU Lesser General Public
22
  License as published by the Free Software Foundation;
23
  version 2.1 of the License, a copy of which is available from
24
  http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt.
25
 
26
  This library is distributed in the hope that it will be useful,
27
  but WITHOUT ANY WARRANTY; without even the implied warranty of
28
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
29
  Lesser General Public License for more details.
30
 
31
  You should have received a copy of the GNU Lesser General Public
32
  License along with this library; if not, write to the Free Software
33
  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
34
*/
35
 
36
// Defines for protocol ensuring synchronisation with the simulation process
37
 
38
// 1. rsp-rtl_sim will first write a command byte
39
// 2. rsp-rtl_sim will then send the address if it's a read or write
40
//    or the data to write if it's a dbg_cpu_wr_ctrl (stall & reset bits)
41
// 3. will then send data if we're writing and we sent address in 2
42
// 4. wait for response from vpi functions
43
 
44
// commands:
45
// 4'h1 jtag set instruction register (input: instruction value)
46
// 4'h2 set debug chain (dbg_set_command here) (input: chain value)
47
// 4'h3 cpu_ctrl_wr (input: ctrl value (2 bits))
48
// 4'h4 cpu_ctrl_rd (output: ctrl value (2bits))
49
// 4'h5 cpu wr reg (inputs: address, data)
50
// 4'h6 cpu rd reg (input: address; output: data)
51 46 julius
// 4'h7 wb wr  (inputs: address, data, size)
52 40 julius
// 4'h8 wb rd 32 (input: address; output: data)
53
// 4'h9 wb wr block 32 (inputs: address, length, data)
54
// 4'ha wb rd block 32 (inputs: address, length; output: data)
55
// 4'hb reset
56
// 4'hc read jtag id (output: data)
57
// 4'hd GDB detach - do something (like close down, restart, etc.)
58
 
59
// There should be a correlating set of verilog `define's in the 
60
// verilog debug testbench module's include file, test_defines.v
61
 
62
#define CMD_JTAG_SET_IR 0x1
63
#define CMD_SET_DEBUG_CHAIN 0x2
64
#define CMD_CPU_CTRL_WR 0x3
65
#define CMD_CPU_CTRL_RD 0x4
66
#define CMD_CPU_WR_REG 0x5
67
#define CMD_CPU_RD_REG 0x6
68 46 julius
#define CMD_WB_WR 0x7
69 40 julius
#define CMD_WB_RD32 0x8
70
#define CMD_WB_BLOCK_WR32 0x9
71
#define CMD_WB_BLOCK_RD32 0xa
72
#define CMD_RESET 0xb
73
#define CMD_READ_JTAG_ID 0xc
74
#define CMD_GDB_DETACH 0xd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.