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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] [README] - Blame information for rev 361

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1 361 julius
UART 16550 compatible (mostly) core RTL
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http://opencores.org/project,uart16550
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The core is configured to be in 8-bit mode in this project.

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