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[/] [orsoc_graphics_accelerator/] [trunk/] [sw/] [drivers/] [gfx/] [bare/] [orgfx.c] - Blame information for rev 5

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/*
Bare metal OpenCores GFX IP driver for Wishbone bus.
 
Anton Fosselius, Per Lenander 2012
  */
 
#include "orgfx.h"
#include "orgfx_regs.h"
 
#define GFX_STAT_COUNT_OFFSET 16
#define GFX_INSTRUCTION_FIFO_SIZE 1024
 
#define SUBPIXEL_WIDTH 16
 
/* VGA defines */
#define VGA_BASEADDR   0x97000000 /* Bus Adress to VGA */
 
#define VGA_CTRL       (VGA_BASEADDR + 0x000) /* Control Register */
#define VGA_STAT       (VGA_BASEADDR + 0x004) /* Status Register */
#define VGA_HTIM       (VGA_BASEADDR + 0x008) /* Horisontal Timing Register */
#define VGA_VTIM       (VGA_BASEADDR + 0x00c) /* Vertical Timing Register */
#define VGA_HVLEN      (VGA_BASEADDR + 0x010) /* Horisontal and Vertical Total Screen Size, (Screen size + Blank) */
#define VGA_VBARA      (VGA_BASEADDR + 0x014) /* Adress to Video Base Register A */
#define VGA_VBARB      (VGA_BASEADDR + 0x018) /* Adress to Video Base Register B */
#define VGA_PALETTE    (VGA_BASEADDR + 0x800) /* Color Palette */
 
#define VGA_STAT_AVMP 16
#define VGA_CTRL_VEN   0x00000001 /* Video Enable */
#define VGA_CTRL_HIE   0x00000002 /* HSync Interrupt Enable */
#define VGA_CTRL_PC    0x00000800 /* 8-bit Pseudo Color Enable*/
#define VGA_CTRL_CD8   0x00000000 /* Color Depth 8 */
#define VGA_CTRL_CD16  0x00000200 /* Color Depth 16 */
#define VGA_CTRL_CD24  0x00000400 /* Color Depth 24 */
#define VGA_CTRL_CD32  0x00000600 /* Color Depth 32 */
#define VGA_CTRL_VBL1  0x00000000 /* Burst Length 1 */
#define VGA_CTRL_VBL2  0x00000080 /* Burst Length 2 */
#define VGA_CTRL_VBL4  0x00000100 /* Burst Length 4 */
#define VGA_CTRL_VBL8  0x00000180 /* Burst Length 8 */
#define VGA_CTRL_VBSWE 0x00000020 /* Bank switch enable */
 
// Generate bits from orgfx_regs.h
 
/* ===================== */
/* Control register bits */
/* ===================== */
#define GFX_CTRL_CD8         0                               /* Color Depth 8              */
#define GFX_CTRL_CD16        (1 << GFX_CTRL_COLOR_DEPTH    ) /* Color Depth 16             */
#define GFX_CTRL_CD24        (2 << GFX_CTRL_COLOR_DEPTH    ) /* Color Depth 24             */ // Not supported!
#define GFX_CTRL_CD32        (3 << GFX_CTRL_COLOR_DEPTH    ) /* Color Depth 32             */
#define GFX_CTRL_CDMASK      (3 << GFX_CTRL_COLOR_DEPTH    ) /* All color depth bits       */
 
#define GFX_TEXTURE_ENABLE   (1 << GFX_CTRL_TEXTURE        ) /* Enable Texture Reads       */
#define GFX_BLEND_ENABLE     (1 << GFX_CTRL_BLENDING       ) /* Enable Alpha Blending      */
#define GFX_COLORKEY_ENABLE  (1 << GFX_CTRL_COLORKEY       ) /* Enable Colorkeying         */
#define GFX_CLIPPING_ENABLE  (1 << GFX_CTRL_CLIPPING       ) /* Enable Clipping/Scissoring */
#define GFX_ZBUFFER_ENABLE   (1 << GFX_CTRL_ZBUFFER        ) /* Enable depth buffer        */
 
#define GFX_RECT             (1 << GFX_CTRL_RECT           ) /* Put rect                   */
#define GFX_LINE             (1 << GFX_CTRL_LINE           ) /* Put line                   */
#define GFX_TRI              (1 << GFX_CTRL_TRI            ) /* Put triangle               */
 
#define GFX_CURVE            (1 << GFX_CTRL_CURVE          ) /* Put curve                  */
#define GFX_INTERP           (1 << GFX_CTRL_INTERP         ) /* Activate interpolation     */
#define GFX_INSIDE           (1 << GFX_CTRL_INSIDE         ) /* Bezier inside/outside      */
 
#define GFX_ACTIVE_POINT0    0                               /* Set the active point to p0 */
#define GFX_ACTIVE_POINT1    (1 << GFX_CTRL_ACTIVE_POINT   ) /* Set the active point to p1 */
#define GFX_ACTIVE_POINT2    (2 << GFX_CTRL_ACTIVE_POINT   ) /* Set the active point to p2 */
#define GFX_ACTIVE_POINTMASK (3 << GFX_CTRL_ACTIVE_POINT   )
#define GFX_FORWARD_POINT    (1 << GFX_CTRL_FORWARD_POINT  ) /* Forward the active point   */
#define GFX_TRANSFORM_POINT  (1 << GFX_CTRL_TRANSFORM_POINT) /* Transform the active point */
 
/* ==================== */
/* Status register bits */
/* ==================== */
#define GFX_BUSY        (1 << GFX_STAT_BUSY           ) /* Ready for op */
 
/* Register access macros */
#define REG8(add)  *((volatile unsigned char  *)(add))
#define REG16(add) *((volatile unsigned short *)(add))
#define REG32(add) *((volatile unsigned int   *)(add))
 
// Wait until req_spaces number of places in the instruction fifo are clear
inline void orgfx_wait(unsigned int reg_spaces)
{
  while( REG32(GFX_STATUS) & GFX_BUSY );
  //while( (REG32(GFX_STATUS) >> GFX_STAT_COUNT_OFFSET) + reg_spaces > GFX_INSTRUCTION_FIFO_SIZE);
}
 
unsigned int memory_base = GFX_VMEM;
struct orgfx_surface* target_surface = 0;
struct orgfx_surface* tex0_surface = 0;
struct orgfx_surface* zbuffer_surface = 0;
unsigned int gfx_control_reg_memory = 0;
 
// Forward or transform points?
unsigned int transformation_mode = GFX_FORWARD_POINT;
 
inline void orgfx_set_colordepth(unsigned char bpp);
 
void Set640x480_60(void)
{
    // Set horizontal timing register
    REG32(VGA_HTIM) = ((96 - 1) << 24) |
            ((48 - 1) << 16) |
            (640 - 1);
    // Set vertical timing register
    REG32(VGA_VTIM) = ((2 - 1) << 24) |
            ((31 - 1) << 16) |
            (480 - 1);
    // Set total vertical and horizontal lenghts
    REG32(VGA_HVLEN) = ((800 - 1) << 16) | (525 - 1);
 
    orgfx_wait(2);
    REG32(GFX_TARGET_SIZE_X) = 640;
    REG32(GFX_TARGET_SIZE_Y) = 480;
}
 
void Set800x600_60(void)
{
    // Set horizontal timing register
    REG32(VGA_HTIM) = ((128 - 1) << 24) |
            ((88 - 1) << 16) |
            (800 - 1);
    // Set vertical timing register
    REG32(VGA_VTIM) = ((4 - 1) << 24) |
            ((23 - 1) << 16) |
            (600 - 1);
    // Set total vertical and horizontal lenghts
    REG32(VGA_HVLEN) = ((1056 - 1) << 16) | (628 - 1);
 
    orgfx_wait(2);
    REG32(GFX_TARGET_SIZE_X) = 800;
    REG32(GFX_TARGET_SIZE_Y) = 600;
}
 
void Set1024x768_60(void)
{
    // Set horizontal timing register
    REG32(VGA_HTIM) = ((136 - 1) << 24) |
            ((160 - 1) << 16) |
            (1024 - 1);
    // Set vertical timing register
    REG32(VGA_VTIM) = ((6 - 1) << 24) |
            ((29 - 1) << 16) |
            (768 - 1);
    // Set total vertical and horizontal lenghts
    REG32(VGA_HVLEN) = ((1344 - 1) << 16) | (806 - 1);
 
    orgfx_wait(2);
    REG32(GFX_TARGET_SIZE_X) = 1024;
    REG32(GFX_TARGET_SIZE_Y) = 768;
}
 
void orgfx_init(unsigned int memoryArea)
{
    memory_base = memoryArea;
 
    // Reset VGA+GFX first
    REG32(VGA_CTRL) = 0;
 
    gfx_control_reg_memory = 0;
    orgfx_wait(2);
    REG32(GFX_CONTROL) = gfx_control_reg_memory;
 
    orgfx_vga_set_vbara(memory_base);
    orgfx_vga_set_vbarb(memory_base);
 
    REG32(GFX_TARGET_BASE) = memory_base;
}
 
void orgfx_vga_set_vbara(unsigned int addr)
{
    // Set base address for Video Base Register A
    REG32(VGA_VBARA) = addr;
}
 
void orgfx_vga_set_vbarb(unsigned int addr)
{
    // Set base address for Video Base Register B
    REG32(VGA_VBARB) = addr;
}
 
inline void orgfx_vga_bank_switch()
{
    orgfx_wait(GFX_INSTRUCTION_FIFO_SIZE);
    REG32(VGA_CTRL) |= VGA_CTRL_VBSWE;
}
 
inline unsigned int orgfx_vga_AVMP()
{
    // Get the active memory page bit
    unsigned int status_reg = REG32(VGA_STAT);
    status_reg = status_reg >> VGA_STAT_AVMP;
    return status_reg & 1;
}
 
void orgfx_set_colordepth(unsigned char bpp)
{
    unsigned int vga_bpp = 0, gfx_bpp = 0;
    switch(bpp)
    {
    case 8:  vga_bpp = VGA_CTRL_CD8;  gfx_bpp = GFX_CTRL_CD8;  break;
    case 16: vga_bpp = VGA_CTRL_CD16; gfx_bpp = GFX_CTRL_CD16; break;
        //      case 24: vga_bpp = VGA_CTRL_CD24; gfx_bpp = GFX_CTRL_CD24; break; // Unsupported by gfx
    case 32: vga_bpp = VGA_CTRL_CD32; gfx_bpp = GFX_CTRL_CD32; break;
    default: break;
    }
 
    // Activate VGA
    REG32(VGA_CTRL) |= VGA_CTRL_VEN | VGA_CTRL_VBL8 | vga_bpp;
    gfx_control_reg_memory &= ~GFX_CTRL_CDMASK;
    gfx_control_reg_memory |= gfx_bpp;
    orgfx_wait(1);
    REG32(GFX_CONTROL) = gfx_control_reg_memory;
}
 
void orgfx_vga_set_videomode(unsigned int width, unsigned int height, unsigned char bpp)
{
    if(width == 640 && height == 480)
        Set640x480_60();
    else if(width == 800 && height == 600)
        Set800x600_60();
    else if(width == 1024 && height == 768)
        Set1024x768_60();
    else // Default mode
        Set640x480_60();
 
    orgfx_set_colordepth(bpp);
}
 
struct orgfx_surface orgfx_init_surface(unsigned int width, unsigned int height)
{
    struct orgfx_surface surface;
    surface.addr = memory_base;
    surface.w = width;
    surface.h = height;
    memory_base += (width << 1) * height; // TODO: Only true for 16 bit surfaces!
    return surface;
}
 
void orgfx_bind_rendertarget(struct orgfx_surface *surface)
{
    target_surface = surface;
    orgfx_wait(3);
    REG32(GFX_TARGET_BASE) = surface->addr;
    REG32(GFX_TARGET_SIZE_X) = surface->w;
    REG32(GFX_TARGET_SIZE_Y) = surface->h;
    // Clear clip rect
    orgfx_cliprect(0,0,surface->w,surface->h);
}
 
void orgfx_enable_zbuffer(unsigned int enable)
{
    if(enable)
        gfx_control_reg_memory |= GFX_ZBUFFER_ENABLE;
    else
        gfx_control_reg_memory &= ~GFX_ZBUFFER_ENABLE;
 
    orgfx_wait(1);
    REG32(GFX_CONTROL) = gfx_control_reg_memory;
}
 
void orgfx_bind_zbuffer(struct orgfx_surface *surface)
{
    zbuffer_surface = surface;
    orgfx_wait(1);
    REG32(GFX_ZBUFFER_BASE) = surface->addr;
}
 
void orgfx_clear_zbuffer()
{
    int y, x;
    for(y = 0; y < zbuffer_surface->h; ++y)
    {
        for(x = 0; x < zbuffer_surface->w; x+=2)
        {
            int addr = (y*zbuffer_surface->w + x)*2; // TODO: only works for 16bits
            REG32(zbuffer_surface->addr+addr) = 0x80008000;
        }
    }
}
 
void orgfx_enable_cliprect(unsigned int enable)
{
    if(enable)
        gfx_control_reg_memory |= GFX_CLIPPING_ENABLE;
    else
        gfx_control_reg_memory &= ~GFX_CLIPPING_ENABLE;
 
    orgfx_wait(1);
    REG32(GFX_CONTROL) = gfx_control_reg_memory;
}
 
void orgfx_cliprect(unsigned int x0, unsigned int y0, unsigned int x1, unsigned int y1)
{
    orgfx_wait(4);
    REG32(GFX_CLIP_PIXEL0_X) = x0;
    REG32(GFX_CLIP_PIXEL0_Y) = y0;
    REG32(GFX_CLIP_PIXEL1_X) = x1;
    REG32(GFX_CLIP_PIXEL1_Y) = y1;
}
 
void orgfx_srcrect(unsigned int x0, unsigned int y0, unsigned int x1, unsigned int y1)
{
    orgfx_wait(4);
    REG32(GFX_SRC_PIXEL0_X) = x0;
    REG32(GFX_SRC_PIXEL0_Y) = y0;
    REG32(GFX_SRC_PIXEL1_X) = x1;
    REG32(GFX_SRC_PIXEL1_Y) = y1;
}
 
void orgfx_init_src()
{
    if((gfx_control_reg_memory & GFX_TEXTURE_ENABLE) && tex0_surface)
        orgfx_srcrect(0, 0, tex0_surface->w, tex0_surface->h);
    else if(target_surface)
        orgfx_srcrect(0, 0, target_surface->w, target_surface->h);
}
 
void orgfx_set_pixel(int x, int y, unsigned int color)
{
    if(x >= 0 && y >= 0)
    {
        int addr = (y*target_surface->w + x)*2; // TODO: only works for 16bits
        REG32(target_surface->addr+addr) = color;
    }
}
 
// Copies a buffer into the current render target
void orgfx_memcpy(unsigned int mem[], unsigned int size)
{
    unsigned int i;
    for(i=0; i < size; ++i)
        REG32(target_surface->addr+i*4) = mem[i];
}
 
void orgfx_set_color(unsigned int color)
{
    orgfx_wait(1);
    REG32(GFX_COLOR0) = color;
}
 
 
void orgfx_set_colors(unsigned int color0, unsigned int color1, unsigned int color2)
{
    orgfx_wait(3);
    REG32(GFX_COLOR0) = color0;
    REG32(GFX_COLOR1) = color1;
    REG32(GFX_COLOR2) = color2;
}
 
void orgfx_rect(int x0, int y0, int x1, int y1)
{
    orgfx_wait(7);
    REG32(GFX_DEST_PIXEL_X) = x0;
    REG32(GFX_DEST_PIXEL_Y) = y0;
    REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT0 | transformation_mode;
    REG32(GFX_DEST_PIXEL_X) = x1;
    REG32(GFX_DEST_PIXEL_Y) = y1;
    REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT1 | transformation_mode;
    REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_RECT;
}
 
void orgfx_line(int x0, int y0, int x1, int y1)
{
    orgfx_line3d(x0, y0, 0, x1, y1, 0);
}
 
void orgfx_triangle(int x0, int y0,
                     int x1, int y1,
                     int x2, int y2,
                     unsigned int interpolate)
{
    orgfx_triangle3d(x0, y0, 0, x1, y1, 0, x2, y2, 0, interpolate);
}
 
void orgfx_curve(int x0, int y0,
                  int x1, int y1,
                  int x2, int y2,
                  unsigned int inside)
{
    orgfx_wait(14);
    REG32(GFX_DEST_PIXEL_Z) = 0; // Set all points depth value to zero
 
    REG32(GFX_DEST_PIXEL_X) = x0;
    REG32(GFX_DEST_PIXEL_Y) = y0;
    REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT0 | transformation_mode;
    REG32(GFX_DEST_PIXEL_X) = x1;
    REG32(GFX_DEST_PIXEL_Y) = y1;
    REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT1 | transformation_mode;
    REG32(GFX_DEST_PIXEL_X) = x2;
    REG32(GFX_DEST_PIXEL_Y) = y2;
    REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT2 | transformation_mode;
 
    if(inside)
        gfx_control_reg_memory |= GFX_INSIDE;
    else
        gfx_control_reg_memory &= ~GFX_INSIDE;
 
    REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_CURVE | GFX_TRI | GFX_INTERP;
}
 
void orgfx_triangle3d(int x0, int y0, int z0,
                       int x1, int y1, int z1,
                       int x2, int y2, int z2,
                       unsigned int interpolate)
{
    orgfx_wait(13);
    REG32(GFX_DEST_PIXEL_X) = x0;
    REG32(GFX_DEST_PIXEL_Y) = y0;
    REG32(GFX_DEST_PIXEL_Z) = z0;
    REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT0 | transformation_mode;
    REG32(GFX_DEST_PIXEL_X) = x1;
    REG32(GFX_DEST_PIXEL_Y) = y1;
    REG32(GFX_DEST_PIXEL_Z) = z1;
    REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT1 | transformation_mode;
    REG32(GFX_DEST_PIXEL_X) = x2;
    REG32(GFX_DEST_PIXEL_Y) = y2;
    REG32(GFX_DEST_PIXEL_Z) = z2;
    REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT2 | transformation_mode;
 
    if(interpolate)
        REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_TRI | GFX_INTERP;
    else
        REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_TRI;
}
 
void orgfx_line3d(int x0, int y0, int z0, int x1, int y1, int z1)
{
    orgfx_wait(9);
    REG32(GFX_DEST_PIXEL_X) = x0;
    REG32(GFX_DEST_PIXEL_Y) = y0;
    REG32(GFX_DEST_PIXEL_Z) = z0;
    REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT0 | transformation_mode;
    REG32(GFX_DEST_PIXEL_X) = x1;
    REG32(GFX_DEST_PIXEL_Y) = y1;
    REG32(GFX_DEST_PIXEL_Z) = z1;
    REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_ACTIVE_POINT1 | transformation_mode;
    REG32(GFX_CONTROL) = gfx_control_reg_memory | GFX_LINE;
}
 
void orgfx_uv(unsigned int u0, unsigned int v0,
               unsigned int u1, unsigned int v1,
               unsigned int u2, unsigned int v2)
{
    orgfx_wait(6);
    REG32(GFX_U0) = u0;
    REG32(GFX_V0) = v0;
    REG32(GFX_U1) = u1;
    REG32(GFX_V1) = v1;
    REG32(GFX_U2) = u2;
    REG32(GFX_V2) = v2;
}
 
void orgfx_enable_tex0(unsigned int enable)
{
    orgfx_wait(1);
    if(enable)
    {
        gfx_control_reg_memory   |= GFX_TEXTURE_ENABLE;
        REG32(GFX_CONTROL) = gfx_control_reg_memory;
    }
    else
    {
        gfx_control_reg_memory &= ~GFX_TEXTURE_ENABLE;
        REG32(GFX_CONTROL) = gfx_control_reg_memory;
    }
    orgfx_init_src();
}
 
void orgfx_bind_tex0(struct orgfx_surface* surface)
{
    orgfx_wait(3);
    tex0_surface = surface;
    REG32(GFX_TEX0_BASE) = surface->addr;
    REG32(GFX_TEX0_SIZE_X) = surface->w;
    REG32(GFX_TEX0_SIZE_Y) = surface->h;
    orgfx_init_src();
}
 
void orgfx_enable_alpha(unsigned int enable)
{
    orgfx_wait(1);
    if(enable)
        gfx_control_reg_memory |= GFX_BLEND_ENABLE;
    else
        gfx_control_reg_memory &= ~GFX_BLEND_ENABLE;
 
    REG32(GFX_CONTROL) = gfx_control_reg_memory;
}
 
void orgfx_set_alpha(unsigned int alpha)
{
    orgfx_wait(1);
    REG32(GFX_ALPHA) = alpha;
}
 
void orgfx_enable_colorkey(unsigned int enable)
{
    orgfx_wait(1);
    if(enable)
        gfx_control_reg_memory |= GFX_COLORKEY_ENABLE;
    else
        gfx_control_reg_memory &= ~GFX_COLORKEY_ENABLE;
 
    REG32(GFX_CONTROL) = gfx_control_reg_memory;
}
 
void orgfx_set_colorkey(unsigned int colorkey)
{
    orgfx_wait(1);
    REG32(GFX_COLORKEY) = colorkey;
}
 
void orgfx_enable_transform(unsigned int enable)
{
    if(enable)
        transformation_mode = GFX_TRANSFORM_POINT;
    else
        transformation_mode = GFX_FORWARD_POINT;
}
 
void orgfx_set_transformation_matrix(int aa, int ab, int ac, int tx,
                                      int ba, int bb, int bc, int ty,
                                      int ca, int cb, int cc, int tz)
{
    orgfx_wait(12);
    REG32(GFX_AA) = aa;
    REG32(GFX_AB) = ab;
    REG32(GFX_AC) = ac;
    REG32(GFX_TX) = tx;
    REG32(GFX_BA) = ba;
    REG32(GFX_BB) = bb;
    REG32(GFX_BC) = bc;
    REG32(GFX_TY) = ty;
    REG32(GFX_CA) = ca;
    REG32(GFX_CB) = cb;
    REG32(GFX_CC) = cc;
    REG32(GFX_TZ) = tz;
}
 

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Subversion Repositories orsoc_graphics_accelerator

[/] [orsoc_graphics_accelerator/] [trunk/] [sw/] [drivers/] [gfx/] [bare/] [orgfx.c] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	maiden	`/*`
2			`Bare metal OpenCores GFX IP driver for Wishbone bus.`
3
4			`Anton Fosselius, Per Lenander 2012`
5			`*/`
6
7			`#include "orgfx.h"`
8			`#include "orgfx_regs.h"`
9
10			`#define GFX_STAT_COUNT_OFFSET 16`
11			`#define GFX_INSTRUCTION_FIFO_SIZE 1024`
12
13			`#define SUBPIXEL_WIDTH 16`
14
15			`/* VGA defines */`
16			`#define VGA_BASEADDR 0x97000000 /* Bus Adress to VGA */`
17
18			`#define VGA_CTRL (VGA_BASEADDR + 0x000) /* Control Register */`
19			`#define VGA_STAT (VGA_BASEADDR + 0x004) /* Status Register */`
20			`#define VGA_HTIM (VGA_BASEADDR + 0x008) /* Horisontal Timing Register */`
21			`#define VGA_VTIM (VGA_BASEADDR + 0x00c) /* Vertical Timing Register */`
22			`#define VGA_HVLEN (VGA_BASEADDR + 0x010) /* Horisontal and Vertical Total Screen Size, (Screen size + Blank) */`
23			`#define VGA_VBARA (VGA_BASEADDR + 0x014) /* Adress to Video Base Register A */`
24			`#define VGA_VBARB (VGA_BASEADDR + 0x018) /* Adress to Video Base Register B */`
25			`#define VGA_PALETTE (VGA_BASEADDR + 0x800) /* Color Palette */`
26
27			`#define VGA_STAT_AVMP 16`
28			`#define VGA_CTRL_VEN 0x00000001 /* Video Enable */`
29			`#define VGA_CTRL_HIE 0x00000002 /* HSync Interrupt Enable */`
30			`#define VGA_CTRL_PC 0x00000800 /* 8-bit Pseudo Color Enable*/`
31			`#define VGA_CTRL_CD8 0x00000000 /* Color Depth 8 */`
32			`#define VGA_CTRL_CD16 0x00000200 /* Color Depth 16 */`
33			`#define VGA_CTRL_CD24 0x00000400 /* Color Depth 24 */`
34			`#define VGA_CTRL_CD32 0x00000600 /* Color Depth 32 */`
35			`#define VGA_CTRL_VBL1 0x00000000 /* Burst Length 1 */`
36			`#define VGA_CTRL_VBL2 0x00000080 /* Burst Length 2 */`
37			`#define VGA_CTRL_VBL4 0x00000100 /* Burst Length 4 */`
38			`#define VGA_CTRL_VBL8 0x00000180 /* Burst Length 8 */`
39			`#define VGA_CTRL_VBSWE 0x00000020 /* Bank switch enable */`
40
41			`// Generate bits from orgfx_regs.h`
42
43			`/* ===================== */`
44			`/* Control register bits */`
45			`/* ===================== */`
46			`#define GFX_CTRL_CD8 0 /* Color Depth 8 */`
47			`#define GFX_CTRL_CD16 (1 << GFX_CTRL_COLOR_DEPTH ) /* Color Depth 16 */`
48			`#define GFX_CTRL_CD24 (2 << GFX_CTRL_COLOR_DEPTH ) /* Color Depth 24 */ // Not supported!`
49			`#define GFX_CTRL_CD32 (3 << GFX_CTRL_COLOR_DEPTH ) /* Color Depth 32 */`
50			`#define GFX_CTRL_CDMASK (3 << GFX_CTRL_COLOR_DEPTH ) /* All color depth bits */`
51
52			`#define GFX_TEXTURE_ENABLE (1 << GFX_CTRL_TEXTURE ) /* Enable Texture Reads */`
53			`#define GFX_BLEND_ENABLE (1 << GFX_CTRL_BLENDING ) /* Enable Alpha Blending */`
54			`#define GFX_COLORKEY_ENABLE (1 << GFX_CTRL_COLORKEY ) /* Enable Colorkeying */`
55			`#define GFX_CLIPPING_ENABLE (1 << GFX_CTRL_CLIPPING ) /* Enable Clipping/Scissoring */`
56			`#define GFX_ZBUFFER_ENABLE (1 << GFX_CTRL_ZBUFFER ) /* Enable depth buffer */`
57
58			`#define GFX_RECT (1 << GFX_CTRL_RECT ) /* Put rect */`
59			`#define GFX_LINE (1 << GFX_CTRL_LINE ) /* Put line */`
60			`#define GFX_TRI (1 << GFX_CTRL_TRI ) /* Put triangle */`
61
62			`#define GFX_CURVE (1 << GFX_CTRL_CURVE ) /* Put curve */`
63			`#define GFX_INTERP (1 << GFX_CTRL_INTERP ) /* Activate interpolation */`
64			`#define GFX_INSIDE (1 << GFX_CTRL_INSIDE ) /* Bezier inside/outside */`
65
66			`#define GFX_ACTIVE_POINT0 0 /* Set the active point to p0 */`
67			`#define GFX_ACTIVE_POINT1 (1 << GFX_CTRL_ACTIVE_POINT ) /* Set the active point to p1 */`
68			`#define GFX_ACTIVE_POINT2 (2 << GFX_CTRL_ACTIVE_POINT ) /* Set the active point to p2 */`
69			`#define GFX_ACTIVE_POINTMASK (3 << GFX_CTRL_ACTIVE_POINT )`
70			`#define GFX_FORWARD_POINT (1 << GFX_CTRL_FORWARD_POINT ) /* Forward the active point */`
71			`#define GFX_TRANSFORM_POINT (1 << GFX_CTRL_TRANSFORM_POINT) /* Transform the active point */`
72
73			`/* ==================== */`
74			`/* Status register bits */`
75			`/* ==================== */`
76			`#define GFX_BUSY (1 << GFX_STAT_BUSY ) /* Ready for op */`
77
78			`/* Register access macros */`
79			`#define REG8(add) ((volatile unsigned char )(add))`
80			`#define REG16(add) ((volatile unsigned short )(add))`
81			`#define REG32(add) ((volatile unsigned int )(add))`
82
83			`// Wait until req_spaces number of places in the instruction fifo are clear`
84			`inline void orgfx_wait(unsigned int reg_spaces)`
85			`{`
86			`while( REG32(GFX_STATUS) & GFX_BUSY );`
87			`//while( (REG32(GFX_STATUS) >> GFX_STAT_COUNT_OFFSET) + reg_spaces > GFX_INSTRUCTION_FIFO_SIZE);`
88			`}`
89
90			`unsigned int memory_base = GFX_VMEM;`
91			`struct orgfx_surface* target_surface = 0;`
92			`struct orgfx_surface* tex0_surface = 0;`
93			`struct orgfx_surface* zbuffer_surface = 0;`
94			`unsigned int gfx_control_reg_memory = 0;`
95
96			`// Forward or transform points?`
97			`unsigned int transformation_mode = GFX_FORWARD_POINT;`
98
99			`inline void orgfx_set_colordepth(unsigned char bpp);`
100
101			`void Set640x480_60(void)`
102			`{`
103			`// Set horizontal timing register`
104			`REG32(VGA_HTIM) = ((96 - 1) << 24) \|`
105			`((48 - 1) << 16) \|`
106			`(640 - 1);`
107			`// Set vertical timing register`
108			`REG32(VGA_VTIM) = ((2 - 1) << 24) \|`
109			`((31 - 1) << 16) \|`
110			`(480 - 1);`
111			`// Set total vertical and horizontal lenghts`
112			`REG32(VGA_HVLEN) = ((800 - 1) << 16) \| (525 - 1);`
113
114			`orgfx_wait(2);`
115			`REG32(GFX_TARGET_SIZE_X) = 640;`
116			`REG32(GFX_TARGET_SIZE_Y) = 480;`
117			`}`
118
119			`void Set800x600_60(void)`
120			`{`
121			`// Set horizontal timing register`
122			`REG32(VGA_HTIM) = ((128 - 1) << 24) \|`
123			`((88 - 1) << 16) \|`
124			`(800 - 1);`
125			`// Set vertical timing register`
126			`REG32(VGA_VTIM) = ((4 - 1) << 24) \|`
127			`((23 - 1) << 16) \|`
128			`(600 - 1);`
129			`// Set total vertical and horizontal lenghts`
130			`REG32(VGA_HVLEN) = ((1056 - 1) << 16) \| (628 - 1);`
131
132			`orgfx_wait(2);`
133			`REG32(GFX_TARGET_SIZE_X) = 800;`
134			`REG32(GFX_TARGET_SIZE_Y) = 600;`
135			`}`
136
137			`void Set1024x768_60(void)`
138			`{`
139			`// Set horizontal timing register`
140			`REG32(VGA_HTIM) = ((136 - 1) << 24) \|`
141			`((160 - 1) << 16) \|`
142			`(1024 - 1);`
143			`// Set vertical timing register`
144			`REG32(VGA_VTIM) = ((6 - 1) << 24) \|`
145			`((29 - 1) << 16) \|`
146			`(768 - 1);`
147			`// Set total vertical and horizontal lenghts`
148			`REG32(VGA_HVLEN) = ((1344 - 1) << 16) \| (806 - 1);`
149
150			`orgfx_wait(2);`
151			`REG32(GFX_TARGET_SIZE_X) = 1024;`
152			`REG32(GFX_TARGET_SIZE_Y) = 768;`
153			`}`
154
155			`void orgfx_init(unsigned int memoryArea)`
156			`{`
157			`memory_base = memoryArea;`
158
159			`// Reset VGA+GFX first`
160			`REG32(VGA_CTRL) = 0;`
161
162			`gfx_control_reg_memory = 0;`
163			`orgfx_wait(2);`
164			`REG32(GFX_CONTROL) = gfx_control_reg_memory;`
165
166			`orgfx_vga_set_vbara(memory_base);`
167			`orgfx_vga_set_vbarb(memory_base);`
168
169			`REG32(GFX_TARGET_BASE) = memory_base;`
170			`}`
171
172			`void orgfx_vga_set_vbara(unsigned int addr)`
173			`{`
174			`// Set base address for Video Base Register A`
175			`REG32(VGA_VBARA) = addr;`
176			`}`
177
178			`void orgfx_vga_set_vbarb(unsigned int addr)`
179			`{`
180			`// Set base address for Video Base Register B`
181			`REG32(VGA_VBARB) = addr;`
182			`}`
183
184			`inline void orgfx_vga_bank_switch()`
185			`{`
186			`orgfx_wait(GFX_INSTRUCTION_FIFO_SIZE);`
187			`REG32(VGA_CTRL) \|= VGA_CTRL_VBSWE;`
188			`}`
189
190			`inline unsigned int orgfx_vga_AVMP()`
191			`{`
192			`// Get the active memory page bit`
193			`unsigned int status_reg = REG32(VGA_STAT);`
194			`status_reg = status_reg >> VGA_STAT_AVMP;`
195			`return status_reg & 1;`
196			`}`
197
198			`void orgfx_set_colordepth(unsigned char bpp)`
199			`{`
200			`unsigned int vga_bpp = 0, gfx_bpp = 0;`
201			`switch(bpp)`
202			`{`
203			`case 8: vga_bpp = VGA_CTRL_CD8; gfx_bpp = GFX_CTRL_CD8; break;`
204			`case 16: vga_bpp = VGA_CTRL_CD16; gfx_bpp = GFX_CTRL_CD16; break;`
205			`// case 24: vga_bpp = VGA_CTRL_CD24; gfx_bpp = GFX_CTRL_CD24; break; // Unsupported by gfx`
206			`case 32: vga_bpp = VGA_CTRL_CD32; gfx_bpp = GFX_CTRL_CD32; break;`
207			`default: break;`
208			`}`
209
210			`// Activate VGA`
211			`REG32(VGA_CTRL) \|= VGA_CTRL_VEN \| VGA_CTRL_VBL8 \| vga_bpp;`
212			`gfx_control_reg_memory &= ~GFX_CTRL_CDMASK;`
213			`gfx_control_reg_memory \|= gfx_bpp;`
214			`orgfx_wait(1);`
215			`REG32(GFX_CONTROL) = gfx_control_reg_memory;`
216			`}`
217
218			`void orgfx_vga_set_videomode(unsigned int width, unsigned int height, unsigned char bpp)`
219			`{`
220			`if(width == 640 && height == 480)`
221			`Set640x480_60();`
222			`else if(width == 800 && height == 600)`
223			`Set800x600_60();`
224			`else if(width == 1024 && height == 768)`
225			`Set1024x768_60();`
226			`else // Default mode`
227			`Set640x480_60();`
228
229			`orgfx_set_colordepth(bpp);`
230			`}`
231
232			`struct orgfx_surface orgfx_init_surface(unsigned int width, unsigned int height)`
233			`{`
234			`struct orgfx_surface surface;`
235			`surface.addr = memory_base;`
236			`surface.w = width;`
237			`surface.h = height;`
238			`memory_base += (width << 1) * height; // TODO: Only true for 16 bit surfaces!`
239			`return surface;`
240			`}`
241
242			`void orgfx_bind_rendertarget(struct orgfx_surface *surface)`
243			`{`
244			`target_surface = surface;`
245			`orgfx_wait(3);`
246			`REG32(GFX_TARGET_BASE) = surface->addr;`
247			`REG32(GFX_TARGET_SIZE_X) = surface->w;`
248			`REG32(GFX_TARGET_SIZE_Y) = surface->h;`
249			`// Clear clip rect`
250			`orgfx_cliprect(0,0,surface->w,surface->h);`
251			`}`
252
253			`void orgfx_enable_zbuffer(unsigned int enable)`
254			`{`
255			`if(enable)`
256			`gfx_control_reg_memory \|= GFX_ZBUFFER_ENABLE;`
257			`else`
258			`gfx_control_reg_memory &= ~GFX_ZBUFFER_ENABLE;`
259
260			`orgfx_wait(1);`
261			`REG32(GFX_CONTROL) = gfx_control_reg_memory;`
262			`}`
263
264			`void orgfx_bind_zbuffer(struct orgfx_surface *surface)`
265			`{`
266			`zbuffer_surface = surface;`
267			`orgfx_wait(1);`
268			`REG32(GFX_ZBUFFER_BASE) = surface->addr;`
269			`}`
270
271			`void orgfx_clear_zbuffer()`
272			`{`
273			`int y, x;`
274			`for(y = 0; y < zbuffer_surface->h; ++y)`
275			`{`
276			`for(x = 0; x < zbuffer_surface->w; x+=2)`
277			`{`
278			`int addr = (yzbuffer_surface->w + x)2; // TODO: only works for 16bits`
279			`REG32(zbuffer_surface->addr+addr) = 0x80008000;`
280			`}`
281			`}`
282			`}`
283
284			`void orgfx_enable_cliprect(unsigned int enable)`
285			`{`
286			`if(enable)`
287			`gfx_control_reg_memory \|= GFX_CLIPPING_ENABLE;`
288			`else`
289			`gfx_control_reg_memory &= ~GFX_CLIPPING_ENABLE;`
290
291			`orgfx_wait(1);`
292			`REG32(GFX_CONTROL) = gfx_control_reg_memory;`
293			`}`
294
295			`void orgfx_cliprect(unsigned int x0, unsigned int y0, unsigned int x1, unsigned int y1)`
296			`{`
297			`orgfx_wait(4);`
298			`REG32(GFX_CLIP_PIXEL0_X) = x0;`
299			`REG32(GFX_CLIP_PIXEL0_Y) = y0;`
300			`REG32(GFX_CLIP_PIXEL1_X) = x1;`
301			`REG32(GFX_CLIP_PIXEL1_Y) = y1;`
302			`}`
303
304			`void orgfx_srcrect(unsigned int x0, unsigned int y0, unsigned int x1, unsigned int y1)`
305			`{`
306			`orgfx_wait(4);`
307			`REG32(GFX_SRC_PIXEL0_X) = x0;`
308			`REG32(GFX_SRC_PIXEL0_Y) = y0;`
309			`REG32(GFX_SRC_PIXEL1_X) = x1;`
310			`REG32(GFX_SRC_PIXEL1_Y) = y1;`
311			`}`
312
313			`void orgfx_init_src()`
314			`{`
315			`if((gfx_control_reg_memory & GFX_TEXTURE_ENABLE) && tex0_surface)`
316			`orgfx_srcrect(0, 0, tex0_surface->w, tex0_surface->h);`
317			`else if(target_surface)`
318			`orgfx_srcrect(0, 0, target_surface->w, target_surface->h);`
319			`}`
320
321			`void orgfx_set_pixel(int x, int y, unsigned int color)`
322			`{`
323			`if(x >= 0 && y >= 0)`
324			`{`
325			`int addr = (ytarget_surface->w + x)2; // TODO: only works for 16bits`
326			`REG32(target_surface->addr+addr) = color;`
327			`}`
328			`}`
329
330			`// Copies a buffer into the current render target`
331			`void orgfx_memcpy(unsigned int mem[], unsigned int size)`
332			`{`
333			`unsigned int i;`
334			`for(i=0; i < size; ++i)`
335			`REG32(target_surface->addr+i*4) = mem[i];`
336			`}`
337
338			`void orgfx_set_color(unsigned int color)`
339			`{`
340			`orgfx_wait(1);`
341			`REG32(GFX_COLOR0) = color;`
342			`}`
343
344
345			`void orgfx_set_colors(unsigned int color0, unsigned int color1, unsigned int color2)`
346			`{`
347			`orgfx_wait(3);`
348			`REG32(GFX_COLOR0) = color0;`
349			`REG32(GFX_COLOR1) = color1;`
350			`REG32(GFX_COLOR2) = color2;`
351			`}`
352
353			`void orgfx_rect(int x0, int y0, int x1, int y1)`
354			`{`
355			`orgfx_wait(7);`
356			`REG32(GFX_DEST_PIXEL_X) = x0;`
357			`REG32(GFX_DEST_PIXEL_Y) = y0;`
358			`REG32(GFX_CONTROL) = gfx_control_reg_memory \| GFX_ACTIVE_POINT0 \| transformation_mode;`
359			`REG32(GFX_DEST_PIXEL_X) = x1;`
360			`REG32(GFX_DEST_PIXEL_Y) = y1;`
361			`REG32(GFX_CONTROL) = gfx_control_reg_memory \| GFX_ACTIVE_POINT1 \| transformation_mode;`
362			`REG32(GFX_CONTROL) = gfx_control_reg_memory \| GFX_RECT;`
363			`}`
364
365			`void orgfx_line(int x0, int y0, int x1, int y1)`
366			`{`
367			`orgfx_line3d(x0, y0, 0, x1, y1, 0);`
368			`}`
369
370			`void orgfx_triangle(int x0, int y0,`
371			`int x1, int y1,`
372			`int x2, int y2,`
373			`unsigned int interpolate)`
374			`{`
375			`orgfx_triangle3d(x0, y0, 0, x1, y1, 0, x2, y2, 0, interpolate);`
376			`}`
377
378			`void orgfx_curve(int x0, int y0,`
379			`int x1, int y1,`
380			`int x2, int y2,`
381			`unsigned int inside)`
382			`{`
383			`orgfx_wait(14);`
384			`REG32(GFX_DEST_PIXEL_Z) = 0; // Set all points depth value to zero`
385
386			`REG32(GFX_DEST_PIXEL_X) = x0;`
387			`REG32(GFX_DEST_PIXEL_Y) = y0;`
388			`REG32(GFX_CONTROL) = gfx_control_reg_memory \| GFX_ACTIVE_POINT0 \| transformation_mode;`
389			`REG32(GFX_DEST_PIXEL_X) = x1;`
390			`REG32(GFX_DEST_PIXEL_Y) = y1;`
391			`REG32(GFX_CONTROL) = gfx_control_reg_memory \| GFX_ACTIVE_POINT1 \| transformation_mode;`
392			`REG32(GFX_DEST_PIXEL_X) = x2;`
393			`REG32(GFX_DEST_PIXEL_Y) = y2;`
394			`REG32(GFX_CONTROL) = gfx_control_reg_memory \| GFX_ACTIVE_POINT2 \| transformation_mode;`
395
396			`if(inside)`
397			`gfx_control_reg_memory \|= GFX_INSIDE;`
398			`else`
399			`gfx_control_reg_memory &= ~GFX_INSIDE;`
400
401			`REG32(GFX_CONTROL) = gfx_control_reg_memory \| GFX_CURVE \| GFX_TRI \| GFX_INTERP;`
402			`}`
403
404			`void orgfx_triangle3d(int x0, int y0, int z0,`
405			`int x1, int y1, int z1,`
406			`int x2, int y2, int z2,`
407			`unsigned int interpolate)`
408			`{`
409			`orgfx_wait(13);`
410			`REG32(GFX_DEST_PIXEL_X) = x0;`
411			`REG32(GFX_DEST_PIXEL_Y) = y0;`
412			`REG32(GFX_DEST_PIXEL_Z) = z0;`
413			`REG32(GFX_CONTROL) = gfx_control_reg_memory \| GFX_ACTIVE_POINT0 \| transformation_mode;`
414			`REG32(GFX_DEST_PIXEL_X) = x1;`
415			`REG32(GFX_DEST_PIXEL_Y) = y1;`
416			`REG32(GFX_DEST_PIXEL_Z) = z1;`
417			`REG32(GFX_CONTROL) = gfx_control_reg_memory \| GFX_ACTIVE_POINT1 \| transformation_mode;`
418			`REG32(GFX_DEST_PIXEL_X) = x2;`
419			`REG32(GFX_DEST_PIXEL_Y) = y2;`
420			`REG32(GFX_DEST_PIXEL_Z) = z2;`
421			`REG32(GFX_CONTROL) = gfx_control_reg_memory \| GFX_ACTIVE_POINT2 \| transformation_mode;`
422
423			`if(interpolate)`
424			`REG32(GFX_CONTROL) = gfx_control_reg_memory \| GFX_TRI \| GFX_INTERP;`
425			`else`
426			`REG32(GFX_CONTROL) = gfx_control_reg_memory \| GFX_TRI;`
427			`}`
428
429			`void orgfx_line3d(int x0, int y0, int z0, int x1, int y1, int z1)`
430			`{`
431			`orgfx_wait(9);`
432			`REG32(GFX_DEST_PIXEL_X) = x0;`
433			`REG32(GFX_DEST_PIXEL_Y) = y0;`
434			`REG32(GFX_DEST_PIXEL_Z) = z0;`
435			`REG32(GFX_CONTROL) = gfx_control_reg_memory \| GFX_ACTIVE_POINT0 \| transformation_mode;`
436			`REG32(GFX_DEST_PIXEL_X) = x1;`
437			`REG32(GFX_DEST_PIXEL_Y) = y1;`
438			`REG32(GFX_DEST_PIXEL_Z) = z1;`
439			`REG32(GFX_CONTROL) = gfx_control_reg_memory \| GFX_ACTIVE_POINT1 \| transformation_mode;`
440			`REG32(GFX_CONTROL) = gfx_control_reg_memory \| GFX_LINE;`
441			`}`
442
443			`void orgfx_uv(unsigned int u0, unsigned int v0,`
444			`unsigned int u1, unsigned int v1,`
445			`unsigned int u2, unsigned int v2)`
446			`{`
447			`orgfx_wait(6);`
448			`REG32(GFX_U0) = u0;`
449			`REG32(GFX_V0) = v0;`
450			`REG32(GFX_U1) = u1;`
451			`REG32(GFX_V1) = v1;`
452			`REG32(GFX_U2) = u2;`
453			`REG32(GFX_V2) = v2;`
454			`}`
455
456			`void orgfx_enable_tex0(unsigned int enable)`
457			`{`
458			`orgfx_wait(1);`
459			`if(enable)`
460			`{`
461			`gfx_control_reg_memory \|= GFX_TEXTURE_ENABLE;`
462			`REG32(GFX_CONTROL) = gfx_control_reg_memory;`
463			`}`
464			`else`
465			`{`
466			`gfx_control_reg_memory &= ~GFX_TEXTURE_ENABLE;`
467			`REG32(GFX_CONTROL) = gfx_control_reg_memory;`
468			`}`
469			`orgfx_init_src();`
470			`}`
471
472			`void orgfx_bind_tex0(struct orgfx_surface* surface)`
473			`{`
474			`orgfx_wait(3);`
475			`tex0_surface = surface;`
476			`REG32(GFX_TEX0_BASE) = surface->addr;`
477			`REG32(GFX_TEX0_SIZE_X) = surface->w;`
478			`REG32(GFX_TEX0_SIZE_Y) = surface->h;`
479			`orgfx_init_src();`
480			`}`
481
482			`void orgfx_enable_alpha(unsigned int enable)`
483			`{`
484			`orgfx_wait(1);`
485			`if(enable)`
486			`gfx_control_reg_memory \|= GFX_BLEND_ENABLE;`
487			`else`
488			`gfx_control_reg_memory &= ~GFX_BLEND_ENABLE;`
489
490			`REG32(GFX_CONTROL) = gfx_control_reg_memory;`
491			`}`
492
493			`void orgfx_set_alpha(unsigned int alpha)`
494			`{`
495			`orgfx_wait(1);`
496			`REG32(GFX_ALPHA) = alpha;`
497			`}`
498
499			`void orgfx_enable_colorkey(unsigned int enable)`
500			`{`
501			`orgfx_wait(1);`
502			`if(enable)`
503			`gfx_control_reg_memory \|= GFX_COLORKEY_ENABLE;`
504			`else`
505			`gfx_control_reg_memory &= ~GFX_COLORKEY_ENABLE;`
506
507			`REG32(GFX_CONTROL) = gfx_control_reg_memory;`
508			`}`
509
510			`void orgfx_set_colorkey(unsigned int colorkey)`
511			`{`
512			`orgfx_wait(1);`
513			`REG32(GFX_COLORKEY) = colorkey;`
514			`}`
515
516			`void orgfx_enable_transform(unsigned int enable)`
517			`{`
518			`if(enable)`
519			`transformation_mode = GFX_TRANSFORM_POINT;`
520			`else`
521			`transformation_mode = GFX_FORWARD_POINT;`
522			`}`
523
524			`void orgfx_set_transformation_matrix(int aa, int ab, int ac, int tx,`
525			`int ba, int bb, int bc, int ty,`
526			`int ca, int cb, int cc, int tz)`
527			`{`
528			`orgfx_wait(12);`
529			`REG32(GFX_AA) = aa;`
530			`REG32(GFX_AB) = ab;`
531			`REG32(GFX_AC) = ac;`
532			`REG32(GFX_TX) = tx;`
533			`REG32(GFX_BA) = ba;`
534			`REG32(GFX_BB) = bb;`
535			`REG32(GFX_BC) = bc;`
536			`REG32(GFX_TY) = ty;`
537			`REG32(GFX_CA) = ca;`
538			`REG32(GFX_CB) = cb;`
539			`REG32(GFX_CC) = cc;`
540			`REG32(GFX_TZ) = tz;`
541			`}`
542