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[/] [othellogame/] [trunk/] [rtl/] [RB_cnt.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 marius_mtm 
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date:    23:44:58 05/05/2009
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// Design Name:
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// Module Name:    RB_cnt
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module RB_cnt(
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                clk,
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                RST,
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                B,
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                R,
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                cntB,
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                cntR
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    );
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input clk;
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input RST;
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input [63:0] B;
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input [63:0] R;
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output [6:0] cntB;
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output [6:0] cntR;
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reg [3:0] cntB_p00_d;
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reg [3:0] cntB_p01_d;
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reg [3:0] cntB_p02_d;
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reg [3:0] cntB_p03_d;
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reg [3:0] cntB_p04_d;
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reg [3:0] cntB_p05_d;
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reg [3:0] cntB_p06_d;
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reg [3:0] cntB_p07_d;
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reg [3:0] cntR_p00_d;
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reg [3:0] cntR_p01_d;
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reg [3:0] cntR_p02_d;
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reg [3:0] cntR_p03_d;
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reg [3:0] cntR_p04_d;
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reg [3:0] cntR_p05_d;
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reg [3:0] cntR_p06_d;
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reg [3:0] cntR_p07_d;
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reg [6:0] cntB_d;
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reg [6:0] cntR_d;
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reg [6:0] cntB_q;
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reg [6:0] cntR_q;
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wire [6:0] cntR;
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wire [6:0] cntB;
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assign cntB = cntB_q;
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assign cntR = cntR_q;
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always @( * ) begin
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        cntB_p00_d = B[00] + B[01] + B[02] + B[03] + B[04] + B[05] + B[06] + B[07];
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        cntB_p01_d = B[08] + B[09] + B[10] + B[11] + B[12] + B[13] + B[14] + B[15];
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        cntB_p02_d = B[16] + B[17] + B[18] + B[19] + B[20] + B[21] + B[22] + B[23];
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        cntB_p03_d = B[24] + B[25] + B[26] + B[27] + B[28] + B[29] + B[30] + B[31];
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        cntB_p04_d = B[32] + B[33] + B[34] + B[35] + B[36] + B[37] + B[38] + B[39];
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        cntB_p05_d = B[40] + B[41] + B[42] + B[43] + B[44] + B[45] + B[46] + B[47];
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        cntB_p06_d = B[48] + B[49] + B[50] + B[51] + B[52] + B[53] + B[54] + B[55];
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        cntB_p07_d = B[56] + B[57] + B[58] + B[59] + B[60] + B[61] + B[62] + B[63];
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        cntB_d = cntB_p00_d + cntB_p01_d + cntB_p02_d + cntB_p03_d + cntB_p04_d + cntB_p05_d + cntB_p06_d + cntB_p07_d;
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        cntR_p00_d = R[00] + R[01] + R[02] + R[03] + R[04] + R[05] + R[06] + R[07];
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        cntR_p01_d = R[08] + R[09] + R[10] + R[11] + R[12] + R[13] + R[14] + R[15];
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        cntR_p02_d = R[16] + R[17] + R[18] + R[19] + R[20] + R[21] + R[22] + R[23];
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        cntR_p03_d = R[24] + R[25] + R[26] + R[27] + R[28] + R[29] + R[30] + R[31];
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        cntR_p04_d = R[32] + R[33] + R[34] + R[35] + R[36] + R[37] + R[38] + R[39];
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        cntR_p05_d = R[40] + R[41] + R[42] + R[43] + R[44] + R[45] + R[46] + R[47];
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        cntR_p06_d = R[48] + R[49] + R[50] + R[51] + R[52] + R[53] + R[54] + R[55];
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        cntR_p07_d = R[56] + R[57] + R[58] + R[59] + R[60] + R[61] + R[62] + R[63];
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        cntR_d = cntR_p00_d + cntR_p01_d + cntR_p02_d + cntR_p03_d + cntR_p04_d + cntR_p05_d + cntR_p06_d + cntR_p07_d;
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end
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always @(posedge clk) begin
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        if ( RST ) begin
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                cntB_q <= 0;
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                cntR_q <= 0;
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        end
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        else begin
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                cntB_q <= cntB_d;
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                cntR_q <= cntR_d;
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        end
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end
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endmodule

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