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[/] [othellogame/] [trunk/] [rtl/] [time_analysis.v] - Blame information for rev 2

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:51:55 05/08/2009 
// Design Name: 
// Module Name:    time_analysis 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//           rs232
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//  Marius TIVADAR.
//
//////////////////////////////////////////////////////////////////////////////////
module time_analysis(
                clk,
                RST,
                start,
                time_cnt,
                busy,
                TxD
    );
 
input clk;
input RST;
input [31:0] time_cnt;
input start;
output busy;
output TxD;
 
 
 
reg [31:0] data;
 
wire TxD_busy;
 
reg [7:0] chunk_q;
reg [7:0] chunk_d;
//reg [3:0] nibble;
reg [7:0] hex_byte_d;
reg [7:0] hex_byte_q;
reg [4:0] how_many_q;
reg busy_q;
 
reg [2:0] state_d;
reg [2:0] state_q;
 
 
 
parameter GATHER_0   = 3'b000;
parameter GATHER     = 3'b001;
parameter TRANSMIT_0 = 3'b010;
parameter TRANSMIT   = 3'b011;
parameter DONE       = 3'b100;
 
 rs232 tx(.clk(clk),
                         .RST(RST),
                         .TxD_data(hex_byte_q),
                         .TxD_start(state_q == TRANSMIT_0),
                         .TxD_busy(TxD_busy),
                         .TxD(TxD));
 
 
 
//assign test = TxD;
wire [3:0] nibble = data[31:28];
assign busy = busy_q;
reg busy_nibble_d;
reg busy_nibble_q;
 
always @( * ) begin
   state_d = state_q;
        busy_nibble_d = busy_nibble_q;
        hex_byte_d = hex_byte_q;
        case (state_q)
                 GATHER_0: begin
                                                 state_d  = GATHER;
                                                 busy_nibble_d = 1;
                                          end
            GATHER:
                     begin
                                        if ( how_many_q == 5'b01000) begin
                                                        hex_byte_d = 8'd10;
                                        end
                                        else begin
                                                case (nibble)
                                                         4'b0000 : hex_byte_d = 8'h30;
                                                         4'b0001 : hex_byte_d = 8'h31;
                                                         4'b0010 : hex_byte_d = 8'h32;
                                                         4'b0011 : hex_byte_d = 8'h33;
                                                         4'b0100 : hex_byte_d = 8'h34;
                                                         4'b0101 : hex_byte_d = 8'h35;
                                                         4'b0110 : hex_byte_d = 8'h36;
                                                         4'b0111 : hex_byte_d = 8'h37;
                                                         4'b1000 : hex_byte_d = 8'h38;
                                                         4'b1001 : hex_byte_d = 8'h39;
                                                         4'b1010 : hex_byte_d = 8'h61;
                                                         4'b1011 : hex_byte_d = 8'h62;
                                                         4'b1100 : hex_byte_d = 8'h63;
                                                         4'b1101 : hex_byte_d = 8'h64;
                                                         4'b1110 : hex_byte_d = 8'h65;
                                                         4'b1111 : hex_byte_d = 8'h66;
 
                                                endcase
 
 
                                        end
                                        state_d = TRANSMIT_0;
                          end
                TRANSMIT_0: begin
                                                //hex_byte_q is ready
                              state_d = TRANSMIT;
                                           end
                                                /*
                TRANSMIT_1: begin
                                                        if ( ~TxD_busy ) begin
                                                                                                        state_d = TRANSMIT_1;
                                                                                                 end
                                                        else begin
                                                                state_d = TRANSMIT;
                                                        end
                                           end
                                                */
                TRANSMIT: begin
                                                if ( TxD_busy ) begin
                                                        state_d = TRANSMIT;
                                                end
                                                else begin
                                                   busy_nibble_d = 0;
                                                        state_d = DONE;
                                                end
 
                                         end
                DONE: begin
                                        busy_nibble_d = 1;
                                        state_d = state_q;
                                end
        endcase
end
 
always @(posedge clk) begin
    if (RST) begin
                data <= 0;
                how_many_q <= 0;
                busy_q <= 0;
                state_q <= GATHER_0;
                busy_nibble_q <= 0;
                hex_byte_q <= 0;
         end
         else begin
                if ( start ) begin
                   data <= time_cnt;
                        state_q <= GATHER_0;
                        how_many_q <= 0;
                        busy_q <= 1;
                        busy_nibble_q <= 1;
                        hex_byte_q <= 0;
 
                end
                else begin
 
                  if ( (how_many_q < 5'b01000) && (~busy_nibble_q) ) begin
                     busy_q <= 1;
                          data <= { data[28:0], data[31:28] };
 
                          how_many_q <= how_many_q + 1;
                          state_q <= GATHER_0;
                  end
                  else
                  if ( (how_many_q == 5'b01000) && (~busy_nibble_q) )
                  begin
                      how_many_q <= how_many_q;
                                state_q <= state_d;
                                busy_q <= 0;
                  end
                  else begin
                          how_many_q <= how_many_q;
                          state_q <= state_d;
                          hex_byte_q <= hex_byte_d;
                          busy_q <= busy_q;
 
                  end
                  busy_nibble_q  <= busy_nibble_d;
                  hex_byte_q <= hex_byte_d;
 
                end
         end
end
 
 
endmodule

Line No.	Rev	Author	Line
1	2	marius_mtm	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company:`
4			`// Engineer:`
5			`//`
6			`// Create Date: 15:51:55 05/08/2009`
7			`// Design Name:`
8			`// Module Name: time_analysis`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`// rs232`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`// Marius TIVADAR.`
20			`//`
21			`//////////////////////////////////////////////////////////////////////////////////`
22			`module time_analysis(`
23			`clk,`
24			`RST,`
25			`start,`
26			`time_cnt,`
27			`busy,`
28			`TxD`
29			`);`
30
31			`input clk;`
32			`input RST;`
33			`input [31:0] time_cnt;`
34			`input start;`
35			`output busy;`
36			`output TxD;`
37
38
39
40			`reg [31:0] data;`
41
42			`wire TxD_busy;`
43
44			`reg [7:0] chunk_q;`
45			`reg [7:0] chunk_d;`
46			`//reg [3:0] nibble;`
47			`reg [7:0] hex_byte_d;`
48			`reg [7:0] hex_byte_q;`
49			`reg [4:0] how_many_q;`
50			`reg busy_q;`
51
52			`reg [2:0] state_d;`
53			`reg [2:0] state_q;`
54
55
56
57			`parameter GATHER_0 = 3'b000;`
58			`parameter GATHER = 3'b001;`
59			`parameter TRANSMIT_0 = 3'b010;`
60			`parameter TRANSMIT = 3'b011;`
61			`parameter DONE = 3'b100;`
62
63			`rs232 tx(.clk(clk),`
64			`.RST(RST),`
65			`.TxD_data(hex_byte_q),`
66			`.TxD_start(state_q == TRANSMIT_0),`
67			`.TxD_busy(TxD_busy),`
68			`.TxD(TxD));`
69
70
71
72			`//assign test = TxD;`
73			`wire [3:0] nibble = data[31:28];`
74			`assign busy = busy_q;`
75			`reg busy_nibble_d;`
76			`reg busy_nibble_q;`
77
78			`always @( * ) begin`
79			`state_d = state_q;`
80			`busy_nibble_d = busy_nibble_q;`
81			`hex_byte_d = hex_byte_q;`
82			`case (state_q)`
83			`GATHER_0: begin`
84			`state_d = GATHER;`
85			`busy_nibble_d = 1;`
86			`end`
87			`GATHER:`
88			`begin`
89			`if ( how_many_q == 5'b01000) begin`
90			`hex_byte_d = 8'd10;`
91			`end`
92			`else begin`
93			`case (nibble)`
94			`4'b0000 : hex_byte_d = 8'h30;`
95			`4'b0001 : hex_byte_d = 8'h31;`
96			`4'b0010 : hex_byte_d = 8'h32;`
97			`4'b0011 : hex_byte_d = 8'h33;`
98			`4'b0100 : hex_byte_d = 8'h34;`
99			`4'b0101 : hex_byte_d = 8'h35;`
100			`4'b0110 : hex_byte_d = 8'h36;`
101			`4'b0111 : hex_byte_d = 8'h37;`
102			`4'b1000 : hex_byte_d = 8'h38;`
103			`4'b1001 : hex_byte_d = 8'h39;`
104			`4'b1010 : hex_byte_d = 8'h61;`
105			`4'b1011 : hex_byte_d = 8'h62;`
106			`4'b1100 : hex_byte_d = 8'h63;`
107			`4'b1101 : hex_byte_d = 8'h64;`
108			`4'b1110 : hex_byte_d = 8'h65;`
109			`4'b1111 : hex_byte_d = 8'h66;`
110
111			`endcase`
112
113
114			`end`
115			`state_d = TRANSMIT_0;`
116			`end`
117			`TRANSMIT_0: begin`
118			`//hex_byte_q is ready`
119			`state_d = TRANSMIT;`
120			`end`
121			`/*`
122			`TRANSMIT_1: begin`
123			`if ( ~TxD_busy ) begin`
124			`state_d = TRANSMIT_1;`
125			`end`
126			`else begin`
127			`state_d = TRANSMIT;`
128			`end`
129			`end`
130			`*/`
131			`TRANSMIT: begin`
132			`if ( TxD_busy ) begin`
133			`state_d = TRANSMIT;`
134			`end`
135			`else begin`
136			`busy_nibble_d = 0;`
137			`state_d = DONE;`
138			`end`
139
140			`end`
141			`DONE: begin`
142			`busy_nibble_d = 1;`
143			`state_d = state_q;`
144			`end`
145			`endcase`
146			`end`
147
148			`always @(posedge clk) begin`
149			`if (RST) begin`
150			`data <= 0;`
151			`how_many_q <= 0;`
152			`busy_q <= 0;`
153			`state_q <= GATHER_0;`
154			`busy_nibble_q <= 0;`
155			`hex_byte_q <= 0;`
156			`end`
157			`else begin`
158			`if ( start ) begin`
159			`data <= time_cnt;`
160			`state_q <= GATHER_0;`
161			`how_many_q <= 0;`
162			`busy_q <= 1;`
163			`busy_nibble_q <= 1;`
164			`hex_byte_q <= 0;`
165
166			`end`
167			`else begin`
168
169			`if ( (how_many_q < 5'b01000) && (~busy_nibble_q) ) begin`
170			`busy_q <= 1;`
171			`data <= { data[28:0], data[31:28] };`
172
173			`how_many_q <= how_many_q + 1;`
174			`state_q <= GATHER_0;`
175			`end`
176			`else`
177			`if ( (how_many_q == 5'b01000) && (~busy_nibble_q) )`
178			`begin`
179			`how_many_q <= how_many_q;`
180			`state_q <= state_d;`
181			`busy_q <= 0;`
182			`end`
183			`else begin`
184			`how_many_q <= how_many_q;`
185			`state_q <= state_d;`
186			`hex_byte_q <= hex_byte_d;`
187			`busy_q <= busy_q;`
188
189			`end`
190			`busy_nibble_q <= busy_nibble_d;`
191			`hex_byte_q <= hex_byte_d;`
192
193			`end`
194			`end`
195			`end`
196
197
198			`endmodule`

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[/] [othellogame/] [trunk/] [rtl/] [time_analysis.v] - Blame information for rev 2