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/*
    Copyright 2011, City University of Hong Kong
    Author is Homer (Dongsheng) Hsing.
 
    This file is part of Tate Bilinear Pairing Core.
 
    Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
    it under the terms of the GNU Lesser General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.
 
    Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU Lesser General Public License for more details.
 
    You should have received a copy of the GNU Lesser General Public License
    along with Tate Bilinear Pairing Core.  If not, see http://www.gnu.org/licenses/lgpl.txt
*/
 
`include "inc.v"
 
// out = (v1 & l1) | (v2 & l2)
module f33m_mux2(v1, l1, v2, l2, out);
    input [`W3:0] v1, v2;
    input l1, l2;
    output [`W3:0] out;
    genvar i;
    generate
        for(i=0;i<=`W3;i=i+1)
          begin : label
            assign out[i] = (v1[i] & l1) | (v2[i] & l2);
          end
    endgenerate
endmodule
 
// out = (v1 & l1) | (v2 & l2) | (v3 & l3)
module f33m_mux3(v1, l1, v2, l2, v3, l3, out);
    input [`W3:0] v1, v2, v3;
    input l1, l2, l3;
    output [`W3:0] out;
    genvar i;
    generate
        for(i=0;i<=`W3;i=i+1)
          begin : label
            assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
          end
    endgenerate
endmodule
 
// c == a+b in GF(3^{3*M})
module f33m_add(a, b, c);
    input [`W3:0] a,b;
    output [`W3:0] c;
    wire [`WIDTH:0] a0,a1,a2,b0,b1,b2,c0,c1,c2;
    assign {a2,a1,a0} = a;
    assign {b2,b1,b0} = b;
    assign c = {c2,c1,c0};
    f3m_add
        ins1 (a0,b0,c0),
        ins2 (a1,b1,c1),
        ins3 (a2,b2,c2);
endmodule
 
// c == -a in GF(3^{3*M})
module f33m_neg(a, c);
    input [`W3:0] a;
    output [`W3:0] c;
    wire [`WIDTH:0] a0,a1,a2,c0,c1,c2;
    assign {a2,a1,a0} = a;
    assign c = {c2,c1,c0};
    f3m_neg
        ins1 (a0,c0),
        ins2 (a1,c1),
        ins3 (a2,c2);
endmodule
 
// c == a*b in GF(3^{3*M})
module f33m_mult(clk, reset, a, b, c, done);
    input clk, reset;
    input [`W3:0] a, b;
    output reg [`W3:0] c;
    output reg done;
 
    reg [`WIDTH:0] x0, x1, x2, x3, x4, x5;
    wire [`WIDTH:0]  a0, a1, a2,
                     b0, b1, b2,
                     c0, c1, c2,
                     v1, v2, v3, v4, v5, v6,
                     nx0, nx2, nx5,
                     d0, d1, d2, d3, d4;
    reg [6:0] K;
    wire e0, e1, e2,
         e3, e4, e5,
         mult_done, p, rst;
    wire [`WIDTH:0] in0, in1;
    wire [`WIDTH:0] o;
    reg mult_reset, delay1, delay2;
 
    assign {e0,e1,e2,e3,e4,e5} = K[6:1];
    assign {a2,a1,a0} = a;
    assign {b2,b1,b0} = b;
    assign d4 = x0;
    assign d0 = x5;
    assign rst = delay2;
 
    f3m_mux6
        ins1 (a2,v1,a1,v3,v5,a0,e0,e1,e2,e3,e4,e5,in0), // $in0$ is the first input
        ins2 (b2,v2,b1,v4,v6,b0,e0,e1,e2,e3,e4,e5,in1); // $in1$ is the second input
    f3m_mult
        ins3 (clk, mult_reset, in0, in1, o, mult_done); // o == in0 * in1
    func6
        ins4 (clk, reset, mult_done, p);
    f3m_add
        ins5 (a1, a2, v1), // v1 == a1+a2
        ins6 (b1, b2, v2), // v2 == b1+b2
        ins7 (a0, a2, v3), // v3 == a0+a2
        ins8 (b0, b2, v4), // v4 == b0+b2
        ins9 (a0, a1, v5), // v5 == a0+a1
        ins10 (b0, b1, v6), // v6 == b0+b1
        ins11 (d0, d3, c0), // c0 == d0+d3
        ins12 (d2, d4, c2); // c2 == d2+d4
    f3m_neg
        ins13 (x0, nx0), // nx0 == -x0
        ins14 (x2, nx2), // nx2 == -x2
        ins15 (x5, nx5); // nx5 == -x5
    f3m_add3
        ins16 (x1, nx0, nx2, d3), // d3 == x1-x0-x2
        ins17 (x4, nx2, nx5, d1), // d1 == x4-x2-x5
        ins18 (d1, d3, d4, c1); // c1 == d1+d3+d4
    f3m_add4
        ins19 (x3, x2, nx0, nx5, d2); // d2 == x3+x2-x0-x5
 
    always @ (posedge clk)
      begin
        if (reset) K <= 7'b1000000;
        else if (p|K[0]) K <= {1'b0,K[6:1]};
      end
 
    always @ (posedge clk)
      begin
        if (e0) x0 <= o; // x0 == a2*b2
        if (e1) x1 <= o; // x1 == (a2+a1)*(b2+b1)
        if (e2) x2 <= o; // x2 == a1*b1
        if (e3) x3 <= o; // x3 == (a2+a0)*(b2+b0)
        if (e4) x4 <= o; // x4 == (a1+a0)*(b1+b0)
        if (e5) x5 <= o; // x5 == a0*b0
      end
 
    always @ (posedge clk)
      begin
        if (reset) done <= 0;
        else if (K[0])
          begin
            done <= 1; c <= {c2,c1,c0};
          end
      end
 
    always @ (posedge clk)
      begin
        if (rst) mult_reset <= 1;
        else if (mult_done) mult_reset <= 1;
        else mult_reset <= 0;
      end
 
    always @ (posedge clk)
      begin
        delay2 <= delay1; delay1 <= reset;
      end
endmodule
 
// c0 == a0*b0; c1 == a1*b1; c2 == a2*b2; all in GF(3^{3*M})
module f33m_mult3(clk, reset,
                 a0, b0, c0,
                 a1, b1, c1,
                 a2, b2, c2,
                 done);
    input clk, reset;
    input [`W3:0] a0, b0, a1, b1, a2, b2;
    output reg [`W3:0] c0, c1, c2;
    output reg done;
    reg [3:0] K;
    reg mult_reset, delay1, delay2;
    wire e1, e2, e3, mult_done, delay3, rst;
    wire [`W3:0] in1, in2, o;
 
    assign rst = delay2;
    assign {e1,e2,e3} = K[3:1];
 
    f33m_mux3
        ins9 (a0, e1, a1, e2, a2, e3, in1),
        ins10 (b0, e1, b1, e2, b2, e3, in2);
    f33m_mult
        ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2
    func6
        ins12 (clk, reset, mult_done, delay3);
 
    always @ (posedge clk)
      begin
        if (e1) c0 <= o;
        if (e2) c1 <= o;
        if (e3) c2 <= o;
      end
 
    always @ (posedge clk)
        if (reset) K <= 4'b1000;
        else if (delay3|K[0]) K <= {1'b0,K[3:1]};
 
    always @ (posedge clk)
      begin
        if (rst) mult_reset <= 1;
        else if (mult_done) mult_reset <= 1;
        else mult_reset <= 0;
      end
 
    always @ (posedge clk)
        if (reset)     done <= 0;
        else if (K[0]) done <= 1;
 
    always @ (posedge clk)
      begin
        delay2 <= delay1; delay1 <= reset;
      end
endmodule
 
// c0 == a0*b0; c1 == a1*b1; both in GF(3^{3*M})
module f33m_mult2(clk, reset,
                 a0, b0, c0,
                 a1, b1, c1,
                 done);
    input clk, reset;
    input [`W3:0] a0, b0, a1, b1;
    output reg [`W3:0] c0, c1;
    output reg done;
    reg [2:0] K;
    reg mult_reset, delay1, delay2;
    wire e1, e2, mult_done, delay3, rst;
    wire [`W3:0] in1, in2, o;
 
    assign rst = delay2;
    assign {e1,e2} = K[2:1];
 
    f33m_mux2
        ins9 (a0, e1, a1, e2, in1),
        ins10 (b0, e1, b1, e2, in2);
    f33m_mult
        ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2
    func6
        ins12 (clk, reset, mult_done, delay3);
 
    always @ (posedge clk)
      begin
        if (e1) c0 <= o;
        if (e2) c1 <= o;
      end
 
    always @ (posedge clk)
        if (reset) K <= 3'b100;
        else if (delay3|K[0]) K <= {1'b0,K[2:1]};
 
    always @ (posedge clk)
      begin
        if (rst) mult_reset <= 1;
        else if (mult_done) mult_reset <= 1;
        else mult_reset <= 0;
      end
 
    always @ (posedge clk)
        if (reset)     done <= 0;
        else if (K[0]) done <= 1;
 
    always @ (posedge clk)
      begin
        delay2 <= delay1; delay1 <= reset;
      end
endmodule
 
// c == a^{-1} in GF(3^{3*M})
module f33m_inv(clk, reset, a, c, done);
    input clk, reset;
    input [`W3:0] a;
    output reg [`W3:0] c;
    output reg done;
 
    wire [`WIDTH:0] a0, a1, a2,
                    c0, c1, c2,
                    v0, v1, v2, v3, v4, v5,
                    v6, v7, v8, v9, v10, v11,
                    v12, v13, v14, v15, v16,
                    v17, nv2, nv11, nv14;
    wire rst1, rst2, rst3, rst4,
         done1, done2, done3, done4,
         dummy;
    reg [4:0] K;
 
    assign {a2, a1, a0} = a;
    assign rst1 = reset;
 
    f3m_mult3
        ins1 (clk, rst1,
              a0, a0, v0, // v0 == a0^2
              a1, a1, v1, // v1 == a1^2
              a2, a2, v2, // v2 == a2^2
              done1),
        ins2 (clk, rst2,
              v0, v3, v6,  // v6 == (a0-a2)*(a0^2)
              v1, v4, v7,  // v7 == (a1-a0)*(a1^2)
              v2, v5, v8,  // v8 == (a0-a1+a2)*(a2^2)
              done2),
        ins3 (clk, rst1,
              a0, a2, v11, // v11 == a0*a2
              a0, a1, v12, // v12 == a0*a1
              a1, a2, v13, // v13 == a1*a2
              dummy),
        ins4 (clk, rst4,
              v10, v15, c0,
              v10, v16, c1,
              v10, v17, c2,
              done4);
    f3m_sub
        ins5 (a0, a2, v3), // v3 == a0-a2
        ins6 (a1, a0, v4), // v4 == a1-a0
        ins7 (a2, v4, v5); // v5 == a2-v4 == a0-a1+a2
    f3m_add3
        ins8 (v6, v7, v8, v9),    // v9 == v6+v7+v8
        ins9 (v11, v1, v13, v14), // v14 == v11+v1+v13
        ins10 (nv14, v0, v2, v15),  // v15 == v0+v2-(v11+v1+v13)
        ins11 (v1, nv2, nv11, v17); // v17 == a1^2-a0*a2-a2^2
    f3m_neg
        ins12 (v2,  nv2),  // nv2 == -v2
        ins13 (v11, nv11), // nv11 == -v11
        ins14 (v14, nv14); // nv14 == -v14 == -(v11+v1+v13)
    f3m_sub
        ins15 (v2, v12, v16); // v16 == a2^2-a0*a1
    f3m_inv
        ins16 (clk, rst3, v9, v10, done3); // v10 == v9^(-1)
    func6
        ins17 (clk, reset, done1, rst2),
        ins18 (clk, reset, done2, rst3),
        ins19 (clk, reset, done3, rst4);
 
    always @ (posedge clk)
        if (reset) K <= 5'h10;
        else if ((K[4]&rst2)|(K[3]&rst3)|(K[2]&rst4)|(K[1]&done4)|K[0])
            K <= K >> 1;
 
    always @ (posedge clk)
        if (reset) done <= 0;
        else if (K[0])
          begin
            done <= 1; c <= {c2,c1,c0};
          end
endmodule
 

Line No.	Rev	Author	Line
1	24	homer.xing	`/*`
2			`Copyright 2011, City University of Hong Kong`
3	32	homer.xing	`Author is Homer (Dongsheng) Hsing.`
4	24	homer.xing
5			`This file is part of Tate Bilinear Pairing Core.`
6
7			`Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify`
8			`it under the terms of the GNU Lesser General Public License as published by`
9			`the Free Software Foundation, either version 3 of the License, or`
10			`(at your option) any later version.`
11
12			`Tate Bilinear Pairing Core is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU Lesser General Public License for more details.`
16
17	31	homer.xing	`You should have received a copy of the GNU Lesser General Public License`
18	30	homer.xing	`along with Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt`
19	24	homer.xing	`*/`
20
21	3	homer.xing	`include "inc.v"
22
23	8	homer.xing	`// out = (v1 & l1) \| (v2 & l2)`
24			`module f33m_mux2(v1, l1, v2, l2, out);`
25			input [`W3:0] v1, v2;
26			`input l1, l2;`
27			output [`W3:0] out;
28			`genvar i;`
29			`generate`
30			for(i=0;i<=`W3;i=i+1)
31			`begin : label`
32			`assign out[i] = (v1[i] & l1) \| (v2[i] & l2);`
33			`end`
34			`endgenerate`
35			`endmodule`
36
37			`// out = (v1 & l1) \| (v2 & l2) \| (v3 & l3)`
38			`module f33m_mux3(v1, l1, v2, l2, v3, l3, out);`
39			input [`W3:0] v1, v2, v3;
40			`input l1, l2, l3;`
41			output [`W3:0] out;
42			`genvar i;`
43			`generate`
44			for(i=0;i<=`W3;i=i+1)
45			`begin : label`
46			`assign out[i] = (v1[i] & l1) \| (v2[i] & l2) \| (v3[i] & l3);`
47			`end`
48			`endgenerate`
49			`endmodule`
50
51	3	homer.xing	`// c == a+b in GF(3^{3*M})`
52			`module f33m_add(a, b, c);`
53			input [`W3:0] a,b;
54			output [`W3:0] c;
55			wire [`WIDTH:0] a0,a1,a2,b0,b1,b2,c0,c1,c2;
56			`assign {a2,a1,a0} = a;`
57			`assign {b2,b1,b0} = b;`
58			`assign c = {c2,c1,c0};`
59			`f3m_add`
60			`ins1 (a0,b0,c0),`
61			`ins2 (a1,b1,c1),`
62			`ins3 (a2,b2,c2);`
63			`endmodule`
64
65	8	homer.xing	`// c == -a in GF(3^{3*M})`
66			`module f33m_neg(a, c);`
67			input [`W3:0] a;
68	3	homer.xing	output [`W3:0] c;
69	8	homer.xing	wire [`WIDTH:0] a0,a1,a2,c0,c1,c2;
70	3	homer.xing	`assign {a2,a1,a0} = a;`
71			`assign c = {c2,c1,c0};`
72	8	homer.xing	`f3m_neg`
73			`ins1 (a0,c0),`
74			`ins2 (a1,c1),`
75			`ins3 (a2,c2);`
76	3	homer.xing	`endmodule`
77
78			`// c == ab in GF(3^{3M})`
79			`module f33m_mult(clk, reset, a, b, c, done);`
80			`input clk, reset;`
81			input [`W3:0] a, b;
82			output reg [`W3:0] c;
83			`output reg done;`
84
85			reg [`WIDTH:0] x0, x1, x2, x3, x4, x5;
86			wire [`WIDTH:0] a0, a1, a2,
87			`b0, b1, b2,`
88			`c0, c1, c2,`
89			`v1, v2, v3, v4, v5, v6,`
90			`nx0, nx2, nx5,`
91			`d0, d1, d2, d3, d4;`
92			`reg [6:0] K;`
93			`wire e0, e1, e2,`
94			`e3, e4, e5,`
95			`mult_done, p, rst;`
96			wire [`WIDTH:0] in0, in1;
97			wire [`WIDTH:0] o;
98			`reg mult_reset, delay1, delay2;`
99
100			`assign {e0,e1,e2,e3,e4,e5} = K[6:1];`
101			`assign {a2,a1,a0} = a;`
102			`assign {b2,b1,b0} = b;`
103			`assign d4 = x0;`
104			`assign d0 = x5;`
105			`assign rst = delay2;`
106
107			`f3m_mux6`
108			`ins1 (a2,v1,a1,v3,v5,a0,e0,e1,e2,e3,e4,e5,in0), // $in0$ is the first input`
109			`ins2 (b2,v2,b1,v4,v6,b0,e0,e1,e2,e3,e4,e5,in1); // $in1$ is the second input`
110			`f3m_mult`
111			`ins3 (clk, mult_reset, in0, in1, o, mult_done); // o == in0 * in1`
112			`func6`
113	8	homer.xing	`ins4 (clk, reset, mult_done, p);`
114	3	homer.xing	`f3m_add`
115			`ins5 (a1, a2, v1), // v1 == a1+a2`
116			`ins6 (b1, b2, v2), // v2 == b1+b2`
117			`ins7 (a0, a2, v3), // v3 == a0+a2`
118			`ins8 (b0, b2, v4), // v4 == b0+b2`
119			`ins9 (a0, a1, v5), // v5 == a0+a1`
120			`ins10 (b0, b1, v6), // v6 == b0+b1`
121			`ins11 (d0, d3, c0), // c0 == d0+d3`
122			`ins12 (d2, d4, c2); // c2 == d2+d4`
123			`f3m_neg`
124			`ins13 (x0, nx0), // nx0 == -x0`
125			`ins14 (x2, nx2), // nx2 == -x2`
126			`ins15 (x5, nx5); // nx5 == -x5`
127			`f3m_add3`
128			`ins16 (x1, nx0, nx2, d3), // d3 == x1-x0-x2`
129			`ins17 (x4, nx2, nx5, d1), // d1 == x4-x2-x5`
130			`ins18 (d1, d3, d4, c1); // c1 == d1+d3+d4`
131			`f3m_add4`
132			`ins19 (x3, x2, nx0, nx5, d2); // d2 == x3+x2-x0-x5`
133
134			`always @ (posedge clk)`
135			`begin`
136			`if (reset) K <= 7'b1000000;`
137	8	homer.xing	`else if (p\|K[0]) K <= {1'b0,K[6:1]};`
138	3	homer.xing	`end`
139
140			`always @ (posedge clk)`
141			`begin`
142			`if (e0) x0 <= o; // x0 == a2*b2`
143			`if (e1) x1 <= o; // x1 == (a2+a1)*(b2+b1)`
144			`if (e2) x2 <= o; // x2 == a1*b1`
145			`if (e3) x3 <= o; // x3 == (a2+a0)*(b2+b0)`
146			`if (e4) x4 <= o; // x4 == (a1+a0)*(b1+b0)`
147			`if (e5) x5 <= o; // x5 == a0*b0`
148			`end`
149
150			`always @ (posedge clk)`
151			`begin`
152			`if (reset) done <= 0;`
153			`else if (K[0])`
154			`begin`
155			`done <= 1; c <= {c2,c1,c0};`
156			`end`
157			`end`
158
159			`always @ (posedge clk)`
160			`begin`
161			`if (rst) mult_reset <= 1;`
162			`else if (mult_done) mult_reset <= 1;`
163			`else mult_reset <= 0;`
164			`end`
165
166			`always @ (posedge clk)`
167			`begin`
168			`delay2 <= delay1; delay1 <= reset;`
169			`end`
170			`endmodule`
171
172	8	homer.xing	`// c0 == a0b0; c1 == a1b1; c2 == a2b2; all in GF(3^{3M})`
173			`module f33m_mult3(clk, reset,`
174			`a0, b0, c0,`
175			`a1, b1, c1,`
176			`a2, b2, c2,`
177			`done);`
178			`input clk, reset;`
179			input [`W3:0] a0, b0, a1, b1, a2, b2;
180			output reg [`W3:0] c0, c1, c2;
181			`output reg done;`
182			`reg [3:0] K;`
183			`reg mult_reset, delay1, delay2;`
184			`wire e1, e2, e3, mult_done, delay3, rst;`
185			wire [`W3:0] in1, in2, o;
186
187			`assign rst = delay2;`
188			`assign {e1,e2,e3} = K[3:1];`
189
190			`f33m_mux3`
191			`ins9 (a0, e1, a1, e2, a2, e3, in1),`
192			`ins10 (b0, e1, b1, e2, b2, e3, in2);`
193			`f33m_mult`
194			`ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2`
195			`func6`
196			`ins12 (clk, reset, mult_done, delay3);`
197
198			`always @ (posedge clk)`
199			`begin`
200			`if (e1) c0 <= o;`
201			`if (e2) c1 <= o;`
202			`if (e3) c2 <= o;`
203			`end`
204
205			`always @ (posedge clk)`
206			`if (reset) K <= 4'b1000;`
207			`else if (delay3\|K[0]) K <= {1'b0,K[3:1]};`
208
209			`always @ (posedge clk)`
210			`begin`
211			`if (rst) mult_reset <= 1;`
212			`else if (mult_done) mult_reset <= 1;`
213			`else mult_reset <= 0;`
214			`end`
215
216			`always @ (posedge clk)`
217			`if (reset) done <= 0;`
218			`else if (K[0]) done <= 1;`
219
220			`always @ (posedge clk)`
221			`begin`
222			`delay2 <= delay1; delay1 <= reset;`
223			`end`
224			`endmodule`
225
226			`// c0 == a0b0; c1 == a1b1; both in GF(3^{3*M})`
227			`module f33m_mult2(clk, reset,`
228			`a0, b0, c0,`
229			`a1, b1, c1,`
230			`done);`
231			`input clk, reset;`
232			input [`W3:0] a0, b0, a1, b1;
233			output reg [`W3:0] c0, c1;
234			`output reg done;`
235			`reg [2:0] K;`
236			`reg mult_reset, delay1, delay2;`
237			`wire e1, e2, mult_done, delay3, rst;`
238			wire [`W3:0] in1, in2, o;
239
240			`assign rst = delay2;`
241			`assign {e1,e2} = K[2:1];`
242
243			`f33m_mux2`
244			`ins9 (a0, e1, a1, e2, in1),`
245			`ins10 (b0, e1, b1, e2, in2);`
246			`f33m_mult`
247			`ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2`
248			`func6`
249			`ins12 (clk, reset, mult_done, delay3);`
250
251			`always @ (posedge clk)`
252			`begin`
253			`if (e1) c0 <= o;`
254			`if (e2) c1 <= o;`
255			`end`
256
257			`always @ (posedge clk)`
258			`if (reset) K <= 3'b100;`
259			`else if (delay3\|K[0]) K <= {1'b0,K[2:1]};`
260
261			`always @ (posedge clk)`
262			`begin`
263			`if (rst) mult_reset <= 1;`
264			`else if (mult_done) mult_reset <= 1;`
265			`else mult_reset <= 0;`
266			`end`
267
268			`always @ (posedge clk)`
269			`if (reset) done <= 0;`
270			`else if (K[0]) done <= 1;`
271
272			`always @ (posedge clk)`
273			`begin`
274			`delay2 <= delay1; delay1 <= reset;`
275			`end`
276			`endmodule`
277
278	6	homer.xing	`// c == a^{-1} in GF(3^{3*M})`
279	7	homer.xing	`module f33m_inv(clk, reset, a, c, done);`
280			`input clk, reset;`
281			input [`W3:0] a;
282			output reg [`W3:0] c;
283			`output reg done;`
284
285			wire [`WIDTH:0] a0, a1, a2,
286			`c0, c1, c2,`
287			`v0, v1, v2, v3, v4, v5,`
288			`v6, v7, v8, v9, v10, v11,`
289			`v12, v13, v14, v15, v16,`
290			`v17, nv2, nv11, nv14;`
291			`wire rst1, rst2, rst3, rst4,`
292			`done1, done2, done3, done4,`
293			`dummy;`
294			`reg [4:0] K;`
295
296			`assign {a2, a1, a0} = a;`
297			`assign rst1 = reset;`
298
299			`f3m_mult3`
300			`ins1 (clk, rst1,`
301			`a0, a0, v0, // v0 == a0^2`
302			`a1, a1, v1, // v1 == a1^2`
303			`a2, a2, v2, // v2 == a2^2`
304			`done1),`
305			`ins2 (clk, rst2,`
306			`v0, v3, v6, // v6 == (a0-a2)*(a0^2)`
307			`v1, v4, v7, // v7 == (a1-a0)*(a1^2)`
308			`v2, v5, v8, // v8 == (a0-a1+a2)*(a2^2)`
309			`done2),`
310			`ins3 (clk, rst1,`
311			`a0, a2, v11, // v11 == a0*a2`
312			`a0, a1, v12, // v12 == a0*a1`
313			`a1, a2, v13, // v13 == a1*a2`
314			`dummy),`
315			`ins4 (clk, rst4,`
316			`v10, v15, c0,`
317			`v10, v16, c1,`
318			`v10, v17, c2,`
319			`done4);`
320			`f3m_sub`
321			`ins5 (a0, a2, v3), // v3 == a0-a2`
322			`ins6 (a1, a0, v4), // v4 == a1-a0`
323			`ins7 (a2, v4, v5); // v5 == a2-v4 == a0-a1+a2`
324			`f3m_add3`
325			`ins8 (v6, v7, v8, v9), // v9 == v6+v7+v8`
326			`ins9 (v11, v1, v13, v14), // v14 == v11+v1+v13`
327			`ins10 (nv14, v0, v2, v15), // v15 == v0+v2-(v11+v1+v13)`
328			`ins11 (v1, nv2, nv11, v17); // v17 == a1^2-a0*a2-a2^2`
329			`f3m_neg`
330			`ins12 (v2, nv2), // nv2 == -v2`
331			`ins13 (v11, nv11), // nv11 == -v11`
332			`ins14 (v14, nv14); // nv14 == -v14 == -(v11+v1+v13)`
333			`f3m_sub`
334			`ins15 (v2, v12, v16); // v16 == a2^2-a0*a1`
335			`f3m_inv`
336			`ins16 (clk, rst3, v9, v10, done3); // v10 == v9^(-1)`
337			`func6`
338	8	homer.xing	`ins17 (clk, reset, done1, rst2),`
339			`ins18 (clk, reset, done2, rst3),`
340			`ins19 (clk, reset, done3, rst4);`
341	7	homer.xing
342			`always @ (posedge clk)`
343			`if (reset) K <= 5'h10;`
344	8	homer.xing	`else if ((K[4]&rst2)\|(K[3]&rst3)\|(K[2]&rst4)\|(K[1]&done4)\|K[0])`
345	7	homer.xing	`K <= K >> 1;`
346
347			`always @ (posedge clk)`
348			`if (reset) done <= 0;`
349			`else if (K[0])`
350			`begin`
351			`done <= 1; c <= {c2,c1,c0};`
352			`end`
353			`endmodule`
354	8	homer.xing

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