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[/] [pc_fpga_com/] [trunk/] [UDP_IP_CORE_FLEX_Virtex5/] [CONFIG_CONTROL.vhd] - Blame information for rev 2

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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:28:06 01/11/2011 
-- Design Name: 
-- Module Name:    CONFIG_CONTROL - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity CONFIG_CONTROL is
    Port ( rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           config_en : in  STD_LOGIC;
                          nxt_sof : in STD_LOGIC;
                          wren : out  STD_LOGIC;
           addr : out  STD_LOGIC_VECTOR (5 downto 0);
                          ulock_en : in  STD_LOGIC;
                          wren_checksum_1 : out  STD_LOGIC;
                          wren_checksum_2 : out  STD_LOGIC;
                          locked : out  STD_LOGIC
                         );
end CONFIG_CONTROL;
 
architecture Behavioral of CONFIG_CONTROL is
 
TYPE state is (rst_state,
                                        idle_state,
                                        pre_config_state,
                                        config_state,
                                        lock_state
                                );
 
signal current_st,next_st: state;
 
signal rst_count, en_count, stop_s, wren_checksum_1_t: std_logic;
signal counter: std_logic_vector(5 downto 0);
 
 
 
 
component wraddr_lut_mem is
  port (
    clk : in STD_LOGIC := 'X';
    a : in STD_LOGIC_VECTOR ( 5 downto 0 );
    qspo : out STD_LOGIC_VECTOR ( 5 downto 0 )
  );
end component;
 
begin
 
process(clk)
begin
if (rst='1') then
        current_st<= rst_state;
elsif (clk'event and clk='1') then
        current_st <= next_st;
end if;
end process;
 
 
process(current_st,config_en,nxt_sof,ulock_en,stop_s)
begin
case current_st is
 
when rst_state =>
 
        rst_count <='1';
        en_count <='0';
 
        wren <='0';
 
        locked<='0';
 
        next_st<=idle_state;
 
when idle_state =>
 
        rst_count <='0';
        en_count <='0';
 
        wren <='0';
 
        locked<='0';
 
        if config_en='1' then
                next_st <= pre_config_state;
        else
                next_st <= idle_state;
        end if;
 
when pre_config_state =>
 
        rst_count <='0';
        en_count <='0';
 
        wren <='0';
 
        locked<='0';
 
        if nxt_sof='0' then
                en_count <='1';
                next_st <= config_state;
        else
                en_count <='0';
                next_st <= pre_config_state;
        end if;
 
 
when config_state =>
 
        rst_count <='0';
        en_count <='1';
 
        wren <='1';
 
        locked<='0';
 
        if stop_s='1' then
                next_st <= lock_state;
        else
                next_st <= config_state;
        end if;
 
when lock_state =>
 
        rst_count <='1';
        en_count <='0';
 
        wren <='0';
 
        locked<='1';
 
        if ulock_en='1' then
                next_st <= rst_state;
        else
                next_st <= lock_state;
        end if;
 
end case;
end process;
 
process(clk)
begin
if rst_count='1' then
        counter <= "000000";
else
        if clk'event and clk='1' then
                if en_count='1' then
                        counter <= counter + "000001";
                end if;
        end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk='1' then
        if counter = "100101" then
                stop_s <='1';
        else
                stop_s <='0';
        end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk='1' then
        if counter = "010111" then
                wren_checksum_1_t <='1';
        else
                wren_checksum_1_t <='0';
        end if;
end if;
end process;
 
wren_checksum_1 <= wren_checksum_1_t;
 
process(clk)
begin
if clk'event and clk='1' then
        wren_checksum_2 <= wren_checksum_1_t;
end if;
end process;
 
 
 
wraddrlutmem: wraddr_lut_mem Port Map
 (
        clk => clk,
        a=> counter,
        qspo=> addr);
 
end Behavioral;
 

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[/] [pc_fpga_com/] [trunk/] [UDP_IP_CORE_FLEX_Virtex5/] [CONFIG_CONTROL.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	NikosAl	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 14:28:06 01/11/2011`
6			`-- Design Name:`
7			`-- Module Name: CONFIG_CONTROL - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`use IEEE.STD_LOGIC_ARITH.ALL;`
23			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
24
25			`---- Uncomment the following library declaration if instantiating`
26			`---- any Xilinx primitives in this code.`
27			`--library UNISIM;`
28			`--use UNISIM.VComponents.all;`
29
30			`entity CONFIG_CONTROL is`
31			`Port ( rst : in STD_LOGIC;`
32			`clk : in STD_LOGIC;`
33			`config_en : in STD_LOGIC;`
34			`nxt_sof : in STD_LOGIC;`
35			`wren : out STD_LOGIC;`
36			`addr : out STD_LOGIC_VECTOR (5 downto 0);`
37			`ulock_en : in STD_LOGIC;`
38			`wren_checksum_1 : out STD_LOGIC;`
39			`wren_checksum_2 : out STD_LOGIC;`
40			`locked : out STD_LOGIC`
41			`);`
42			`end CONFIG_CONTROL;`
43
44			`architecture Behavioral of CONFIG_CONTROL is`
45
46			`TYPE state is (rst_state,`
47			`idle_state,`
48			`pre_config_state,`
49			`config_state,`
50			`lock_state`
51			`);`
52
53			`signal current_st,next_st: state;`
54
55			`signal rst_count, en_count, stop_s, wren_checksum_1_t: std_logic;`
56			`signal counter: std_logic_vector(5 downto 0);`
57
58
59
60
61			`component wraddr_lut_mem is`
62			`port (`
63			`clk : in STD_LOGIC := 'X';`
64			`a : in STD_LOGIC_VECTOR ( 5 downto 0 );`
65			`qspo : out STD_LOGIC_VECTOR ( 5 downto 0 )`
66			`);`
67			`end component;`
68
69			`begin`
70
71			`process(clk)`
72			`begin`
73			`if (rst='1') then`
74			`current_st<= rst_state;`
75			`elsif (clk'event and clk='1') then`
76			`current_st <= next_st;`
77			`end if;`
78			`end process;`
79
80
81			`process(current_st,config_en,nxt_sof,ulock_en,stop_s)`
82			`begin`
83			`case current_st is`
84
85			`when rst_state =>`
86
87			`rst_count <='1';`
88			`en_count <='0';`
89
90			`wren <='0';`
91
92			`locked<='0';`
93
94			`next_st<=idle_state;`
95
96			`when idle_state =>`
97
98			`rst_count <='0';`
99			`en_count <='0';`
100
101			`wren <='0';`
102
103			`locked<='0';`
104
105			`if config_en='1' then`
106			`next_st <= pre_config_state;`
107			`else`
108			`next_st <= idle_state;`
109			`end if;`
110
111			`when pre_config_state =>`
112
113			`rst_count <='0';`
114			`en_count <='0';`
115
116			`wren <='0';`
117
118			`locked<='0';`
119
120			`if nxt_sof='0' then`
121			`en_count <='1';`
122			`next_st <= config_state;`
123			`else`
124			`en_count <='0';`
125			`next_st <= pre_config_state;`
126			`end if;`
127
128
129			`when config_state =>`
130
131			`rst_count <='0';`
132			`en_count <='1';`
133
134			`wren <='1';`
135
136			`locked<='0';`
137
138			`if stop_s='1' then`
139			`next_st <= lock_state;`
140			`else`
141			`next_st <= config_state;`
142			`end if;`
143
144			`when lock_state =>`
145
146			`rst_count <='1';`
147			`en_count <='0';`
148
149			`wren <='0';`
150
151			`locked<='1';`
152
153			`if ulock_en='1' then`
154			`next_st <= rst_state;`
155			`else`
156			`next_st <= lock_state;`
157			`end if;`
158
159			`end case;`
160			`end process;`
161
162			`process(clk)`
163			`begin`
164			`if rst_count='1' then`
165			`counter <= "000000";`
166			`else`
167			`if clk'event and clk='1' then`
168			`if en_count='1' then`
169			`counter <= counter + "000001";`
170			`end if;`
171			`end if;`
172			`end if;`
173			`end process;`
174
175			`process(clk)`
176			`begin`
177			`if clk'event and clk='1' then`
178			`if counter = "100101" then`
179			`stop_s <='1';`
180			`else`
181			`stop_s <='0';`
182			`end if;`
183			`end if;`
184			`end process;`
185
186			`process(clk)`
187			`begin`
188			`if clk'event and clk='1' then`
189			`if counter = "010111" then`
190			`wren_checksum_1_t <='1';`
191			`else`
192			`wren_checksum_1_t <='0';`
193			`end if;`
194			`end if;`
195			`end process;`
196
197			`wren_checksum_1 <= wren_checksum_1_t;`
198
199			`process(clk)`
200			`begin`
201			`if clk'event and clk='1' then`
202			`wren_checksum_2 <= wren_checksum_1_t;`
203			`end if;`
204			`end process;`
205
206
207
208			`wraddrlutmem: wraddr_lut_mem Port Map`
209			`(`
210			`clk => clk,`
211			`a=> counter,`
212			`qspo=> addr);`
213
214			`end Behavioral;`
215