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#

# Xilinx Core Generator version K.39

# Date: Sat Feb 12 16:26:42 2011

#

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#

#  This file contains the customisation parameters for a

#  Xilinx CORE Generator IP GUI. It is strongly recommended

#  that you do not manually alter this file as it may cause

#  unexpected and unsupported behavior.

#

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#

# BEGIN Project Options

SET addpads = False

SET asysymbol = False

SET busformat = BusFormatAngleBracketNotRipped

SET createndf = False

SET designentry = VHDL

SET device = xc5vsx95t

SET devicefamily = virtex5

SET flowvendor = Other

SET formalverification = False

SET foundationsym = False

SET implementationfiletype = Ngc

SET package = ff1136

SET removerpms = False

SET simulationfiles = Structural

SET speedgrade = -1

SET verilogsim = False

SET vhdlsim = True

# END Project Options

# BEGIN Select

SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.4

# END Select

# BEGIN Parameters

CSET ce_overrides=ce_overrides_sync_controls

CSET coefficient_file="C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/ipv4_lut.coe"

CSET common_output_ce=false

CSET common_output_clk=false

CSET component_name=dist_mem_64x8

CSET data_width=8

CSET default_data=0

CSET default_data_radix=16

CSET depth=64

CSET dual_port_address=non_registered

CSET dual_port_output_clock_enable=false

CSET input_clock_enable=false

CSET input_options=non_registered

CSET memory_type=single_port_ram

CSET output_options=registered

CSET pipeline_stages=0

CSET qualify_we_with_i_ce=false

CSET reset_qdpo=false

CSET reset_qspo=false

CSET single_port_output_clock_enable=false

CSET sync_reset_qdpo=false

CSET sync_reset_qspo=false

# END Parameters

GENERATE

# CRC: b55d2f1c