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<!--# set var="title" value="pci" -->
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<!--# include virtual="/ssi/ssi_start.shtml" -->
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<b><font size=+2 face="Helvetica, Arial"color=#bf0000>Project Name: PCI bridge</font></b>
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<p><table align=center border=1 cellPadding=2 cellSpacing=0 width="100%" valign="top">
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<tbody><tr bgcolor=#bbccff> <td align=center valign=center>
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<a href="http://www.opencores.org/cores/pci/index.shtml">Introduction</a> |
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<a href="http://www.opencores.org/cores/pci/documentation.shtml">Documentation</a> |
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<a href="http://www.opencores.org/cores/pci/charact.shtml">Characteristics</a> |
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<a href="http://www.opencores.org/cores/pci/current_stat.shtml">Current Status</a> |
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<a href="http://www.opencores.org/cores/pci/todo_list.shtml">To Do list</a> |
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<a href="http://www.opencores.org/cores/pci/test_app.shtml">Test Application</a> |
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<a href="http://www.opencores.org/cores/pci/download.shtml">Download</a> |
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<a href="http://www.opencores.org/cores/pci/testbench.shtml">Testbench</a> |
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<a href="http://www.opencores.org/cores/pci/references.shtml">References</a> |
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<a href="http://www.opencores.org/cores/pci/links.shtml">Links</a> |
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<a href="mailto:pci@opencores.org">Mailing list</a> |
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<a href="http://www.opencores.org/cores/pci/contacts.shtml">Contacts</a>
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</td></tr></tbody>
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</table>
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<table border=0 cellPadding=0 cellSpacing=0 width="100%">
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<tbody><tr><td>
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<p><center><font color="#bf0000" size=+3><b>Introduction</b></font></center>
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</p></td></tr>
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<tr><td align=left>
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<font color="000088"size=+1>
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<b>Description<br>
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</b></font>
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</td></tr>
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<tr><td align=left>
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<font>
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<br>PCI bridge is a member of a family of open source cores. It is a bus bridge device,
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which enables access to PCI bus to other WISHBONE SoC bus compatible cores. Both sides
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of bridge can operate at totaly independent clock frequencies.
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Performance features include 32-bit bus interfaces on both sides, high level of performance
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and flexibility like burst data transfers, memory access optimizing command usage etc.
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<br><br>
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For detailed information refer to related links.
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<br><br>
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</font>
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</td></tr>
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<tr><td align=left>
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<font color="000088"size=+1>
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<b>Purpose of the PCI bridge project<br>
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</b></font>
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</td></tr>
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<tr><td align=left>
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<font>
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<br>
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FIRST: All commercial PCI soft cores, that we noticed, are PCI interfaces. They have different
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backend interfaces. A system designer using PCI interface for some application must also be
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avare of the PCI protocol.<br><br>
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With a PCI bridge a designer considers only the system bus (WISHBONE SoC bus) and can easily
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focus to his application. (It is true, that PCI interfaces occupy less space)<br><br>
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SECOND: We believe that the PCI bridge will be better tested and more imroved because it is an
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open source PCI bridge core.
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<br><br>
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</font>
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</td></tr>
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<tr><td align=left>
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<font color="000088"size=+1>
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<b>What help do we need?<br>
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</b></font>
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</td></tr>
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<tr><td align=left>
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<font>
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<br>There will be testench prepared soon. Fist it will support MEMORY and CONFIG commands.
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Some testcases will be written, but there are so many different possibilities, that every
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help will be needed. Please contact Miha or Tadej.
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<br><br>
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</font>
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</td></tr>
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</table>
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