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<FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>-- Title      : PCI Parity core
</FONT></I><FONT COLOR=red><I>-- Project    : PCI target Core
</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>-- File        : pci_parity.VHD
</FONT></I><FONT COLOR=red><I>-- Author      : Jamil Khatib  <khatib@ieee.org>
</FONT></I><FONT COLOR=red><I>-- Organization: OpenCores Project
</FONT></I><FONT COLOR=red><I>-- Created     : 2000/04/1
</FONT></I><FONT COLOR=red><I>-- Last update : 2000/04/1
</FONT></I><FONT COLOR=red><I>-- Platform    :
</FONT></I><FONT COLOR=red><I>-- Simulators  : Modelsim 5.3XE / Windows98
</FONT></I><FONT COLOR=red><I>-- Synthesizers: webfitter - Leonardo / WindowsNT
</FONT></I><FONT COLOR=red><I>-- Target      : XC9572XL-5-VQ64 - EPF10K100EQC208 Flex10K
</FONT></I><FONT COLOR=red><I>-- Dependency  :
</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>-- Description: PCI Parity Core
</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>-- Copyright (c) 2000 Jamil Khatib
</FONT></I><FONT COLOR=red><I>--
</FONT></I><FONT COLOR=red><I>-- This VHDL design file is an open design; you can redistribute it and/or
</FONT></I><FONT COLOR=red><I>-- modify it and/or implement it under the terms of the Openip General Public
</FONT></I><FONT COLOR=red><I>-- License as it is going to be published by the OpenIPCore Organization and
</FONT></I><FONT COLOR=red><I>-- any coming versions of this license.
</FONT></I><FONT COLOR=red><I>-- You can check the draft license at
</FONT></I><FONT COLOR=red><I>-- http://www.openip.org/oc/license.html
</FONT></I><FONT COLOR=red><I>--
</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>-- Revisions  :
</FONT></I><FONT COLOR=red><I>-- Revision Number : 1
</FONT></I><FONT COLOR=red><I>-- Version         :   1.0
</FONT></I><FONT COLOR=red><I>-- Date            :   1st Apr 2000
</FONT></I><FONT COLOR=red><I>-- Modifier        :   Jamil Khatib (khatib@ieee.org)
</FONT></I><FONT COLOR=red><I>-- Desccription    :   Created
</FONT></I><FONT COLOR=red><I>--
</FONT></I><FONT COLOR=red><I>-- Known bugs      : Extending the PAR signals to wait states
</FONT></I><FONT COLOR=red><I>--                 : SERR is generated upon local side request only
</FONT></I><FONT COLOR=red><I>--                 : PERR must remain active two clockcycles after the ERR
</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=brown><EM>library ieee;
</FONT></EM>
<FONT COLOR=brown><EM>use ieee.std_logic_1164.all;
</FONT></EM>
 
<FONT COLOR=blue><EM>entity parity is
</FONT></EM>
 
  <FONT COLOR=yellow>port</FONT> (
    <FONT COLOR=red><I>-- PCI Interface
 
</FONT></I>    AD           : <FONT COLOR=yellow>in</FONT>    <FONT COLOR=green>std_logic_vector</FONT>(31 <FONT COLOR=yellow>downto</FONT> 0);  <FONT COLOR=red><I>-- PCI AD signal
</FONT></I>    CBE          : <FONT COLOR=yellow>in</FONT>    <FONT COLOR=green>std_logic_vector</FONT>(3 <FONT COLOR=yellow>downto</FONT> 0);  <FONT COLOR=red><I>-- C/BE PCI bus signals
</FONT></I>    PAR          : <FONT COLOR=yellow>inout</FONT> <FONT COLOR=green>std_logic</FONT>;     <FONT COLOR=red><I>-- PAR signal
</FONT></I>    SERR_n       : <FONT COLOR=yellow>inout</FONT> <FONT COLOR=green>std_logic</FONT>;     <FONT COLOR=red><I>-- SERR# signal
</FONT></I>    PERR_n       : <FONT COLOR=yellow>out</FONT>   <FONT COLOR=green>std_logic</FONT>;     <FONT COLOR=red><I>-- PERR# signal
</FONT></I>                                        <FONT COLOR=red><I>-- PERR# signal is output only for target
</FONT></I>    <FONT COLOR=red><I>-- Local Interface
</FONT></I>    ParOperation : <FONT COLOR=yellow>in</FONT>    <FONT COLOR=green>std_logic</FONT>;     <FONT COLOR=red><I>-- Parity Operation
</FONT></I>                                        <FONT COLOR=red><I>-- Drive PAR or check it
</FONT></I>    Par_oe       : <FONT COLOR=yellow>in</FONT>    <FONT COLOR=green>std_logic</FONT>;     <FONT COLOR=red><I>-- PAR Output Enable
</FONT></I>    Locserr_n    : <FONT COLOR=yellow>in</FONT>    <FONT COLOR=green>std_logic</FONT>;     <FONT COLOR=red><I>-- Local System Error
</FONT></I>    LocErrRep_n  : <FONT COLOR=yellow>out</FONT>   <FONT COLOR=green>std_logic</FONT>);    <FONT COLOR=red><I>-- Local Error Report
</FONT></I>                                        <FONT COLOR=red><I>-- used to report parity errors for local interface
</FONT></I>                                        <FONT COLOR=red><I>-- and to the configuration register
</FONT></I>
<FONT COLOR=yellow>end</FONT> parity;
 
<FONT COLOR=brown><EM>library ieee;
</FONT></EM>
<FONT COLOR=brown><EM>use ieee.std_logic_1164.all;
</FONT></EM>
 
</FONT></I><FONT COLOR=blue><EM>architecture behavior of parity is
</FONT></EM>
 
<FONT COLOR=yellow>begin</FONT>  <FONT COLOR=red><I>-- behavior
</FONT></I>
<FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>-- purpose: Parity Generation
</FONT></I><FONT COLOR=red><I>-- type   : sequential
 
</FONT></I><FONT COLOR=red><I>-- outputs: PAR, LocErrRep
</FONT></I>  Paritygen : <FONT COLOR=yellow>process</FONT> (CLK)
 
    <FONT COLOR=yellow>variable</FONT> tmp_par : <FONT COLOR=green>std_logic</FONT>;       <FONT COLOR=red><I>-- temporary parity vriable
</FONT></I>    <FONT COLOR=yellow>variable</FONT> par_q   : <FONT COLOR=green>std_logic</FONT>;       <FONT COLOR=red><I>-- Next Par signal
</FONT></I>    <FONT COLOR=yellow>variable</FONT> perr_q  : <FONT COLOR=green>std_logic</FONT>;       <FONT COLOR=red><I>-- Next PERR signal
</FONT></I>
  <FONT COLOR=yellow>begin</FONT>  <FONT COLOR=red><I>-- process Paritygen
 
    <FONT COLOR=yellow>if</FONT> CLK'event <FONT COLOR=yellow>and</FONT> CLK = '1' <FONT COLOR=yellow>then</FONT>     <FONT COLOR=red><I>-- rising clock edge
</FONT></I>      <FONT COLOR=yellow>if</FONT> Par_oe = '1' <FONT COLOR=yellow>then</FONT>
 
<FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>--      PAR signal states:
</FONT></I><FONT COLOR=red><I>--      Idel: when no operation on the current target or master
</FONT></I><FONT COLOR=red><I>--          PAR = 'Z' , PERR = 'Z'
</FONT></I><FONT COLOR=red><I>--      Master Read:
 
</FONT></I><FONT COLOR=red><I>--                 Master Drives PAR
</FONT></I><FONT COLOR=red><I>--                 Target Drives PERR
</FONT></I><FONT COLOR=red><I>--        Data phase:
</FONT></I><FONT COLOR=red><I>--                 Target Drives PAR
</FONT></I><FONT COLOR=red><I>--                 Master Drives PERR
</FONT></I><FONT COLOR=red><I>--      Master write:
</FONT></I><FONT COLOR=red><I>--        Address and data phase
</FONT></I><FONT COLOR=red><I>--                 Master Drives PAR
</FONT></I><FONT COLOR=red><I>--                 Master Drives PERR
</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=red><I>--      ParOperation = 1 Calculate and drive PAR Port
</FONT></I><FONT COLOR=red><I>--      ParOperation = 0 Calculate and report Parity Errors
</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I>        <FONT COLOR=yellow>if</FONT> ParOperation = '1' <FONT COLOR=yellow>then</FONT>      <FONT COLOR=red><I>-- Drive PAR signal
</FONT></I>
          PAR         <= par_q;
          LocErrRep_n <= perr_q;
          PERR_n <= 'Z';
 
        <FONT COLOR=yellow>else</FONT>
 
          PERR_n <= perr_q;
          PAR <= 'Z';
 
 
 
 
</FONT></I>        tmp_par := CBE(3) <FONT COLOR=yellow>xor</FONT> CBE(2) <FONT COLOR=yellow>xor</FONT> CBE(1) <FONT COLOR=yellow>xor</FONT> CBE(0);
 
 
 
 
 
        <FONT COLOR=yellow>end</FONT> <FONT COLOR=yellow>loop</FONT>;  <FONT COLOR=red><I>-- i
 
        par_q := tmp_par;
 
        perr_q := tmp_par <FONT COLOR=yellow>xor</FONT> PAR_q;
 
      <FONT COLOR=yellow>else</FONT>
 
        PAR    <= 'Z';
 
 
 
    <FONT COLOR=yellow>end</FONT> <FONT COLOR=yellow>if</FONT>;
 
<FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I>
 
<FONT COLOR=red><I>-------------------------------------------------------------------------------
</FONT></I><FONT COLOR=yellow>end</FONT> behavior;
</PRE>
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Line No.	Rev	Author	Line
1	156	root	`<HTML>`
2			`<BODY>`
3			`<PRE>`
4			`<FONT COLOR=red><I>-------------------------------------------------------------------------------`
5			`</FONT></I><FONT COLOR=red><I>-- Title : PCI Parity core`
6			`</FONT></I><FONT COLOR=red><I>-- Project : PCI target Core`
7			`</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------`
8			`</FONT></I><FONT COLOR=red><I>-- File : pci_parity.VHD`
9			`</FONT></I><FONT COLOR=red><I>-- Author : Jamil Khatib <khatib@ieee.org>`
10			`</FONT></I><FONT COLOR=red><I>-- Organization: OpenCores Project`
11			`</FONT></I><FONT COLOR=red><I>-- Created : 2000/04/1`
12			`</FONT></I><FONT COLOR=red><I>-- Last update : 2000/04/1`
13			`</FONT></I><FONT COLOR=red><I>-- Platform :`
14			`</FONT></I><FONT COLOR=red><I>-- Simulators : Modelsim 5.3XE / Windows98`
15			`</FONT></I><FONT COLOR=red><I>-- Synthesizers: webfitter - Leonardo / WindowsNT`
16			`</FONT></I><FONT COLOR=red><I>-- Target : XC9572XL-5-VQ64 - EPF10K100EQC208 Flex10K`
17			`</FONT></I><FONT COLOR=red><I>-- Dependency :`
18			`</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------`
19			`</FONT></I><FONT COLOR=red><I>-- Description: PCI Parity Core`
20			`</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------`
21			`</FONT></I><FONT COLOR=red><I>-- Copyright (c) 2000 Jamil Khatib`
22			`</FONT></I><FONT COLOR=red><I>--`
23			`</FONT></I><FONT COLOR=red><I>-- This VHDL design file is an open design; you can redistribute it and/or`
24			`</FONT></I><FONT COLOR=red><I>-- modify it and/or implement it under the terms of the Openip General Public`
25			`</FONT></I><FONT COLOR=red><I>-- License as it is going to be published by the OpenIPCore Organization and`
26			`</FONT></I><FONT COLOR=red><I>-- any coming versions of this license.`
27			`</FONT></I><FONT COLOR=red><I>-- You can check the draft license at`
28			`</FONT></I><FONT COLOR=red><I>-- http://www.openip.org/oc/license.html`
29			`</FONT></I><FONT COLOR=red><I>--`
30			`</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------`
31			`</FONT></I><FONT COLOR=red><I>-- Revisions :`
32			`</FONT></I><FONT COLOR=red><I>-- Revision Number : 1`
33			`</FONT></I><FONT COLOR=red><I>-- Version : 1.0`
34			`</FONT></I><FONT COLOR=red><I>-- Date : 1st Apr 2000`
35			`</FONT></I><FONT COLOR=red><I>-- Modifier : Jamil Khatib (khatib@ieee.org)`
36			`</FONT></I><FONT COLOR=red><I>-- Desccription : Created`
37			`</FONT></I><FONT COLOR=red><I>--`
38			`</FONT></I><FONT COLOR=red><I>-- Known bugs : Extending the PAR signals to wait states`
39			`</FONT></I><FONT COLOR=red><I>-- : SERR is generated upon local side request only`
40			`</FONT></I><FONT COLOR=red><I>-- : PERR must remain active two clockcycles after the ERR`
41			`</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------`
42			`</FONT></I><FONT COLOR=brown><EM>library ieee; </FONT></EM>`
43			`<FONT COLOR=brown><EM>use ieee.std_logic_1164.all; </FONT></EM>`
44
45			`<FONT COLOR=blue><EM>entity parity is </FONT></EM>`
46
47			`<FONT COLOR=yellow>port</FONT> (`
48			`<FONT COLOR=red><I>-- PCI Interface`
49
50			`</FONT></I> AD : <FONT COLOR=yellow>in</FONT> <FONT COLOR=green>std_logic_vector</FONT>(31 <FONT COLOR=yellow>downto</FONT> 0); <FONT COLOR=red><I>-- PCI AD signal`
51			`</FONT></I> CBE : <FONT COLOR=yellow>in</FONT> <FONT COLOR=green>std_logic_vector</FONT>(3 <FONT COLOR=yellow>downto</FONT> 0); <FONT COLOR=red><I>-- C/BE PCI bus signals`
52			`</FONT></I> PAR : <FONT COLOR=yellow>inout</FONT> <FONT COLOR=green>std_logic</FONT>; <FONT COLOR=red><I>-- PAR signal`
53			`</FONT></I> SERR_n : <FONT COLOR=yellow>inout</FONT> <FONT COLOR=green>std_logic</FONT>; <FONT COLOR=red><I>-- SERR# signal`
54			`</FONT></I> PERR_n : <FONT COLOR=yellow>out</FONT> <FONT COLOR=green>std_logic</FONT>; <FONT COLOR=red><I>-- PERR# signal`
55			`</FONT></I> <FONT COLOR=red><I>-- PERR# signal is output only for target`
56			`</FONT></I> <FONT COLOR=red><I>-- Local Interface`
57			`</FONT></I> ParOperation : <FONT COLOR=yellow>in</FONT> <FONT COLOR=green>std_logic</FONT>; <FONT COLOR=red><I>-- Parity Operation`
58			`</FONT></I> <FONT COLOR=red><I>-- Drive PAR or check it`
59			`</FONT></I> Par_oe : <FONT COLOR=yellow>in</FONT> <FONT COLOR=green>std_logic</FONT>; <FONT COLOR=red><I>-- PAR Output Enable`
60			`</FONT></I> Locserr_n : <FONT COLOR=yellow>in</FONT> <FONT COLOR=green>std_logic</FONT>; <FONT COLOR=red><I>-- Local System Error`
61			`</FONT></I> LocErrRep_n : <FONT COLOR=yellow>out</FONT> <FONT COLOR=green>std_logic</FONT>); <FONT COLOR=red><I>-- Local Error Report`
62			`</FONT></I> <FONT COLOR=red><I>-- used to report parity errors for local interface`
63			`</FONT></I> <FONT COLOR=red><I>-- and to the configuration register`
64			`</FONT></I>`
65			`<FONT COLOR=yellow>end</FONT> parity;`
66
67			`<FONT COLOR=brown><EM>library ieee; </FONT></EM>`
68			`<FONT COLOR=brown><EM>use ieee.std_logic_1164.all; </FONT></EM>`
69
70			`</FONT></I><FONT COLOR=blue><EM>architecture behavior of parity is </FONT></EM>`
71
72			`<FONT COLOR=yellow>begin</FONT> <FONT COLOR=red><I>-- behavior`
73			`</FONT></I>`
74			`<FONT COLOR=red><I>-------------------------------------------------------------------------------`
75			`</FONT></I><FONT COLOR=red><I>-- purpose: Parity Generation`
76			`</FONT></I><FONT COLOR=red><I>-- type : sequential`
77
78			`</FONT></I><FONT COLOR=red><I>-- outputs: PAR, LocErrRep`
79			`</FONT></I> Paritygen : <FONT COLOR=yellow>process</FONT> (CLK)`
80
81			`<FONT COLOR=yellow>variable</FONT> tmp_par : <FONT COLOR=green>std_logic</FONT>; <FONT COLOR=red><I>-- temporary parity vriable`
82			`</FONT></I> <FONT COLOR=yellow>variable</FONT> par_q : <FONT COLOR=green>std_logic</FONT>; <FONT COLOR=red><I>-- Next Par signal`
83			`</FONT></I> <FONT COLOR=yellow>variable</FONT> perr_q : <FONT COLOR=green>std_logic</FONT>; <FONT COLOR=red><I>-- Next PERR signal`
84			`</FONT></I>`
85			`<FONT COLOR=yellow>begin</FONT> <FONT COLOR=red><I>-- process Paritygen`
86
87			`<FONT COLOR=yellow>if</FONT> CLK'event <FONT COLOR=yellow>and</FONT> CLK = '1' <FONT COLOR=yellow>then</FONT> <FONT COLOR=red><I>-- rising clock edge`
88			`</FONT></I> <FONT COLOR=yellow>if</FONT> Par_oe = '1' <FONT COLOR=yellow>then</FONT>`
89
90			`<FONT COLOR=red><I>-------------------------------------------------------------------------------`
91			`</FONT></I><FONT COLOR=red><I>-- PAR signal states:`
92			`</FONT></I><FONT COLOR=red><I>-- Idel: when no operation on the current target or master`
93			`</FONT></I><FONT COLOR=red><I>-- PAR = 'Z' , PERR = 'Z'`
94			`</FONT></I><FONT COLOR=red><I>-- Master Read:`
95
96			`</FONT></I><FONT COLOR=red><I>-- Master Drives PAR`
97			`</FONT></I><FONT COLOR=red><I>-- Target Drives PERR`
98			`</FONT></I><FONT COLOR=red><I>-- Data phase:`
99			`</FONT></I><FONT COLOR=red><I>-- Target Drives PAR`
100			`</FONT></I><FONT COLOR=red><I>-- Master Drives PERR`
101			`</FONT></I><FONT COLOR=red><I>-- Master write:`
102			`</FONT></I><FONT COLOR=red><I>-- Address and data phase`
103			`</FONT></I><FONT COLOR=red><I>-- Master Drives PAR`
104			`</FONT></I><FONT COLOR=red><I>-- Master Drives PERR`
105			`</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------`
106			`</FONT></I><FONT COLOR=red><I>-- ParOperation = 1 Calculate and drive PAR Port`
107			`</FONT></I><FONT COLOR=red><I>-- ParOperation = 0 Calculate and report Parity Errors`
108			`</FONT></I><FONT COLOR=red><I>-------------------------------------------------------------------------------`
109			`</FONT></I> <FONT COLOR=yellow>if</FONT> ParOperation = '1' <FONT COLOR=yellow>then</FONT> <FONT COLOR=red><I>-- Drive PAR signal`
110			`</FONT></I>`
111			`PAR <= par_q;`
112			`LocErrRep_n <= perr_q;`
113			`PERR_n <= 'Z';`
114
115			`<FONT COLOR=yellow>else</FONT>`
116
117			`PERR_n <= perr_q;`
118			`PAR <= 'Z';`
119
120
121
122
123			`</FONT></I> tmp_par := CBE(3) <FONT COLOR=yellow>xor</FONT> CBE(2) <FONT COLOR=yellow>xor</FONT> CBE(1) <FONT COLOR=yellow>xor</FONT> CBE(0);`
124
125
126
127
128
129			`<FONT COLOR=yellow>end</FONT> <FONT COLOR=yellow>loop</FONT>; <FONT COLOR=red><I>-- i`
130
131			`par_q := tmp_par;`
132
133			`perr_q := tmp_par <FONT COLOR=yellow>xor</FONT> PAR_q;`
134
135			`<FONT COLOR=yellow>else</FONT>`
136
137			`PAR <= 'Z';`
138
139
140
141			`<FONT COLOR=yellow>end</FONT> <FONT COLOR=yellow>if</FONT>;`
142
143			`<FONT COLOR=red><I>-------------------------------------------------------------------------------`
144			`</FONT></I>`
145
146			`<FONT COLOR=red><I>-------------------------------------------------------------------------------`
147			`</FONT></I><FONT COLOR=yellow>end</FONT> behavior;`
148			`</PRE>`
149			`</BODY>`
150			`</HTML>`
151

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