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Lord_Nelso |
--+------------------------------------------------------------------+
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--| |
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--| PCI_TARGET -> Wishbone_MASTER interface (PCI_to_WB) v1.9 |
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--| |
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--| The first, original PCI module is from: |
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--| Ben Jackson, http://www.ben.com/minipci/verilog.php |
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--| |
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--| The second, modified module "pci_mini" is from: |
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--| Istvan Nagy, buenos@freemail.hu |
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--| |
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--| |
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--| DOWNLOADED FROM OPENCORES. License = LGPL. |
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--| |
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--+------------------------------------------------------------------+
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--| I used the code of the original pci_mini module to create |
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--| a PCI to WB interface with direct read accesses (not |
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--| like before, where data would be available only on |
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--| a second PCI read) because that didn't work in my system. |
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--| Thanks to Ben Jackson and Istvan Nagy for their works! |
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--| I would not have been able to design such a core without |
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--| the provided code base. |
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--| Nelson Scheja (Lord_Nelson@opencores.org). |
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--+------------------------------------------------------------------+----------------------------+
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-- ########## General info ##########
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-- The core implements a 16 MB memory image which is relocable on the WB bus:
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-- WB_address = 4 * baseaddr + PCI_addr[23:2], where baseaddr is the WB image relocation
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-- register (BAR0).
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-- Only Dword aligned Dword accesses are allowed on the PCI. This way we can have access to the
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-- full 32 bit WB address space through a 16 MB PCI window. The addressing on the WB bus is
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-- Dword addressing, while on the PCI bus, it is byte addressing: PCI_addr / 4 = WB_address.
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-- That means, when the PCI address is increasing by 4 ( = 4 Bytes = 1 Dword), the WB address
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-- is increasing by 1 ( = 1 Dword, too).
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-- Nearly full Wishbone compatible; single exception is master arbitration (through signals
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-- wb_req and wb_gnt) which is not implemented.
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-- (Remember, most PCI signals are active low, so I call them "asserted" when they are 0!
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-- Only exceptions are clk, idsel and par, which are active high.)
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-- The duration of a complete PCI cycle depends on the PCI command and the reaction time of the
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-- PCI master and the addressed WB slave. Generally, Memory Reads need the most time to complete
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-- (as the data path is the longest), and Config Writes are fastest.
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-- ########## PCI bus support ##########
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-- Intended PCI operation mode is 33 MHz, 32 bit.
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-- Supported PCI commands are Config Read / Write, Memory Read / Write. Only single Dword
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-- accesses are supported. (As the cbe bits are ignored for MemRead and MemWrite, a full DWord
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-- is always transferred on these commands. Still, Byte or Word accesses are not recommended.)
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-- The core supports only single reads / writes, that means only one data phase per PCI
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-- cycle. Bursts are not allowed. In the first data phase, it asserts the stop signal
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-- together with trdy to enforce a so-called "target initiated disconnect". This makes sure
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-- that the PCI master will never try to extend a cycle past the first data phase.
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-- When no WB response has been sent for WB_MAX_LAT clock cycles during a MemRead or MemWrite,
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-- the core signals "Target-Abort" to the master. WB_MAX_LAT is user-definable in the range
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-- from 0h to Fh.
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-- DEVSEL timing is "fast". That means, devsel will be asserted the next clock edge after the
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-- assertion of frame.
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-- Parity of outgoing data is generated (one clock cycle after driving the ad lines). Parity
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-- check of incoming address/data is not implemented. Thus, perr is held in high impedance the
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-- whole time.
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-- System Error indication is not implemented, thus serr is high impedance the whole time.
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-- ########## Wishbone bus support ##########
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-- Implemented Wishbone signals: wb_adr_o, wb_dat_o, wb_dat_i, wb_sel_o, wb_cyc_o, wb_stb_o,
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-- wb_we_o, wb_ack_i, wb_err_i.
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-- Not implemented Wishbone signals: clk, rst, rty, req, gnt, lock, stall, tag signals.
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-- The signals wb_rst and wb_clk are not generated as this is actually the job of the Syscon
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-- module and should be done outside this core. Still, it could come in handy to use the core
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-- also as Syscon, so these two ports and their processes are only commented out and can be
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-- quickly reactivated if necessary.
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-- Attention! The core was intended for a Wishbone bus scenario where it is the only master.
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-- Thus, no arbitration methods are supported, which actually is not 100% WB compatible. Do not
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-- put another master on the same WB bus as this core! The advantage is fewer logic units and
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-- faster bus cycles (because the core asserts wb_cyc and wb_stb at the same time and doesn't
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-- have to wait for a grant in between).
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-- Supported commands are single read / write. Pipelined mode is not supported.
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-- All bits of the signal wb_sel are always driven high during normal operation because all WB
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-- accesses use 4 Bytes. Only when reset is asserted, wb_sel = 0000.
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-- ########## Device Compatibility ##########
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-- The core was tested and used on a Xilinx Spartan3 XC3S1000 FT256-4. The PCI master was a
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-- MPC5200 microcontroller.
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-- There are no Xilinx-specific components defined in the code, so theoretically it should be
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-- compatible to FPGAs of all developers.
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-- Utilization (extract from Xilinx ISE Map Report): Slices 183; Slice Reg 143; LUTs 194.
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-- The IEEE library numeric_std is used.
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-- ########## Change log ##########
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-- Merged PCI state machine, WB state machine and Address decoder into a single big process to
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-- allow faster PCI reaction and reduce amount of signals.
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-- Made the interrupt asynchronously to clk to ensure fastest possible interrupt generation.
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-- In Config cycles, it is now paid attention to the Byte Enable bits cbe.
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-- Target-Abort is generated when no response (ack or err) has come from the Wishbone for
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-- WB_MAX_LAT clock cycles.
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-- Completely modified the internal structure of the config signals.
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-- Made the interrupt port information configurable via generic.
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-- Removed everything that's got to do with interrupts, as an INTA pin is not mandatory for PCI
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-- and WB has no definition of an interrupt request protocol.
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-- Realized main_state signal (formerly pci_state) as an enum type and let it also control all
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-- the sub states (deleted former sub_state).
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-- ########## ToDos / Problems ##########
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-- Implement parity check?
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-- Implement WB byte select?
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-- Check WB Timeout counter accuracy! Don't know whether the cycle count is perfectly correct.
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-- Assertion of trdy and stop lasts for about 10 clock cycles when scoped in reality! Reason
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-- unclear, maybe an effect due to the slow pullups?
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-- Uncorrect handling of wb_err assertion (it seems)! Stop isn't asserted sometimes.
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--+-----------------------------------------------------------------------------------------------+
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library ieee;
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use ieee.STD_LOGIC_1164.all;
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use ieee.numeric_std.all;
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entity pci_to_wb is
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port(
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--PCI signals
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reset : in std_logic;
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clk : in std_logic;
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frame : in std_logic;
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irdy : in std_logic;
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trdy : out std_logic;
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devsel : out std_logic;
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idsel : in std_logic;
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ad : inout std_logic_vector(31 downto 0) := (others => 'Z');
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cbe : in std_logic_vector(3 downto 0);
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par : inout std_logic := 'Z';
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stop : out std_logic;
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serr : out std_logic;
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perr : out std_logic;
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--Wishbone signals
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-- wb_clk_o : out std_logic; --uncomment these two signals and their corresponding processes at the
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-- wb_rst_o : out std_logic; --beginning of the architecture body to achieve syscon functionality
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wb_adr_o : out std_logic_vector(31 downto 0);
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wb_dat_o : out std_logic_vector(31 downto 0);
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wb_dat_i : in std_logic_vector(31 downto 0);
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wb_sel_o : out std_logic_vector(3 downto 0) := "0000";
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wb_cyc_o : out std_logic := '0';
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wb_stb_o : out std_logic := '0';
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wb_we_o : out std_logic := '0';
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wb_ack_i : in std_logic;
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wb_err_i : in std_logic
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);
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end pci_to_wb;
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architecture Behavioral of pci_to_wb is
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--+------------------------------------------------------------------------------------+
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--| Constants |
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--+------------------------------------------------------------------------------------+
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--user specific constants. Change them at your will.
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constant DEVICE_ID : std_logic_vector := x"1337"; --It's leet. Yo.
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constant VENDOR_ID : std_logic_vector := x"1234";
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constant DEVICE_CLASS : std_logic_vector := x"118000"; --(068000=bridge/other, 078000=simple_comm_contr/other, 118000=data_acquisition/other)
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constant DEVICE_REV : std_logic_vector := x"09"; --version of the PCI to WB module
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constant SUBSYSTEM_ID : std_logic_vector := x"0001"; --card identifier
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constant SUBSYSTEM_VENDOR_ID : std_logic_vector := x"9876";
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constant WB_MAX_LAT : unsigned := x"4"; --defines how many clock cycles the WB has time to answer to wb_stb before Target-Abort is activated
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-- supported PCI commands
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constant CFGREAD : std_logic_vector := "1010";
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constant CFGWRITE : std_logic_vector := "1011";
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constant MEMREAD : std_logic_vector := "0110";
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constant MEMWRITE : std_logic_vector := "0111";
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--+------------------------------------------------------------------------------------+
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--| Internal signals |
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--+------------------------------------------------------------------------------------+
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-- state machine flow
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type main_state_type is (Idle, Cfg_read_1, Cfg_read_2, Cfg_write_1, Cfg_write_2,
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Mem_read_1, Mem_read_2, Mem_read_3, Mem_write_1, Mem_write_2, Mem_write_3);
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signal main_state : main_state_type := Idle;
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signal wait_count : unsigned(3 downto 0) := x"0"; --counts up to WB_MAX_LAT while waiting on WB response
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signal par_create : std_logic := '0'; --controls the parity generator: when 1, parity is generated, else not
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signal pci_address : std_logic_vector(23 downto 2); --latch of AD lines during the address phase (upper 8 and lower 2 of the 32 bits are never used)
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-- configuration registers
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signal cfg_reg_0x00 : std_logic_vector(31 downto 0) := DEVICE_ID & VENDOR_ID;
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signal cfg_reg_0x04 : std_logic_vector(31 downto 0) := x"00000000";
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alias target_abort : std_logic is cfg_reg_0x04(27); --Target-Abort status bit (status register)
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alias mem_ena : std_logic is cfg_reg_0x04(1); --memory space enable bit (command register)
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signal cfg_reg_0x08 : std_logic_vector(31 downto 0) := DEVICE_CLASS & DEVICE_REV;
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signal cfg_reg_0x10 : std_logic_vector(31 downto 0) := x"00000000";
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alias baseaddr : std_logic_vector(7 downto 0) is cfg_reg_0x10(31 downto 24); --used for relocating the WB address space
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signal cfg_reg_0x2c : std_logic_vector(31 downto 0) := SUBSYSTEM_ID & SUBSYSTEM_VENDOR_ID;
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begin
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--+------------------------------------------------------------------------------------+
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--| Small signal processes |
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--+------------------------------------------------------------------------------------+
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--Wishbone clock and (asynchronous) reset:
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-- wb_clk_o <= clk; --uncomment these two processes and their corresponding
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-- wb_rst_o <= not reset; --signals in the entity to achieve syscon functionality
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--these are not used:
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serr <= 'Z';
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perr <= 'Z';
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--only dword accesses, so wb_sel can always be high (except during reset):
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process(reset)
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begin
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if reset = '0' then
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wb_sel_o <= "0000";
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else
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wb_sel_o <= "1111";
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end if;
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end process;
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--+------------------------------------------------------------------------------------+
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--| MAIN STATE MACHINE |
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--+------------------------------------------------------------------------------------+
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-- This process controls the translation from PCI protocol to Wishbone protocol.
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-- It is realized as a state machine with five main states (defined with main_state).
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-- Most main states are further divided into sub states (defined with sub_state)
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-- to control the flow of execution during a PCI cycle.
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process(reset, clk)
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begin
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if reset = '0' then
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main_state <= Idle;
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ad <= (others => 'Z');
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devsel <= 'Z';
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trdy <= 'Z';
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stop <= 'Z';
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par_create <= '0';
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wait_count <= (others => '0');
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target_abort<= '0';
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mem_ena <= '0';
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baseaddr <= (others => '0');
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wb_adr_o <= (others => '0');
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wb_dat_o <= (others => '0');
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wb_cyc_o <= '0';
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wb_stb_o <= '0';
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wb_we_o <= '0';
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elsif rising_edge(clk) then
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case main_state is
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-- ########## IDLE STATE ##########
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-- State for between PCI cycles and during the address phase (which is identified by the
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-- assertion of frame). While here, all signals to PCI, WB and internals are in deasserted
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-- state. When the core is being addressed correctly by the PCI master, it asserts devsel
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-- as response and changes to the state defined by the command bits (cbe).
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when Idle =>
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trdy <= 'Z';
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stop <= 'Z';
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devsel <= 'Z';
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if frame = '0' then
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pci_address <= ad(23 downto 2);
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if idsel = '1' and ad(10 downto 8) = "000" and ad(1 downto 0) = "00" then --correct config space access
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if cbe = CFGREAD then
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devsel <= '0';
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main_state <= Cfg_read_1;
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elsif cbe = CFGWRITE then
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devsel <= '0';
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main_state <= Cfg_write_1;
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end if;
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elsif mem_ena = '1' and ad(31 downto 24) = baseaddr then --correct memory space access
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if cbe = MEMREAD then
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devsel <= '0';
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main_state <= Mem_read_1;
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elsif cbe = MEMWRITE then
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devsel <= '0';
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main_state <= Mem_write_1;
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end if;
|
| 305 |
|
|
end if;
|
| 306 |
|
|
end if;
|
| 307 |
|
|
|
| 308 |
|
|
|
| 309 |
|
|
-- ########## CFG READ STATE ##########
|
| 310 |
|
|
-- The config register at the DWord address pci_address is read. Depending on the Byte Enables
|
| 311 |
|
|
-- cbe, the data is provided on ad When cbe(0) = 0, then byte 0 is all zeroes, etc. One
|
| 312 |
|
|
-- clock cycle later, the parity is provided and the PCI cycle is terminated.
|
| 313 |
|
|
|
| 314 |
|
|
--STAGE 1: gather register data internally in the first clock cycle where irdy is asserted
|
| 315 |
|
|
when Cfg_read_1 =>
|
| 316 |
|
|
if irdy = '0' then
|
| 317 |
|
|
case pci_address(7 downto 2) is
|
| 318 |
|
|
when "000000" => --0d*4 = 00h. Device ID (31 - 16), Vendor ID (15 - 0).
|
| 319 |
|
|
if cbe(3) = '0' then
|
| 320 |
|
|
ad(31 downto 24) <= cfg_reg_0x00(31 downto 24);
|
| 321 |
|
|
else
|
| 322 |
|
|
ad(31 downto 24) <= (others => '0');
|
| 323 |
|
|
end if;
|
| 324 |
|
|
if cbe(2) = '0' then
|
| 325 |
|
|
ad(23 downto 16) <= cfg_reg_0x00(23 downto 16);
|
| 326 |
|
|
else
|
| 327 |
|
|
ad(23 downto 16) <= (others => '0');
|
| 328 |
|
|
end if;
|
| 329 |
|
|
if cbe(1) = '0' then
|
| 330 |
|
|
ad(15 downto 8) <= cfg_reg_0x00(15 downto 8);
|
| 331 |
|
|
else
|
| 332 |
|
|
ad(15 downto 8) <= (others => '0');
|
| 333 |
|
|
end if;
|
| 334 |
|
|
if cbe(0) = '0' then
|
| 335 |
|
|
ad(7 downto 0) <= cfg_reg_0x00(7 downto 0);
|
| 336 |
|
|
else
|
| 337 |
|
|
ad(7 downto 0) <= (others => '0');
|
| 338 |
|
|
end if;
|
| 339 |
|
|
when "000001" => --1d*4 = 04h. Status (31 - 16), Command (15 - 0).
|
| 340 |
|
|
if cbe(3) = '0' then
|
| 341 |
|
|
ad(31 downto 24) <= cfg_reg_0x04(31 downto 24);
|
| 342 |
|
|
else
|
| 343 |
|
|
ad(31 downto 24) <= (others => '0');
|
| 344 |
|
|
end if;
|
| 345 |
|
|
ad(23 downto 8) <= (others => '0');
|
| 346 |
|
|
if cbe(0) = '0' then
|
| 347 |
|
|
ad(7 downto 0) <= cfg_reg_0x04(7 downto 0);
|
| 348 |
|
|
else
|
| 349 |
|
|
ad(7 downto 0) <= (others => '0');
|
| 350 |
|
|
end if;
|
| 351 |
|
|
when "000010" => --2d*4 = 08h. Class Code (31 - 8), Revision ID (7 - 0).
|
| 352 |
|
|
if cbe(3) = '0' then
|
| 353 |
|
|
ad(31 downto 24) <= cfg_reg_0x08(31 downto 24);
|
| 354 |
|
|
else
|
| 355 |
|
|
ad(31 downto 24) <= (others => '0');
|
| 356 |
|
|
end if;
|
| 357 |
|
|
if cbe(2) = '0' then
|
| 358 |
|
|
ad(23 downto 16) <= cfg_reg_0x08(23 downto 16);
|
| 359 |
|
|
else
|
| 360 |
|
|
ad(23 downto 16) <= (others => '0');
|
| 361 |
|
|
end if;
|
| 362 |
|
|
if cbe(1) = '0' then
|
| 363 |
|
|
ad(15 downto 8) <= cfg_reg_0x08(15 downto 8);
|
| 364 |
|
|
else
|
| 365 |
|
|
ad(15 downto 8) <= (others => '0');
|
| 366 |
|
|
end if;
|
| 367 |
|
|
if cbe(0) = '0' then
|
| 368 |
|
|
ad(7 downto 0) <= cfg_reg_0x08(7 downto 0);
|
| 369 |
|
|
else
|
| 370 |
|
|
ad(7 downto 0) <= (others => '0');
|
| 371 |
|
|
end if;
|
| 372 |
|
|
when "000100" => --4d*4 = 10h. Base Address Register 0, = baseaddr.
|
| 373 |
|
|
if cbe(3) = '0' then
|
| 374 |
|
|
ad(31 downto 24) <= cfg_reg_0x10(31 downto 24);
|
| 375 |
|
|
else
|
| 376 |
|
|
ad(31 downto 24) <= (others => '0');
|
| 377 |
|
|
end if;
|
| 378 |
|
|
ad(23 downto 0) <= (others => '0');
|
| 379 |
|
|
when "001011" => --11d*4 = 2Ch. Subsystem ID (31 - 16), Subsystem Vendor ID (15 - 0).
|
| 380 |
|
|
if cbe(3) = '0' then
|
| 381 |
|
|
ad(31 downto 24) <= cfg_reg_0x2c(31 downto 24);
|
| 382 |
|
|
else
|
| 383 |
|
|
ad(31 downto 24) <= (others => '0');
|
| 384 |
|
|
end if;
|
| 385 |
|
|
if cbe(2) = '0' then
|
| 386 |
|
|
ad(23 downto 16) <= cfg_reg_0x2c(23 downto 16);
|
| 387 |
|
|
else
|
| 388 |
|
|
ad(23 downto 16) <= (others => '0');
|
| 389 |
|
|
end if;
|
| 390 |
|
|
if cbe(1) = '0' then
|
| 391 |
|
|
ad(15 downto 8) <= cfg_reg_0x2c(15 downto 8);
|
| 392 |
|
|
else
|
| 393 |
|
|
ad(15 downto 8) <= (others => '0');
|
| 394 |
|
|
end if;
|
| 395 |
|
|
if cbe(0) = '0' then
|
| 396 |
|
|
ad(7 downto 0) <= cfg_reg_0x2c(7 downto 0);
|
| 397 |
|
|
else
|
| 398 |
|
|
ad(7 downto 0) <= (others => '0');
|
| 399 |
|
|
end if;
|
| 400 |
|
|
when others => --unsupported or reserved config registers.
|
| 401 |
|
|
ad <= (others => '0');
|
| 402 |
|
|
end case;
|
| 403 |
|
|
|
| 404 |
|
|
trdy <= '0';
|
| 405 |
|
|
stop <= '0';
|
| 406 |
|
|
par_create <= '1';
|
| 407 |
|
|
main_state <= Cfg_read_2;
|
| 408 |
|
|
end if;
|
| 409 |
|
|
|
| 410 |
|
|
--STAGE 2: one clock cycle later, end the PCI cycle
|
| 411 |
|
|
when Cfg_read_2 =>
|
| 412 |
|
|
ad <= (others => 'Z');
|
| 413 |
|
|
devsel <= '1';
|
| 414 |
|
|
trdy <= '1';
|
| 415 |
|
|
stop <= '1';
|
| 416 |
|
|
par_create <= '0';
|
| 417 |
|
|
main_state <= Idle;
|
| 418 |
|
|
|
| 419 |
|
|
|
| 420 |
|
|
-- ########## CFG WRITE STATE ##########
|
| 421 |
|
|
-- The config register at the DWord address pci_address is written, depending on the Byte Enables
|
| 422 |
|
|
-- cbe. Some bits are not writable, so nothing will be changed then. The status register
|
| 423 |
|
|
-- is special: When writing a 1 onto a bit, this bit is cleared; writing a 0 will have no
|
| 424 |
|
|
-- effect. One clock cycle later, the PCI cycle is terminated.
|
| 425 |
|
|
|
| 426 |
|
|
-- STAGE 1: return config values in the first clock cycle where irdy is asserted
|
| 427 |
|
|
when Cfg_write_1 =>
|
| 428 |
|
|
trdy <= '0';
|
| 429 |
|
|
stop <= '0';
|
| 430 |
|
|
if irdy = '0' then
|
| 431 |
|
|
case pci_address(7 downto 2) is
|
| 432 |
|
|
when "000001" => --1d*4 = 04h. Status (31 - 16), Command (15 - 0).
|
| 433 |
|
|
if cbe(3) = '0' and ad(27) = '1' then
|
| 434 |
|
|
target_abort<= '0'; --reset status bit Target-Abort when writing a 1 there
|
| 435 |
|
|
end if;
|
| 436 |
|
|
if cbe(0) = '0' then
|
| 437 |
|
|
mem_ena <= ad(1);
|
| 438 |
|
|
end if;
|
| 439 |
|
|
when "000100" => --4d*4 = 10h. Base Address Register 0 (BAR0).
|
| 440 |
|
|
if cbe(3) = '0' then
|
| 441 |
|
|
baseaddr <= ad(31 downto 24);
|
| 442 |
|
|
end if;
|
| 443 |
|
|
when others => --config registers that are reserved, unsupported or don't support writes.
|
| 444 |
|
|
null;
|
| 445 |
|
|
end case;
|
| 446 |
|
|
main_state <= Cfg_write_2;
|
| 447 |
|
|
end if;
|
| 448 |
|
|
|
| 449 |
|
|
--STAGE 2: one clock cycle later, end the PCI cycle
|
| 450 |
|
|
when Cfg_write_2 =>
|
| 451 |
|
|
devsel <= '1';
|
| 452 |
|
|
trdy <= '1';
|
| 453 |
|
|
stop <= '1';
|
| 454 |
|
|
main_state <= Idle;
|
| 455 |
|
|
|
| 456 |
|
|
|
| 457 |
|
|
-- ########## MEM READ STATE ##########
|
| 458 |
|
|
-- The data to be written and the address is provided for the Wishbone bus. Then,
|
| 459 |
|
|
-- wait for Wishbone response:
|
| 460 |
|
|
-- When ack_i is asserted (= data ready), signal "Disconnect with data" to PCI master,
|
| 461 |
|
|
-- provide the data and one clock cycle later the parity.
|
| 462 |
|
|
-- When err_i is asserted (= access error), signal "Target-Abort". In this case, no
|
| 463 |
|
|
-- data is provided and the third stage is not activated.
|
| 464 |
|
|
-- When neither ack_i nor err_i were asserted for WB_MAX_LAT clock cycles, signal
|
| 465 |
|
|
-- "Target-Abort". The third stage is not activated then, too.
|
| 466 |
|
|
|
| 467 |
|
|
--STAGE 1: save address for Wishbone in the first clock cycle where irdy is asserted and initiate WB action
|
| 468 |
|
|
when Mem_read_1 =>
|
| 469 |
|
|
if irdy = '0' then
|
| 470 |
|
|
wb_adr_o <= "0000000000" & pci_address;
|
| 471 |
|
|
wb_cyc_o <= '1'; --set the Wishbone master signals for a read cycle
|
| 472 |
|
|
wb_stb_o <= '1';
|
| 473 |
|
|
wait_count <= x"0"; --reset timeout counter
|
| 474 |
|
|
main_state <= Mem_read_2;
|
| 475 |
|
|
end if;
|
| 476 |
|
|
|
| 477 |
|
|
--STAGE 2: wait for Wishbone response, react accordingly to the PCI bus and end the WB cycle
|
| 478 |
|
|
when Mem_read_2 =>
|
| 479 |
|
|
if wb_ack_i = '1' then --WB transaction completed
|
| 480 |
|
|
wb_adr_o <= (others => '0');
|
| 481 |
|
|
wb_cyc_o <= '0';
|
| 482 |
|
|
wb_stb_o <= '0';
|
| 483 |
|
|
ad <= wb_dat_i;
|
| 484 |
|
|
trdy <= '0'; --trdy and stop asserted at the same time -> Disconnect
|
| 485 |
|
|
stop <= '0';
|
| 486 |
|
|
par_create <= '1';
|
| 487 |
|
|
main_state <= Mem_read_3;
|
| 488 |
|
|
elsif wb_err_i = '1' or wait_count = WB_MAX_LAT then --WB transaction aborted, or no WB answer for WB_MAX_LAT clock cycles
|
| 489 |
|
|
wb_adr_o <= (others => '0');
|
| 490 |
|
|
wb_cyc_o <= '0';
|
| 491 |
|
|
wb_stb_o <= '0';
|
| 492 |
|
|
devsel <= '1'; --stop asserted and devsel deasserted at the same time -> Target-Abort
|
| 493 |
|
|
stop <= '0';
|
| 494 |
|
|
target_abort <= '1'; --status register entry
|
| 495 |
|
|
main_state <= Idle;
|
| 496 |
|
|
end if;
|
| 497 |
|
|
wait_count <= wait_count + 1; --count the wait cycles
|
| 498 |
|
|
|
| 499 |
|
|
--STAGE 3: one clock cycle later, end the PCI cycle (only after Disconnect)
|
| 500 |
|
|
when Mem_read_3 =>
|
| 501 |
|
|
ad <= (others => 'Z');
|
| 502 |
|
|
devsel <= '1';
|
| 503 |
|
|
trdy <= '1';
|
| 504 |
|
|
stop <= '1';
|
| 505 |
|
|
par_create <= '0';
|
| 506 |
|
|
main_state <= Idle;
|
| 507 |
|
|
|
| 508 |
|
|
|
| 509 |
|
|
-- ########## MEM WRITE STATE ##########
|
| 510 |
|
|
-- The data to be written and the address is provided for the Wishbone bus. Then,
|
| 511 |
|
|
-- wait for Wishbone response:
|
| 512 |
|
|
-- When ack_i is asserted (= data was stored), signal "Disconnect with data" to PCI
|
| 513 |
|
|
-- master and end the PCI cycle on the next clock edge.
|
| 514 |
|
|
-- When err_i is asserted (= access error, no transaction), signal "Target-Abort". In
|
| 515 |
|
|
-- this case, no data was changed and the third stage is not activated.
|
| 516 |
|
|
-- When neither ack_i nor err_i were asserted for WB_MAX_LAT clock cycles, signal
|
| 517 |
|
|
-- "Target-Abort". The third stage is not activated then, too.
|
| 518 |
|
|
|
| 519 |
|
|
--STAGE 1: save write data for WB in the first clock cycle where irdy is asserted and initiate WB action
|
| 520 |
|
|
when Mem_write_1 =>
|
| 521 |
|
|
if irdy = '0' then
|
| 522 |
|
|
wb_adr_o <= x"00" & "00" & pci_address;
|
| 523 |
|
|
wb_dat_o <= ad;
|
| 524 |
|
|
wb_cyc_o <= '1'; --set the Wishbone master signals for a write cycle
|
| 525 |
|
|
wb_stb_o <= '1';
|
| 526 |
|
|
wb_we_o <= '1';
|
| 527 |
|
|
wait_count <= x"0"; --reset timeout counter
|
| 528 |
|
|
main_state <= Mem_write_2;
|
| 529 |
|
|
end if;
|
| 530 |
|
|
|
| 531 |
|
|
--STAGE 2: wait for Wishbone response, react accordingly to the PCI bus and end the WB cycle
|
| 532 |
|
|
when Mem_write_2 =>
|
| 533 |
|
|
if wb_ack_i = '1' then --WB transaction completed
|
| 534 |
|
|
wb_adr_o <= (others => '0');
|
| 535 |
|
|
wb_dat_o <= (others => '0');
|
| 536 |
|
|
wb_cyc_o <= '0';
|
| 537 |
|
|
wb_stb_o <= '0';
|
| 538 |
|
|
wb_we_o <= '0';
|
| 539 |
|
|
trdy <= '0'; --trdy and stop asserted at the same time -> Disconnect
|
| 540 |
|
|
stop <= '0';
|
| 541 |
|
|
main_state <= Mem_write_3;
|
| 542 |
|
|
elsif wb_err_i = '1' or wait_count = WB_MAX_LAT then --WB transaction aborted, or no WB answer for WB_MAX_LAT clock cycles
|
| 543 |
|
|
wb_adr_o <= (others => '0');
|
| 544 |
|
|
wb_dat_o <= (others => '0');
|
| 545 |
|
|
wb_cyc_o <= '0';
|
| 546 |
|
|
wb_stb_o <= '0';
|
| 547 |
|
|
wb_we_o <= '0';
|
| 548 |
|
|
devsel <= '1'; --stop asserted and devsel deasserted at the same time -> Target-Abort
|
| 549 |
|
|
stop <= '0';
|
| 550 |
|
|
target_abort<= '1'; --status register entry
|
| 551 |
|
|
main_state <= Idle;
|
| 552 |
|
|
end if;
|
| 553 |
|
|
wait_count <= wait_count + 1; --count the wait cycles
|
| 554 |
|
|
|
| 555 |
|
|
--STAGE 3: one clock cycle later, end the PCI cycle (only after Disconnect)
|
| 556 |
|
|
when Mem_write_3 =>
|
| 557 |
|
|
devsel <= '1';
|
| 558 |
|
|
trdy <= '1';
|
| 559 |
|
|
stop <= '1';
|
| 560 |
|
|
main_state <= Idle;
|
| 561 |
|
|
|
| 562 |
|
|
|
| 563 |
|
|
-- ########## undefined state ##########
|
| 564 |
|
|
-- This state normally should never occur. Just for completion.
|
| 565 |
|
|
when others =>
|
| 566 |
|
|
main_state <= Idle;
|
| 567 |
|
|
|
| 568 |
|
|
end case;
|
| 569 |
|
|
end if;
|
| 570 |
|
|
end process;
|
| 571 |
|
|
|
| 572 |
|
|
|
| 573 |
|
|
--+------------------------------------------------------------------------------------+
|
| 574 |
|
|
--| Parity generation |
|
| 575 |
|
|
--+------------------------------------------------------------------------------------+
|
| 576 |
|
|
-- This process calcutates the even parity of the ad and cbe lines when par_create is
|
| 577 |
|
|
-- asserted. The main state machine asserts par_create exactly when trdy is asserted
|
| 578 |
|
|
-- in a Read cycle (both Config and Memory). Because this process sees the assertion
|
| 579 |
|
|
-- of par_create only on the following clock edge, parity for the master is always
|
| 580 |
|
|
-- provided one clock cycle delayed to ad (which is required by PCI).
|
| 581 |
|
|
process(reset, clk)
|
| 582 |
|
|
begin
|
| 583 |
|
|
if reset = '0' then
|
| 584 |
|
|
par <= 'Z';
|
| 585 |
|
|
elsif rising_edge(clk) then
|
| 586 |
|
|
if par_create = '1' then
|
| 587 |
|
|
par <= ( ad(31) xor ad(30) xor ad(29) xor ad(28) ) xor
|
| 588 |
|
|
( ad(27) xor ad(26) xor ad(25) xor ad(24) ) xor
|
| 589 |
|
|
( ad(23) xor ad(22) xor ad(21) xor ad(20) ) xor
|
| 590 |
|
|
( ad(19) xor ad(18) xor ad(17) xor ad(16) ) xor
|
| 591 |
|
|
( ad(15) xor ad(14) xor ad(13) xor ad(12) ) xor
|
| 592 |
|
|
( ad(11) xor ad(10) xor ad(9) xor ad(8) ) xor
|
| 593 |
|
|
( ad(7) xor ad(6) xor ad(5) xor ad(4) ) xor
|
| 594 |
|
|
( ad(3) xor ad(2) xor ad(1) xor ad(0) ) xor
|
| 595 |
|
|
( cbe(3) xor cbe(2) xor cbe(1) xor cbe(0) );
|
| 596 |
|
|
else
|
| 597 |
|
|
par <= 'Z';
|
| 598 |
|
|
end if;
|
| 599 |
|
|
end if;
|
| 600 |
|
|
end process;
|
| 601 |
|
|
|
| 602 |
|
|
|
| 603 |
|
|
end Behavioral;
|
