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-------------------------------------------------------------------------------
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--
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-- Title : pcie_core64_wishbone
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-- Author : Dmitry Smekhov
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-- Company : Instrumental Systems
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-- E-mail : dsmv@insys.ru
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--
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-- Version : 1.4
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--
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-------------------------------------------------------------------------------
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--
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-- Description : Контроллер PCI Express
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-- Модификация Wishbone - Spartan-6 PCI Express v1.1 x1
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-- Шина Wishbone 64 разряда
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-- Блок PE_MAIN
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--
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-------------------------------------------------------------------------------
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--
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-- Version 1.1 (15.10.2011) : Kuzmi4
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-- Construct Module Architecture for WB bus : CORE64_M6 + PE_MAIN + PB_WB_BRIDGE
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--
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-- Version 1.2 (16.10.2011) : Kuzmi4
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-- Del PE_MAIN - useless module
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--
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-- Version 1.3 (19.10.2011) : dsmv
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-- return PE_MAIN to design (software driver req this module for correct WRK: req constants)
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package pcie_core64_wishbone_pkg is
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component pcie_core64_wishbone is
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generic
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(
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Device_ID : in std_logic_vector( 15 downto 0 ):=x"0000"; -- идентификатор модуля
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Revision : in std_logic_vector( 15 downto 0 ):=x"0000"; -- версия модуля
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PLD_VER : in std_logic_vector( 15 downto 0 ):=x"0000"; -- версия ПЛИС
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is_simulation : integer:=0 --! 0 - синтез, 1 - моделирование
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);
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port
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(
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---- PCI-Express ----
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txp : out std_logic_vector( 0 downto 0 );
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txn : out std_logic_vector( 0 downto 0 );
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rxp : in std_logic_vector( 0 downto 0 );
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rxn : in std_logic_vector( 0 downto 0 );
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mgt125 : in std_logic; -- тактовая частота 125 MHz от PCI_Express
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perst : in std_logic; -- 0 - сброс
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px : out std_logic_vector( 7 downto 0 ); --! контрольные точки
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pcie_lstatus : out std_logic_vector( 15 downto 0 ); -- регистр LSTATUS
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pcie_link_up : out std_logic; -- 0 - завершена инициализация PCI-Express
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---- Wishbone SYS_CON -----
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o_wb_clk : out std_logic;
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o_wb_rst : out std_logic;
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---- Wishbone BUS -----
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ov_wbm_addr : out std_logic_vector(31 downto 0);
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ov_wbm_data : out std_logic_vector(63 downto 0);
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ov_wbm_sel : out std_logic_vector( 7 downto 0);
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o_wbm_we : out std_logic;
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o_wbm_cyc : out std_logic;
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o_wbm_stb : out std_logic;
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ov_wbm_cti : out std_logic_vector( 2 downto 0); -- Cycle Type Identifier Address Tag
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ov_wbm_bte : out std_logic_vector( 1 downto 0); -- Burst Type Extension Address Tag
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iv_wbm_data : in std_logic_vector(63 downto 0);
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i_wbm_ack : in std_logic;
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i_wbm_err : in std_logic; -- error input - abnormal cycle termination
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i_wbm_rty : in std_logic; -- retry input - interface is not ready
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i_wdm_irq_0 : in std_logic;
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iv_wbm_irq_dmar : in std_logic_vector( 1 downto 0)
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);
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end component pcie_core64_wishbone;
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end package pcie_core64_wishbone_pkg;
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.core64_type_pkg.all;
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use work.pcie_core64_m6_pkg.all;
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use work.core64_pb_wishbone_pkg.all;
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dsmv |
use work.block_pe_main_pkg.all;
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2 |
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library unisim;
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use unisim.vcomponents.all;
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entity pcie_core64_wishbone is
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generic
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(
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Device_ID : in std_logic_vector( 15 downto 0 ):=x"0000"; -- идентификатор модуля
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Revision : in std_logic_vector( 15 downto 0 ):=x"0000"; -- версия модуля
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PLD_VER : in std_logic_vector( 15 downto 0 ):=x"0000"; -- версия ПЛИС
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is_simulation : integer:=0 --! 0 - синтез, 1 - моделирование
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);
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port
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(
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---- PCI-Express ----
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txp : out std_logic_vector( 0 downto 0 );
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txn : out std_logic_vector( 0 downto 0 );
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rxp : in std_logic_vector( 0 downto 0 );
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rxn : in std_logic_vector( 0 downto 0 );
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mgt125 : in std_logic; -- тактовая частота 125 MHz от PCI_Express
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perst : in std_logic; -- 0 - сброс
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px : out std_logic_vector( 7 downto 0 ); --! контрольные точки
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pcie_lstatus : out std_logic_vector( 15 downto 0 ); -- регистр LSTATUS
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pcie_link_up : out std_logic; -- 0 - завершена инициализация PCI-Express
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---- Wishbone SYS_CON -----
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o_wb_clk : out std_logic;
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o_wb_rst : out std_logic;
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---- Wishbone BUS -----
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ov_wbm_addr : out std_logic_vector(31 downto 0);
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ov_wbm_data : out std_logic_vector(63 downto 0);
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ov_wbm_sel : out std_logic_vector( 7 downto 0);
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o_wbm_we : out std_logic;
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o_wbm_cyc : out std_logic;
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o_wbm_stb : out std_logic;
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ov_wbm_cti : out std_logic_vector( 2 downto 0); -- Cycle Type Identifier Address Tag
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ov_wbm_bte : out std_logic_vector( 1 downto 0); -- Burst Type Extension Address Tag
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iv_wbm_data : in std_logic_vector(63 downto 0);
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i_wbm_ack : in std_logic;
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i_wbm_err : in std_logic; -- error input - abnormal cycle termination
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i_wbm_rty : in std_logic; -- retry input - interface is not ready
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i_wdm_irq_0 : in std_logic;
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iv_wbm_irq_dmar : in std_logic_vector( 1 downto 0)
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);
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end pcie_core64_wishbone;
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architecture pcie_core64_wishbone of pcie_core64_wishbone is
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-------------------------------------------------------------------------------
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--
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-- BAR0 - блоки управления ----
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signal bp_host_data : std_logic_vector( 31 downto 0 ); --! шина данных - выход
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signal bp_data : std_logic_vector( 31 downto 0 ); --! шина данных - вход
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signal bp_adr : std_logic_vector( 19 downto 0 ); --! адрес регистра внутри блока
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signal bp_we : std_logic_vector( 3 downto 0 ); --! 1 - запись в регистры
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signal bp_rd : std_logic_vector( 3 downto 0 ); --! 1 - чтение из регистров блока
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signal bp_sel : std_logic_vector( 1 downto 0 ); --! номер блока для чтения
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signal bp_reg_we : std_logic; --! 1 - запись в регистр по адресам 0x100000 - 0x1FFFFF
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signal bp_reg_rd : std_logic; --! 1 - чтение из регистра по адресам 0x100000 - 0x1FFFFF
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signal bp_irq : std_logic; --! 1 - запрос прерывания
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signal pb_master : type_pb_master; --! запрос
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signal pb_slave : type_pb_slave; --! ответ
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signal pb_reset : std_logic;
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signal brd_mode : std_logic_vector( 15 downto 0 );
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signal bp0_data : std_logic_vector( 31 downto 0 );
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-------------------------------------------------------------------------------
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--
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-- Declare Global SYS_CON stuff:
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dsmv |
signal clk : std_logic;
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signal reset : std_logic;
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signal dcm_rst : std_logic;
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signal reset_p : std_logic;
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signal reset_p_z1 : std_logic;
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dsmv |
signal reset_p_z2 : std_logic;
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signal clk62x : std_logic:='0';
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signal clk62 : std_logic;
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2 |
dsmv |
-------------------------------------------------------------------------------
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begin
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-------------------------------------------------------------------------------
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--
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-- Instantiate CORE64_M6 module with PB BUS:
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--
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CORE : pcie_core64_m6
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generic map
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(
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is_simulation => is_simulation --! 0 - синтез, 1 - моделирование
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)
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port map
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(
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---- PCI-Express ----
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txp => txp,
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txn => txn,
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rxp => rxp,
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rxn => rxn,
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mgt125 => mgt125,
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perst => perst,
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px => px,
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pcie_lstatus => pcie_lstatus,
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pcie_link_up => pcie_link_up,
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---- Локальная шина ----
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38 |
dsmv |
clk_out => clk, -- S6 PCIE x1 module clock output
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reset_out => reset, --
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dcm_rstp => dcm_rst, -- S6 PCIE x1 module INV trn_reset_n_c
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2 |
dsmv |
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---- BAR1 (PB bus) ----
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40 |
dsmv |
aclk => clk62, -- clock for local bus
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2 |
dsmv |
aclk_lock => '1', --
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pb_master => pb_master, --
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pb_slave => pb_slave, --
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---- BAR0 (to PE_MAIN) - блоки управления ----
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bp_host_data => bp_host_data,
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bp_data => bp_data,
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bp_adr => bp_adr,
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bp_we => bp_we,
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bp_rd => bp_rd,
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bp_sel => bp_sel,
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bp_reg_we => bp_reg_we,
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bp_reg_rd => bp_reg_rd,
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bp_irq => bp_irq
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);
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-- Deal with CORE BP Input data:
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bp_data <= bp0_data when bp_sel="00" else (others=>'0');
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-------------------------------------------------------------------------------
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--
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-- Instantiate PE_MAIN module:
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--
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PE_MAIN : block_pe_main
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generic map
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(
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Device_ID => Device_ID, -- идентификатор модуля
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Revision => Revision, -- версия модуля
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PLD_VER => PLD_VER, -- версия ПЛИС
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BLOCK_CNT => x"0008" -- число блоков управления
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)
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port map
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(
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---- Global ----
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38 |
dsmv |
reset_hr1 => reset, -- 0 - сброс
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clk => clk, -- Тактовая частота PCIE x1 S6
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2 |
dsmv |
pb_reset => pb_reset, -- 0 - сброс ведомой ПЛИС
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---- HOST ----
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bl_adr => bp_adr( 4 downto 0 ), -- адрес
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bl_data_in => bp_host_data, -- данные
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bl_data_out => bp0_data, -- данные
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bl_data_we => bp_we(0), -- 1 - запись данных
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---- Управление ----
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brd_mode => brd_mode -- регистр BRD_MODE
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265 |
38 |
dsmv |
);
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40 |
dsmv |
clk62x <= not clk62x after 1 ns when rising_edge( clk );
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xclk62: bufg port map( clk62, clk62x );
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38 |
dsmv |
reset_p <= (not reset) or (not brd_mode(3));
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40 |
dsmv |
reset_p_z1 <= reset_p after 1 ns when rising_edge( clk62 );
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reset_p_z2 <= reset_p_z1 after 1 ns when rising_edge( clk62 );
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38 |
dsmv |
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275 |
2 |
dsmv |
-------------------------------------------------------------------------------
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--
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-- Instantiate PB BUS <-> WB BUS translator module:
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--
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PW_WB : core64_pb_wishbone
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port map
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(
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282 |
38 |
dsmv |
reset => reset_p_z2, --! 1 - сброс
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283 |
40 |
dsmv |
clk => clk62, --! тактовая частота локальной шины
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284 |
2 |
dsmv |
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285 |
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---- BAR1 ----
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pb_master => pb_master, --! запрос
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pb_slave => pb_slave, --! ответ
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---- Wishbone BUS -----
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ov_wbm_addr => ov_wbm_addr,
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ov_wbm_data => ov_wbm_data,
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ov_wbm_sel => ov_wbm_sel,
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o_wbm_we => o_wbm_we,
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o_wbm_cyc => o_wbm_cyc,
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o_wbm_stb => o_wbm_stb,
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ov_wbm_cti => ov_wbm_cti, -- Cycle Type Identifier Address Tag
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ov_wbm_bte => ov_wbm_bte, -- Burst Type Extension Address Tag
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iv_wbm_data => iv_wbm_data,
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i_wbm_ack => i_wbm_ack,
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i_wbm_err => i_wbm_err, -- error input - abnormal cycle termination
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i_wbm_rty => i_wbm_rty, -- retry input - interface is not ready
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i_wdm_irq_0 => i_wdm_irq_0,
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iv_wbm_irq_dmar => iv_wbm_irq_dmar
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);
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-------------------------------------------------------------------------------
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308 |
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--
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309 |
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-- Module Output route:
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310 |
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--
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311 |
40 |
dsmv |
o_wb_clk <= clk62; -- route from PW_WB wrk clock
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312 |
2 |
dsmv |
--
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313 |
38 |
dsmv |
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314 |
40 |
dsmv |
pr_o_wb_rst: process( reset_p, clk62 ) begin
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315 |
38 |
dsmv |
if( reset_p='1' ) then
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316 |
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o_wb_rst <= '1' after 1 ns;
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317 |
40 |
dsmv |
elsif( rising_edge( clk62 ) ) then
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318 |
38 |
dsmv |
o_wb_rst <= reset_p_z2 after 1 ns;
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319 |
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end if;
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320 |
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end process;
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321 |
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322 |
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323 |
2 |
dsmv |
-------------------------------------------------------------------------------
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324 |
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end pcie_core64_wishbone;
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