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[/] [pcie_ds_dma/] [trunk/] [core/] [ds_dma64/] [pcie_src/] [pcie_core64_m1/] [source_artix7/] [cl_a7pcie_x4_gt_top.vhd] - Blame information for rev 48

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1 46 dsmv 
-------------------------------------------------------------------------------
2 
--
3 
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
4 
--
5 
-- This file contains confidential and proprietary information
6 
-- of Xilinx, Inc. and is protected under U.S. and
7 
-- international copyright and other intellectual property
8 
-- laws.
9 
--
10 
-- DISCLAIMER
11 
-- This disclaimer is not a license and does not grant any
12 
-- rights to the materials distributed herewith. Except as
13 
-- otherwise provided in a valid license issued to you by
14 
-- Xilinx, and to the maximum extent permitted by applicable
15 
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
16 
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
17 
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
18 
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
19 
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
20 
-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
31 
--
32 
-- CRITICAL APPLICATIONS
33 
-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
35 
-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
40 
-- (individually and collectively, "Critical
41 
-- Applications"). Customer assumes the sole risk and
42 
-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
46 
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
47 
-- PART OF THIS FILE AT ALL TIMES.
48 
--
49 
-------------------------------------------------------------------------------
50 
-- Project    : Series-7 Integrated Block for PCI Express
51 
-- File       : cl_a7pcie_x4_gt_top.vhd
52 48 dsmv 
-- Version    : 1.10
53 46 dsmv 
---- Description: GTX module for 7-series Integrated PCIe Block
54 
----
55 
----
56 
----
57 
----------------------------------------------------------------------------------
58 
library ieee;
59 
use ieee.std_logic_1164.all;
60 
use ieee.std_logic_misc.all;
61 
use ieee.std_logic_unsigned.all;
62 
 
63 
entity cl_a7pcie_x4_gt_top is
64 
generic (
65 
   LINK_CAP_MAX_LINK_WIDTH_int    : integer := 1;       -- 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
66 
   REF_CLK_FREQ                   : integer := 0;       -- 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
67 
   USER_CLK2_DIV2                 : string := "FALSE";  -- "TRUE" => user_clk2 = user_clk/2, where user_clk = 500 or 250 MHz.
68 
                                                        -- "FALSE" => user_clk2 = user_clk
69 
   USER_CLK_FREQ                  : integer := 3;       -- 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz
70 
   PL_FAST_TRAIN                  : string := "FALSE";  -- Simulation Speedup
71 
   PCIE_EXT_CLK                   : string := "FALSE";  -- External Clock Enable
72 
   PCIE_USE_MODE                  : string := "1.0"  ;  -- 1.0=K325T IES, 1.1=VX48T IES, 3.0 = K325T GES
73 
   PCIE_GT_DEVICE                 : string := "GTX"  ;  -- Select the GT to use (GTP for Artix-7, GTX for K7/V7)
74 
   PCIE_PLL_SEL                   : string := "CPLL" ;  -- Select the PLL (CPLL or QPLL)
75 
   PCIE_ASYNC_EN                  : string := "FALSE";  -- Asynchronous Clocking Enable
76 
   PCIE_TXBUF_EN                  : string := "FALSE";  -- Use the Transmit Buffer
77 
   PCIE_CHAN_BOND                 : integer := 0
78 
);
79 
port (
80 
   -- pl ltssm
81 
   pl_ltssm_state         : in std_logic_vector(5 downto 0);
82 
 
83 
   -- Pipe Per-Link Signals
84 
   pipe_tx_rcvr_det       : in std_logic;
85 
   pipe_tx_reset          : in std_logic;
86 
   pipe_tx_rate           : in std_logic;
87 
   pipe_tx_deemph         : in std_logic;
88 
   pipe_tx_margin         : in std_logic_vector (2 downto 0);
89 
   pipe_tx_swing          : in std_logic;
90 
 
91 
   PIPE_PCLK_IN           : in std_logic;
92 
   PIPE_RXUSRCLK_IN       : in std_logic;
93 
   PIPE_RXOUTCLK_IN       : in std_logic_vector(3 downto 0);
94 
   PIPE_DCLK_IN           : in std_logic;
95 
   PIPE_USERCLK1_IN       : in std_logic;
96 
   PIPE_USERCLK2_IN       : in std_logic;
97 
   PIPE_OOBCLK_IN         : in std_logic;
98 
   PIPE_MMCM_LOCK_IN      : in std_logic;
99 
 
100 
   PIPE_TXOUTCLK_OUT      : out std_logic;
101 
   PIPE_RXOUTCLK_OUT      : out std_logic_vector(3 downto 0);
102 
   PIPE_PCLK_SEL_OUT      : out std_logic_vector(3 downto 0);
103 
   PIPE_GEN3_OUT          : out std_logic;
104 
 
105 
   -- Pipe Per-Lane Signals - Lane 0
106 
   pipe_rx0_char_is_k     : out std_logic_vector(1 downto 0);
107 
   pipe_rx0_data          : out std_logic_vector(15 downto 0);
108 
   pipe_rx0_valid         : out std_logic;
109 
   pipe_rx0_chanisaligned : out std_logic;
110 
   pipe_rx0_status        : out std_logic_vector(2 downto 0);
111 
   pipe_rx0_phy_status    : out std_logic;
112 
   pipe_rx0_elec_idle     : out std_logic;
113 
   pipe_rx0_polarity      : in std_logic;
114 
   pipe_tx0_compliance    : in std_logic;
115 
   pipe_tx0_char_is_k     : in std_logic_vector(1 downto 0);
116 
   pipe_tx0_data          : in std_logic_vector(15 downto 0);
117 
   pipe_tx0_elec_idle     : in std_logic;
118 
   pipe_tx0_powerdown     : in std_logic_vector(1 downto 0);
119 
 
120 
   -- Pipe Per-Lane Signals - Lane 1
121 
   pipe_rx1_char_is_k     : out std_logic_vector(1 downto 0);
122 
   pipe_rx1_data          : out std_logic_vector(15 downto 0);
123 
   pipe_rx1_valid         : out std_logic;
124 
   pipe_rx1_chanisaligned : out std_logic;
125 
   pipe_rx1_status        : out std_logic_vector(2 downto 0);
126 
   pipe_rx1_phy_status    : out std_logic;
127 
   pipe_rx1_elec_idle     : out std_logic;
128 
   pipe_rx1_polarity      : in std_logic;
129 
   pipe_tx1_compliance    : in std_logic;
130 
   pipe_tx1_char_is_k     : in std_logic_vector(1 downto 0);
131 
   pipe_tx1_data          : in std_logic_vector(15 downto 0);
132 
   pipe_tx1_elec_idle     : in std_logic;
133 
   pipe_tx1_powerdown     : in std_logic_vector(1 downto 0);
134 
 
135 
   -- Pipe Per-Lane Signals - Lane 2
136 
   pipe_rx2_char_is_k     : out std_logic_vector(1 downto 0);
137 
   pipe_rx2_data          : out std_logic_vector(15 downto 0);
138 
   pipe_rx2_valid         : out std_logic;
139 
   pipe_rx2_chanisaligned : out std_logic;
140 
   pipe_rx2_status        : out std_logic_vector(2 downto 0);
141 
   pipe_rx2_phy_status    : out std_logic;
142 
   pipe_rx2_elec_idle     : out std_logic;
143 
   pipe_rx2_polarity      : in std_logic;
144 
   pipe_tx2_compliance    : in std_logic;
145 
   pipe_tx2_char_is_k     : in std_logic_vector(1 downto 0);
146 
   pipe_tx2_data          : in std_logic_vector(15 downto 0);
147 
   pipe_tx2_elec_idle     : in std_logic;
148 
   pipe_tx2_powerdown     : in std_logic_vector(1 downto 0);
149 
 
150 
   -- Pipe Per-Lane Signals - Lane 3
151 
   pipe_rx3_char_is_k     : out std_logic_vector(1 downto 0);
152 
   pipe_rx3_data          : out std_logic_vector(15 downto 0);
153 
   pipe_rx3_valid         : out std_logic;
154 
   pipe_rx3_chanisaligned : out std_logic;
155 
   pipe_rx3_status        : out std_logic_vector(2 downto 0);
156 
   pipe_rx3_phy_status    : out std_logic;
157 
   pipe_rx3_elec_idle     : out std_logic;
158 
   pipe_rx3_polarity      : in std_logic;
159 
   pipe_tx3_compliance    : in std_logic;
160 
   pipe_tx3_char_is_k     : in std_logic_vector(1 downto 0);
161 
   pipe_tx3_data          : in std_logic_vector(15 downto 0);
162 
   pipe_tx3_elec_idle     : in std_logic;
163 
   pipe_tx3_powerdown     : in std_logic_vector(1 downto 0);
164 
 
165 
   -- Pipe Per-Lane Signals - Lane 4
166 
   pipe_rx4_char_is_k     : out std_logic_vector(1 downto 0);
167 
   pipe_rx4_data          : out std_logic_vector(15 downto 0);
168 
   pipe_rx4_valid         : out std_logic;
169 
   pipe_rx4_chanisaligned : out std_logic;
170 
   pipe_rx4_status        : out std_logic_vector(2 downto 0);
171 
   pipe_rx4_phy_status    : out std_logic;
172 
   pipe_rx4_elec_idle     : out std_logic;
173 
   pipe_rx4_polarity      : in std_logic;
174 
   pipe_tx4_compliance    : in std_logic;
175 
   pipe_tx4_char_is_k     : in std_logic_vector(1 downto 0);
176 
   pipe_tx4_data          : in std_logic_vector(15 downto 0);
177 
   pipe_tx4_elec_idle     : in std_logic;
178 
   pipe_tx4_powerdown     : in std_logic_vector(1 downto 0);
179 
 
180 
   -- Pipe Per-Lane Signals - Lane 5
181 
   pipe_rx5_char_is_k     : out std_logic_vector(1 downto 0);
182 
   pipe_rx5_data          : out std_logic_vector(15 downto 0);
183 
   pipe_rx5_valid         : out std_logic;
184 
   pipe_rx5_chanisaligned : out std_logic;
185 
   pipe_rx5_status        : out std_logic_vector(2 downto 0);
186 
   pipe_rx5_phy_status    : out std_logic;
187 
   pipe_rx5_elec_idle     : out std_logic;
188 
   pipe_rx5_polarity      : in std_logic;
189 
   pipe_tx5_compliance    : in std_logic;
190 
   pipe_tx5_char_is_k     : in std_logic_vector(1 downto 0);
191 
   pipe_tx5_data          : in std_logic_vector(15 downto 0);
192 
   pipe_tx5_elec_idle     : in std_logic;
193 
   pipe_tx5_powerdown     : in std_logic_vector(1 downto 0);
194 
 
195 
   -- Pipe Per-Lane Signals - Lane 6
196 
   pipe_rx6_char_is_k     : out std_logic_vector(1 downto 0);
197 
   pipe_rx6_data          : out std_logic_vector(15 downto 0);
198 
   pipe_rx6_valid         : out std_logic;
199 
   pipe_rx6_chanisaligned : out std_logic;
200 
   pipe_rx6_status        : out std_logic_vector(2 downto 0);
201 
   pipe_rx6_phy_status    : out std_logic;
202 
   pipe_rx6_elec_idle     : out std_logic;
203 
   pipe_rx6_polarity      : in std_logic;
204 
   pipe_tx6_compliance    : in std_logic;
205 
   pipe_tx6_char_is_k     : in std_logic_vector(1 downto 0);
206 
   pipe_tx6_data          : in std_logic_vector(15 downto 0);
207 
   pipe_tx6_elec_idle     : in std_logic;
208 
   pipe_tx6_powerdown     : in std_logic_vector(1 downto 0);
209 
 
210 
   -- Pipe Per-Lane Signals - Lane 7
211 
   pipe_rx7_char_is_k     : out std_logic_vector(1 downto 0);
212 
   pipe_rx7_data          : out std_logic_vector(15 downto 0);
213 
   pipe_rx7_valid         : out std_logic;
214 
   pipe_rx7_chanisaligned : out std_logic;
215 
   pipe_rx7_status        : out std_logic_vector(2 downto 0);
216 
   pipe_rx7_phy_status    : out std_logic;
217 
   pipe_rx7_elec_idle     : out std_logic;
218 
   pipe_rx7_polarity      : in std_logic;
219 
   pipe_tx7_compliance    : in std_logic;
220 
   pipe_tx7_char_is_k     : in std_logic_vector(1 downto 0);
221 
   pipe_tx7_data          : in std_logic_vector(15 downto 0);
222 
   pipe_tx7_elec_idle     : in std_logic;
223 
   pipe_tx7_powerdown     : in std_logic_vector(1 downto 0);
224 
 
225 
   -- PCI Express signals
226 
   pci_exp_txn            : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
227 
   pci_exp_txp            : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
228 
   pci_exp_rxn            : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
229 
   pci_exp_rxp            : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
230 
 
231 
   -- Non PIPE signals
232 
   sys_clk                : in std_logic;
233 
   sys_rst_n              : in std_logic;
234 
   PIPE_MMCM_RST_N        : in std_logic;   --     // Async      | Async
235 
 
236 
   pipe_clk               : out std_logic;
237 
   user_clk               : out std_logic;
238 
   user_clk2              : out std_logic;
239 
 
240 
   phy_rdy_n              : out std_logic
241 
);
242 
end cl_a7pcie_x4_gt_top;
243 
 
244 
architecture pcie_7x of cl_a7pcie_x4_gt_top is
245 
 
246 
 
247 
   component cl_a7pcie_x4_gt_rx_valid_filter_7x is
248 
      generic (
249 
        CLK_COR_MIN_LAT      : integer := 28;
250 
        TCQ                  : integer := 1
251 
      );
252 
      port (
253 
        USER_RXCHARISK       : out std_logic_vector( 1 downto 0);
254 
        USER_RXDATA          : out std_logic_vector(15 downto 0);
255 
        USER_RXVALID         : out std_logic;
256 
        USER_RXELECIDLE      : out std_logic;
257 
        USER_RX_STATUS       : out std_logic_vector( 2 downto 0);
258 
        USER_RX_PHY_STATUS   : out std_logic;
259 
        GT_RXCHARISK         : in  std_logic_vector( 1 downto 0);
260 
        GT_RXDATA            : in  std_logic_vector(15 downto 0);
261 
        GT_RXVALID           : in  std_logic;
262 
        GT_RXELECIDLE        : in  std_logic;
263 
        GT_RX_STATUS         : in  std_logic_vector( 2 downto 0);
264 
        GT_RX_PHY_STATUS     : in  std_logic;
265 
 
266 
        PLM_IN_L0            : in  std_logic;
267 
        PLM_IN_RS            : in  std_logic;
268 
 
269 
        USER_CLK             : in  std_logic;
270 
        RESET                : in  std_logic
271 
      );
272 
   end component;
273 
 
274 
 
275 
   component cl_a7pcie_x4_pipe_wrapper is
276 
      generic (
277 
        PCIE_SIM_MODE                 : string  := "false";
278 
 
279 
        -- pragma synthesis_off
280 
        PCIE_SIM_SPEEDUP              : string  := "TRUE"; -- Simulation Speedup
281 
        -- pragma synthesis_on
282 
 
283 
        PCIE_TXBUF_EN                 : string  := "false";
284 
        PCIE_CHAN_BOND                : integer := 0;
285 
        PCIE_PLL_SEL                  : string  := "CPLL";
286 
        PCIE_GT_DEVICE                : string  := "GTX";
287 
        PCIE_USE_MODE                 : string  := "1.0";
288 
        PCIE_LPM_DFE                  : string  := "LPM";
289 
        PCIE_LANE                     : integer := 1;
290 
        PCIE_LINK_SPEED               : integer := 3;
291 
        PCIE_REFCLK_FREQ              : integer := 0;
292 
        PCIE_TX_EIDLE_ASSERT_DELAY    : integer := 4;
293 
        PCIE_OOBCLK_MODE              : integer := 0;
294 
        PCIE_USERCLK1_FREQ            : integer := 2;
295 
        PCIE_USERCLK2_FREQ            : integer := 2;
296 
        PCIE_EXT_CLK                  : string  := "FALSE"
297 
 
298 
      );
299 
      port (
300 
 
301 
    PIPE_CLK                      : in std_logic;
302 
    PIPE_RESET_N                  : in std_logic;
303 
    PIPE_PCLK                     : out std_logic;
304 
 
305 
    PIPE_TXDATA                   : in std_logic_vector((32*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
306 
    PIPE_TXDATAK                  : in std_logic_vector((4*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
307 
 
308 
    PIPE_TXP                      : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
309 
    PIPE_TXN                      : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
310 
 
311 
    PIPE_RXP                      : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
312 
    PIPE_RXN                      : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
313 
 
314 
    PIPE_RXDATA                   : out std_logic_vector((32*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
315 
    PIPE_RXDATAK                  : out std_logic_vector((4*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
316 
 
317 
    PIPE_TXDETECTRX               : in std_logic;
318 
    PIPE_TXELECIDLE               : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
319 
    PIPE_TXCOMPLIANCE             : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
320 
    PIPE_RXPOLARITY               : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
321 
    PIPE_POWERDOWN                : in std_logic_vector((2*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
322 
    PIPE_RATE                     : in std_logic_vector(1 downto 0);
323 
 
324 
    PIPE_TXMARGIN                 : in std_logic_vector(2 downto 0);
325 
    PIPE_TXSWING                  : in std_logic;
326 
    PIPE_TXEQ_CONTROL             : in std_logic_vector((2*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
327 
    PIPE_TXEQ_PRESET              : in std_logic_vector((4*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
328 
    PIPE_TXEQ_PRESET_DEFAULT      : in std_logic_vector((4*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
329 
 
330 
    PIPE_RXEQ_CONTROL             : in std_logic_vector((2*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
331 
    PIPE_RXEQ_PRESET              : in std_logic_vector((3*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
332 
    PIPE_RXEQ_LFFS                : in std_logic_vector((6*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
333 
    PIPE_RXEQ_TXPRESET            : in std_logic_vector((4*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
334 
    PIPE_TXEQ_COEFF               : out std_logic_vector(((18*LINK_CAP_MAX_LINK_WIDTH_int)-1) downto 0);
335 
    PIPE_RXEQ_USER_EN             : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
336 
    PIPE_RXEQ_USER_TXCOEFF        : in std_logic_vector((18*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
337 
    PIPE_RXEQ_USER_MODE           : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
338 
    PIPE_TXDEEMPH                 : in std_logic_vector((1*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
339 
    PIPE_TXEQ_DEEMPH              : in std_logic_vector((6*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
340 
 
341 
    PIPE_TXEQ_FS                  : out std_logic_vector(5 downto 0);
342 
    PIPE_TXEQ_LF                  : out std_logic_vector(5 downto 0);
343 
    PIPE_TXEQ_DONE                : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
344 
 
345 
    PIPE_RXEQ_NEW_TXCOEFF         : out std_logic_vector((18*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
346 
    PIPE_RXEQ_LFFS_SEL            : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
347 
    PIPE_RXEQ_ADAPT_DONE          : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
348 
    PIPE_RXEQ_DONE                : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
349 
 
350 
    PIPE_RXVALID                  : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
351 
    PIPE_PHYSTATUS                : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
352 
    PIPE_PHYSTATUS_RST            : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
353 
    PIPE_RXELECIDLE               : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
354 
    PIPE_RXSTATUS                 : out std_logic_vector((3*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
355 
    PIPE_RXBUFSTATUS              : out std_logic_vector((3*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
356 
 
357 
    PIPE_MMCM_RST_N               : in std_logic;   --     // Async      | Async
358 
 
359 
    PIPE_RXSLIDE                  : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
360 
    PIPE_CPLL_LOCK                : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
361 
    PIPE_QPLL_LOCK                : out std_logic_vector(((LINK_CAP_MAX_LINK_WIDTH_int)/8) downto 0);
362 
    PIPE_PCLK_LOCK                : out std_logic;
363 
    PIPE_RXCDRLOCK                : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
364 
    PIPE_USERCLK1                 : out std_logic;
365 
    PIPE_USERCLK2                 : out std_logic;
366 
    PIPE_RXUSRCLK                 : out std_logic;
367 
 
368 
    PIPE_RXOUTCLK                 : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
369 
    PIPE_TXSYNC_DONE              : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
370 
    PIPE_RXSYNC_DONE              : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
371 
    PIPE_GEN3_RDY                 : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
372 
    PIPE_RXCHANISALIGNED          : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
373 
    PIPE_ACTIVE_LANE              : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
374 
 
375 
    PIPE_PCLK_IN                  : in  std_logic;
376 
    PIPE_RXUSRCLK_IN              : in  std_logic;
377 
 
378 
    PIPE_RXOUTCLK_IN              : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
379 
    PIPE_DCLK_IN                  : in  std_logic;
380 
    PIPE_USERCLK1_IN              : in  std_logic;
381 
    PIPE_USERCLK2_IN              : in  std_logic;
382 
    PIPE_OOBCLK_IN                : in std_logic;
383 
    PIPE_JTAG_EN                  : in std_logic;
384 
    PIPE_JTAG_RDY                 : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
385 
    PIPE_MMCM_LOCK_IN             : in  std_logic;
386 
 
387 
    PIPE_TXOUTCLK_OUT             : out std_logic;
388 
    PIPE_RXOUTCLK_OUT             : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
389 
    PIPE_PCLK_SEL_OUT             : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
390 
    PIPE_GEN3_OUT                 : out std_logic;
391 
 
392 
    PIPE_TXPRBSSEL                : in std_logic_vector(2 downto 0);
393 
    PIPE_RXPRBSSEL                : in std_logic_vector(2 downto 0);
394 
    PIPE_TXPRBSFORCEERR           : in std_logic;
395 
    PIPE_RXPRBSCNTRESET           : in std_logic;
396 
    PIPE_LOOPBACK                 : in std_logic_vector(2 downto 0);
397 
 
398 
    PIPE_RXPRBSERR                : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
399 
 
400 
    PIPE_RST_FSM                  : out std_logic_vector(10 downto 0);
401 
    PIPE_QRST_FSM                 : out std_logic_vector(11 downto 0);
402 
    PIPE_SYNC_FSM_TX              : out std_logic_vector((6*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
403 
    PIPE_SYNC_FSM_RX              : out std_logic_vector((7*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
404 
    PIPE_DRP_FSM                  : out std_logic_vector((7*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
405 
    PIPE_TXEQ_FSM                 : out std_logic_vector((6*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
406 
    PIPE_QDRP_FSM                 : out std_logic_vector(((((LINK_CAP_MAX_LINK_WIDTH_int)/8)+1)*9)-1 downto 0);
407 
    PIPE_RATE_FSM                 : out std_logic_vector((31*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
408 
 
409 
    PIPE_RXEQ_FSM                 : out std_logic_vector((6*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
410 
 
411 
    PIPE_RST_IDLE                 : out std_logic;
412 
    PIPE_QRST_IDLE                : out std_logic;
413 
    PIPE_RATE_IDLE                : out std_logic;
414 
 
415 
    PIPE_DEBUG_0                  : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
416 
    PIPE_DEBUG_1                  : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
417 
    PIPE_DEBUG_2                  : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
418 
    PIPE_DEBUG_3                  : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
419 
    PIPE_DEBUG_4                  : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
420 
    PIPE_DEBUG_5                  : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
421 
    PIPE_DEBUG_6                  : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
422 
    PIPE_DEBUG_7                  : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
423 
    PIPE_DEBUG_8                  : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
424 
    PIPE_DEBUG_9                  : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
425 
    PIPE_DEBUG                    : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
426 
 
427 
    PIPE_DMONITOROUT              : out std_logic_vector((15*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0)
428 
 
429 
    );
430 
   end component;
431 
  -- Calculate USERCLK2 Frequency
432 
  function get_usrclk2_freq (
433 
    constant div2   : string;
434 
    constant freq   : integer)
435 
    return integer is
436 
  begin  -- msb_addr
437 
 
438 
    if (div2 = "TRUE") then
439 
      if (freq = 4) then
440 
        return 3;
441 
      elsif (freq = 3) then
442 
        return 2;
443 
      else
444 
        return freq;
445 
      end if;
446 
    else
447 
      return freq;
448 
    end if;
449 
  end get_usrclk2_freq;
450 
 
451 
   -- purpose: Determine LPM_DFE setting for GT
452 
   function get_lpm (
453 
     constant simulation : string)
454 
     return string is
455 
   begin  -- lpm
456 
     if (simulation = "TRUE") then
457 
       return "DFE";
458 
     else
459 
       return "LPM";
460 
     end if;
461 
   end get_lpm;
462 
 
463 
   -- purpose: Determine TX Electrical Idle Delay
464 
   function get_ei_delay (
465 
     constant simulation : string)
466 
     return integer is
467 
   begin  -- ei_delay
468 
     if (simulation = "TRUE") then
469 
       return 4;
470 
     else
471 
       return 2;
472 
     end if;
473 
   end get_ei_delay;
474 
 
475 
   -- purpose: Determine Link Speed Configuration for GT
476 
   function get_gt_lnk_spd_cfg (
477 
     constant simulation : string)
478 
     return integer is
479 
   begin  -- get_gt_lnk_spd_cfg
480 
     if (simulation = "TRUE") then
481 
       return 2;
482 
     else
483 
       return 3;
484 
     end if;
485 
   end get_gt_lnk_spd_cfg;
486 
 
487 
    -- purpose: Assign the value to PCIE_OOBCLK_MODE depending on the simulation - 0 / synthesis - 1
488 
    function get_oobclk_mode (
489 
      constant simulation : string)
490 
      return integer is
491 
   begin  -- get_oobclk_mode
492 
     if (simulation = "TRUE") then
493 
        return 0;
494 
     else
495 
        return 1;
496 
     end if;
497 
   end get_oobclk_mode;
498 
 
499 
  constant USERCLK2_FREQ : integer := get_usrclk2_freq(USER_CLK2_DIV2, USER_CLK_FREQ);
500 
  constant TCQ           : integer := 1;       -- clock to out delay model
501 
  constant LPM_DFE       : string  := get_lpm(PL_FAST_TRAIN);
502 
  constant LNK_SPD       : integer := get_gt_lnk_spd_cfg(PL_FAST_TRAIN);
503 
  constant EI_DELAY      : integer := get_ei_delay(PL_FAST_TRAIN);
504 
  constant PCIE_OOBCLK_MODE_ENABLE : integer := get_oobclk_mode(PL_FAST_TRAIN);
505 
 
506 
  constant signal_z      : std_logic_vector((18*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0) := (others => '0');
507 
 
508 
  signal gt_rx_phy_status_wire    : std_logic_vector(7 downto 0);
509 
  signal gt_rxchanisaligned_wire  : std_logic_vector(7 downto 0);
510 
  signal gt_rx_data_k_wire        : std_logic_vector(31 downto 0);
511 
  signal gt_rx_data_wire          : std_logic_vector(255 downto 0);
512 
  signal gt_rx_elec_idle_wire     : std_logic_vector(7 downto 0);
513 
  signal gt_rx_status_wire        : std_logic_vector(23 downto 0);
514 
  signal gt_rx_valid_wire         : std_logic_vector(7 downto 0);
515 
  signal gt_rx_polarity           : std_logic_vector(7 downto 0);
516 
  signal gt_power_down            : std_logic_vector(15 downto 0);
517 
  signal gt_tx_char_disp_mode     : std_logic_vector(7 downto 0);
518 
  signal gt_tx_data_k             : std_logic_vector(31 downto 0);
519 
  signal gt_tx_data               : std_logic_vector(255 downto 0);
520 
  signal gt_tx_detect_rx_loopback : std_logic;
521 
  signal gt_tx_elec_idle          : std_logic_vector(7 downto 0);
522 
  signal gt_rx_elec_idle_reset    : std_logic_vector(7 downto 0);
523 
  signal plllkdet                 : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
524 
  signal phystatus_rst            : std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
525 
  signal clock_locked             : std_logic;
526 
  signal pipe_rate_concat         : std_logic_vector(1 downto 0);
527 
 
528 
  signal pipe_tx_deemph_concat    : std_logic_vector((1*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0);
529 
  signal all_phystatus_rst        : std_logic;
530 
  signal gt_rx_phy_status_wire_filter : std_logic_vector(  7 downto 0);
531 
  signal gt_rx_data_k_wire_filter     : std_logic_vector( 31 downto 0);
532 
  signal gt_rx_data_wire_filter       : std_logic_vector(255 downto 0);
533 
  signal gt_rx_elec_idle_wire_filter  : std_logic_vector(  7 downto 0);
534 
  signal gt_rx_status_wire_filter     : std_logic_vector( 23 downto 0);
535 
  signal gt_rx_valid_wire_filter      : std_logic_vector(  7 downto 0);
536 
 
537 
  signal pl_ltssm_state_q             : std_logic_vector(  5 downto 0);
538 
 
539 
  signal plm_in_l0                    : std_logic;
540 
  signal plm_in_rl                    : std_logic;
541 
  signal plm_in_dt                    : std_logic;
542 
  signal plm_in_rs                    : std_logic;
543 
 
544 
  signal pipe_clk_int                 : std_logic;
545 
  signal phy_rdy_n_int                : std_logic;
546 
  signal reg_clock_locked             : std_logic;
547 
 
548 
 
549 
  begin
550 
 
551 
  -- Register pl_ltssm_state
552 
  process(pipe_clk_int,clock_locked)
553 
  begin
554 
     if (clock_locked = '0') then
555 
        pl_ltssm_state_q <= (others => '0') after (TCQ)*1 ps;
556 
     elsif (pipe_clk_int'event and pipe_clk_int = '1') then
557 
        pl_ltssm_state_q <= pl_ltssm_state after (TCQ)*1 ps;
558 
     end if;
559 
  end process;
560 
 
561 
  pipe_clk <= pipe_clk_int;
562 
 
563 
 
564 
  plm_in_l0 <= '1' when (pl_ltssm_state_q = "010110") else '0';
565 
  plm_in_rl <= '1' when (pl_ltssm_state_q = "011100") else '0';
566 
  plm_in_dt <= '1' when (pl_ltssm_state_q = "101101") else '0';
567 
  plm_in_rs <= '1' when (pl_ltssm_state_q = "011111") else '0';
568 
 
569 
  pipe_rate_concat      <= ('0' & pipe_tx_rate);
570 
 
571 
  -- Generate TX Deemph input based on Link Width
572 
  tx_deemph_x1 : if (LINK_CAP_MAX_LINK_WIDTH_int = "000001") generate
573 
    pipe_tx_deemph_concat(0) <= pipe_tx_deemph;
574 
  end generate;
575 
 
576 
  tx_deemph_x2 : if (LINK_CAP_MAX_LINK_WIDTH_int = "000010") generate
577 
    pipe_tx_deemph_concat <= ("0" & pipe_tx_deemph);
578 
  end generate;
579 
 
580 
  tx_deemph_x4 : if (LINK_CAP_MAX_LINK_WIDTH_int = "000100") generate
581 
    pipe_tx_deemph_concat <= ("000" & pipe_tx_deemph);
582 
  end generate;
583 
 
584 
  tx_deemph_x8 : if (LINK_CAP_MAX_LINK_WIDTH_int = "001000") generate
585 
    pipe_tx_deemph_concat <= ("0000000" & pipe_tx_deemph);
586 
  end generate;
587 
 
588 
 
589 
 
590 
--------------RX FILTER Instantiation--------------------------------------------
591 
 
592 
  gt_rx_valid_filter : for i in 0 to (LINK_CAP_MAX_LINK_WIDTH_int - 1) generate
593 
  begin
594 
 
595 
   GT_RX_VALID_FILTER_7x_inst : cl_a7pcie_x4_gt_rx_valid_filter_7x
596 
   generic map (
597 
     CLK_COR_MIN_LAT    => 28,
598 
     TCQ                => 1
599 
   )
600 
   port map(
601 
     USER_RXCHARISK     => gt_rx_data_k_wire( (( 2*i)+ 1+( 2*i)) downto (( 2*i)+ ( 2*i))),        --O
602 
     USER_RXDATA        => gt_rx_data_wire(   ((16*i)+15+(16*i)) downto ((16*i)+ (16*i))),        --O
603 
     USER_RXVALID       => gt_rx_valid_wire(i),                                                   --O
604 
     USER_RXELECIDLE    => gt_rx_elec_idle_wire (i),                                              --O
605 
     USER_RX_STATUS     => gt_rx_status_wire( ((3*i)+ 2) downto (3*i)),                           --O
606 
     USER_RX_PHY_STATUS => gt_rx_phy_status_wire (i),                                             --O
607 
 
608 
     GT_RXCHARISK       => gt_rx_data_k_wire_filter( (( 2*i)+ 1+( 2*i)) downto (( 2*i)+ ( 2*i))), --I
609 
     GT_RXDATA          => gt_rx_data_wire_filter(   ((16*i)+15+(16*i)) downto ((16*i)+ (16*i))), --I
610 
     GT_RXVALID         => gt_rx_valid_wire_filter(i),                                            --I
611 
     GT_RXELECIDLE      => gt_rx_elec_idle_wire_filter(i),                                        --I
612 
     GT_RX_STATUS       => gt_rx_status_wire_filter( (( 3*i)+ 2) downto (3*i)),                   --I
613 
     GT_RX_PHY_STATUS   => gt_rx_phy_status_wire_filter(i),                                       --I
614 
 
615 
     PLM_IN_L0          => plm_in_l0,                                                             --I
616 
     PLM_IN_RS          => plm_in_rs,                                                             --I
617 
     USER_CLK           => pipe_clk_int,                                                          --I
618 
     RESET              => phy_rdy_n_int                                                          --I
619 
   );
620 
 
621 
  end generate;
622 
 
623 
------------ GTX ---------------------------------------------------------------
624 
  pipe_wrapper_i : cl_a7pcie_x4_pipe_wrapper
625 
  generic map (
626 
 
627 
    PCIE_SIM_MODE                  => PL_FAST_TRAIN,
628 
 
629 
    -- pragma synthesis_off
630 
    PCIE_SIM_SPEEDUP               => "TRUE", -- Simulation Speedup
631 
    -- pragma synthesis_on
632 
 
633 
    PCIE_EXT_CLK                   => PCIE_EXT_CLK,
634 
    PCIE_TXBUF_EN                  => PCIE_TXBUF_EN,
635 
    PCIE_GT_DEVICE                 => PCIE_GT_DEVICE,
636 
    PCIE_CHAN_BOND                 => PCIE_CHAN_BOND,
637 
    PCIE_PLL_SEL                   => PCIE_PLL_SEL,
638 
    PCIE_USE_MODE                  => PCIE_USE_MODE,
639 
    PCIE_LPM_DFE                   => LPM_DFE,
640 
    PCIE_LANE                      => LINK_CAP_MAX_LINK_WIDTH_int,
641 
    PCIE_LINK_SPEED                => LNK_SPD,
642 
    PCIE_REFCLK_FREQ               => REF_CLK_FREQ,
643 
    -- PCIE_OOBCLK_MODE               => PCIE_OOBCLK_MODE_ENABLE,
644 
    PCIE_OOBCLK_MODE               => 1,
645 
    PCIE_TX_EIDLE_ASSERT_DELAY     => EI_DELAY,
646 
    PCIE_USERCLK1_FREQ             => (USER_CLK_FREQ +1),
647 
    PCIE_USERCLK2_FREQ             => (USERCLK2_FREQ +1)
648 
 
649 
 
650 
  )
651 
  port map (
652 
 
653 
    ------------ PIPE Clock & Reset Ports ------------------
654 
    PIPE_CLK                        => sys_clk,
655 
    PIPE_RESET_N                    => sys_rst_n,
656 
    PIPE_PCLK                       => pipe_clk_int,
657 
 
658 
    ----------- PIPE TX Data Ports ------------------
659 
    PIPE_TXDATA                    => gt_tx_data((32*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
660 
    PIPE_TXDATAK                   => gt_tx_data_k((4*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
661 
 
662 
    PIPE_TXP                       => pci_exp_txp((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
663 
    PIPE_TXN                       => pci_exp_txn((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
664 
 
665 
    ----------- PIPE RX Data Ports ------------------
666 
    PIPE_RXP                       => pci_exp_rxp((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
667 
    PIPE_RXN                       => pci_exp_rxn((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
668 
 
669 
    PIPE_RXDATA                    => gt_rx_data_wire_filter((32*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
670 
    PIPE_RXDATAK                   => gt_rx_data_k_wire_filter((4*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
671 
 
672 
    ----------- PIPE Command Ports ------------------
673 
    PIPE_TXDETECTRX                => gt_tx_detect_rx_loopback,
674 
    PIPE_TXELECIDLE                => gt_tx_elec_idle((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
675 
    PIPE_TXCOMPLIANCE              => gt_tx_char_disp_mode((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
676 
    PIPE_RXPOLARITY                => gt_rx_polarity((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
677 
    PIPE_POWERDOWN                 => gt_power_down((2*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
678 
    PIPE_RATE                      => pipe_rate_concat,
679 
 
680 
    ----------- PIPE Electrical Command Ports ------------------
681 
    PIPE_TXMARGIN                  => pipe_tx_margin,
682 
    PIPE_TXSWING                   => pipe_tx_swing,
683 
 
684 
    PIPE_TXEQ_CONTROL              => signal_z((2*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
685 
    PIPE_TXEQ_PRESET               =>  signal_z((4*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
686 
    PIPE_TXEQ_PRESET_DEFAULT       =>  signal_z((4*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
687 
 
688 
    PIPE_RXEQ_CONTROL              => signal_z((2*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
689 
    PIPE_RXEQ_PRESET               => signal_z((3*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
690 
    PIPE_RXEQ_LFFS                 => signal_z((6*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
691 
    PIPE_RXEQ_TXPRESET             => signal_z((4*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
692 
 
693 
    PIPE_TXDEEMPH                  => pipe_tx_deemph_concat,
694 
 
695 
    PIPE_TXEQ_COEFF                => open,
696 
    PIPE_RXEQ_USER_EN              => signal_z((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
697 
    PIPE_RXEQ_USER_TXCOEFF         => signal_z((18*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
698 
    PIPE_RXEQ_USER_MODE            => signal_z((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
699 
    PIPE_TXEQ_DEEMPH               => signal_z((6*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
700 
    PIPE_TXEQ_FS                   => open,
701 
    PIPE_TXEQ_LF                   => open,
702 
    PIPE_TXEQ_DONE                 => open,
703 
 
704 
    PIPE_RXEQ_NEW_TXCOEFF          => open,
705 
    PIPE_RXEQ_LFFS_SEL             => open,
706 
    PIPE_RXEQ_ADAPT_DONE           => open,
707 
    PIPE_RXEQ_DONE                 => open,
708 
 
709 
    ----------- PIPE Status Ports -------------------
710 
    PIPE_RXVALID                   => gt_rx_valid_wire_filter((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
711 
    PIPE_PHYSTATUS                 => gt_rx_phy_status_wire_filter((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
712 
    PIPE_PHYSTATUS_RST             => phystatus_rst,
713 
    PIPE_RXELECIDLE                => gt_rx_elec_idle_wire_filter((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
714 
    PIPE_RXSTATUS                  => gt_rx_status_wire_filter((3*LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
715 
    PIPE_RXBUFSTATUS               => open,
716 
 
717 
    ----------- PIPE User Ports ---------------------------
718 
    PIPE_MMCM_RST_N                => PIPE_MMCM_RST_N,        -- Async      | Async
719 
 
720 
    PIPE_RXSLIDE                   => signal_z((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0) ,
721 
 
722 
    PIPE_CPLL_LOCK                 => plllkdet,
723 
    PIPE_QPLL_LOCK                 => open,
724 
    PIPE_PCLK_LOCK                 => clock_locked,
725 
    PIPE_RXCDRLOCK                 => open,
726 
    PIPE_USERCLK1                  => user_clk,
727 
    PIPE_USERCLK2                  => user_clk2,
728 
    PIPE_RXUSRCLK                  => open,
729 
 
730 
    PIPE_RXOUTCLK                  => open,
731 
    PIPE_TXSYNC_DONE               => open,
732 
    PIPE_RXSYNC_DONE               => open,
733 
    PIPE_GEN3_RDY                  => open,
734 
    PIPE_RXCHANISALIGNED           => gt_rxchanisaligned_wire((LINK_CAP_MAX_LINK_WIDTH_int-1) downto 0),
735 
    PIPE_ACTIVE_LANE               => open,
736 
 
737 
    ---------- External Clock Ports ---------------------------
738 
    PIPE_PCLK_IN                   => PIPE_PCLK_IN,
739 
    PIPE_RXUSRCLK_IN               => PIPE_RXUSRCLK_IN,
740 
 
741 
    PIPE_RXOUTCLK_IN               => PIPE_RXOUTCLK_IN,
742 
    PIPE_DCLK_IN                   => PIPE_DCLK_IN,
743 
    PIPE_USERCLK1_IN               => PIPE_USERCLK1_IN,
744 
    PIPE_USERCLK2_IN               => PIPE_USERCLK2_IN,
745 
    PIPE_OOBCLK_IN                 => PIPE_OOBCLK_IN,
746 
    PIPE_JTAG_EN                   => '0',
747 
    PIPE_JTAG_RDY                  => open,
748 
    PIPE_MMCM_LOCK_IN              => PIPE_MMCM_LOCK_IN,
749 
 
750 
    PIPE_TXOUTCLK_OUT              => PIPE_TXOUTCLK_OUT,
751 
    PIPE_RXOUTCLK_OUT              => PIPE_RXOUTCLK_OUT,
752 
    PIPE_PCLK_SEL_OUT              => PIPE_PCLK_SEL_OUT,
753 
    PIPE_GEN3_OUT                  => PIPE_GEN3_OUT,
754 
 
755 
    ----------- PRBS/Loopback Ports ---------------------------
756 
    PIPE_TXPRBSSEL                 => "000",
757 
    PIPE_RXPRBSSEL                 => "000",
758 
    PIPE_TXPRBSFORCEERR            => '0',
759 
    PIPE_RXPRBSCNTRESET            => '0',
760 
    PIPE_LOOPBACK                  => "000",
761 
    PIPE_RXPRBSERR                 => open,
762 
 
763 
    ----------- FSM Ports ---------------------------
764 
    PIPE_RST_FSM                   => open,
765 
    PIPE_QRST_FSM                  => open,
766 
    PIPE_RATE_FSM                  => open,
767 
    PIPE_SYNC_FSM_TX               => open,
768 
    PIPE_SYNC_FSM_RX               => open,
769 
    PIPE_DRP_FSM                   => open,
770 
    PIPE_TXEQ_FSM                  => open,
771 
    PIPE_RXEQ_FSM                  => open,
772 
    PIPE_QDRP_FSM                  => open,
773 
 
774 
    PIPE_RST_IDLE                  => open,
775 
    PIPE_QRST_IDLE                 => open,
776 
    PIPE_RATE_IDLE                 => open,
777 
 
778 
    ----------- Debug Ports ---------------------------
779 
    PIPE_DEBUG_0                   => open,
780 
    PIPE_DEBUG_1                   => open,
781 
    PIPE_DEBUG_2                   => open,
782 
    PIPE_DEBUG_3                   => open,
783 
    PIPE_DEBUG_4                   => open,
784 
    PIPE_DEBUG_5                   => open,
785 
    PIPE_DEBUG_6                   => open,
786 
    PIPE_DEBUG_7                   => open,
787 
    PIPE_DEBUG_8                   => open,
788 
    PIPE_DEBUG_9                   => open,
789 
    PIPE_DEBUG                     => open,
790 
 
791 
    PIPE_DMONITOROUT               => open
792 
 
793 
);
794 
 
795 
  pipe_rx0_phy_status <= gt_rx_phy_status_wire(0);
796 
  pipe_rx1_phy_status <= gt_rx_phy_status_wire(1) when (LINK_CAP_MAX_LINK_WIDTH_int >= 2) else
797 
                         '0';
798 
  pipe_rx2_phy_status <= gt_rx_phy_status_wire(2) when (LINK_CAP_MAX_LINK_WIDTH_int >= 4) else
799 
                         '0';
800 
  pipe_rx3_phy_status <= gt_rx_phy_status_wire(3) when (LINK_CAP_MAX_LINK_WIDTH_int >= 4) else
801 
                         '0';
802 
  pipe_rx4_phy_status <= gt_rx_phy_status_wire(4) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
803 
                         '0';
804 
  pipe_rx5_phy_status <= gt_rx_phy_status_wire(5) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
805 
                         '0';
806 
  pipe_rx6_phy_status <= gt_rx_phy_status_wire(6) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
807 
                         '0';
808 
  pipe_rx7_phy_status <= gt_rx_phy_status_wire(7) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
809 
                         '0';
810 
 
811 
  pipe_rx0_chanisaligned <= gt_rxchanisaligned_wire(0);
812 
  pipe_rx1_chanisaligned <= gt_rxchanisaligned_wire(1) when (LINK_CAP_MAX_LINK_WIDTH_int >= 2) else
813 
                            '0';
814 
  pipe_rx2_chanisaligned <= gt_rxchanisaligned_wire(2) when (LINK_CAP_MAX_LINK_WIDTH_int >= 4) else
815 
                            '0';
816 
  pipe_rx3_chanisaligned <= gt_rxchanisaligned_wire(3) when (LINK_CAP_MAX_LINK_WIDTH_int >= 4) else
817 
                            '0';
818 
  pipe_rx4_chanisaligned <= gt_rxchanisaligned_wire(4) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
819 
                            '0';
820 
  pipe_rx5_chanisaligned <= gt_rxchanisaligned_wire(5) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
821 
                            '0';
822 
  pipe_rx6_chanisaligned <= gt_rxchanisaligned_wire(6) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
823 
                            '0';
824 
  pipe_rx7_chanisaligned <= gt_rxchanisaligned_wire(7) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
825 
                            '0';
826 
 
827 
  --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
828 
  --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
829 
 
830 
  pipe_rx0_char_is_k <= (gt_rx_data_k_wire(1) & gt_rx_data_k_wire(0));
831 
  pipe_rx1_char_is_k <= (gt_rx_data_k_wire(5) & gt_rx_data_k_wire(4)) when (LINK_CAP_MAX_LINK_WIDTH_int >= 2) else
832 
                        "00";
833 
  pipe_rx2_char_is_k <= (gt_rx_data_k_wire(9) & gt_rx_data_k_wire(8)) when (LINK_CAP_MAX_LINK_WIDTH_int >= 4) else
834 
                        "00";
835 
  pipe_rx3_char_is_k <= (gt_rx_data_k_wire(13) & gt_rx_data_k_wire(12)) when (LINK_CAP_MAX_LINK_WIDTH_int >= 4) else
836 
                        "00";
837 
  pipe_rx4_char_is_k <= (gt_rx_data_k_wire(17) & gt_rx_data_k_wire(16)) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
838 
                        "00";
839 
  pipe_rx5_char_is_k <= (gt_rx_data_k_wire(21) & gt_rx_data_k_wire(20)) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
840 
                        "00";
841 
  pipe_rx6_char_is_k <= (gt_rx_data_k_wire(25) & gt_rx_data_k_wire(24)) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
842 
                        "00";
843 
  pipe_rx7_char_is_k <= (gt_rx_data_k_wire(29) & gt_rx_data_k_wire(28)) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
844 
                        "00";
845 
 
846 
  pipe_rx0_data <= (gt_rx_data_wire(15 downto 8) & gt_rx_data_wire(7 downto 0));
847 
  pipe_rx1_data <= (gt_rx_data_wire(47 downto 40) & gt_rx_data_wire(39 downto 32)) when (LINK_CAP_MAX_LINK_WIDTH_int >= 2) else
848 
                   "0000000000000000";
849 
  pipe_rx2_data <= (gt_rx_data_wire(79 downto 72) & gt_rx_data_wire(71 downto 64)) when (LINK_CAP_MAX_LINK_WIDTH_int >= 4) else
850 
                   "0000000000000000";
851 
  pipe_rx3_data <= (gt_rx_data_wire(111 downto 104) & gt_rx_data_wire(103 downto 96)) when (LINK_CAP_MAX_LINK_WIDTH_int >= 4) else
852 
                   "0000000000000000";
853 
  pipe_rx4_data <= (gt_rx_data_wire(143 downto 136) & gt_rx_data_wire(135 downto 128)) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
854 
                   "0000000000000000";
855 
  pipe_rx5_data <= (gt_rx_data_wire(175 downto 168) & gt_rx_data_wire(167 downto 160)) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
856 
                   "0000000000000000";
857 
  pipe_rx6_data <= (gt_rx_data_wire(207 downto 200) & gt_rx_data_wire(199 downto 192)) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
858 
                   "0000000000000000";
859 
  pipe_rx7_data <= (gt_rx_data_wire(239 downto 232) & gt_rx_data_wire(231 downto 224)) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
860 
                   "0000000000000000";
861 
 
862 
  --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
863 
  --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
864 
 
865 
  pipe_rx0_elec_idle <= gt_rx_elec_idle_wire(0);
866 
  pipe_rx1_elec_idle <= gt_rx_elec_idle_wire(1) when (LINK_CAP_MAX_LINK_WIDTH_int >= 2) else
867 
                        '1';
868 
  pipe_rx2_elec_idle <= gt_rx_elec_idle_wire(2) when (LINK_CAP_MAX_LINK_WIDTH_int >= 4) else
869 
                        '1';
870 
  pipe_rx3_elec_idle <= gt_rx_elec_idle_wire(3) when (LINK_CAP_MAX_LINK_WIDTH_int >= 4) else
871 
                        '1';
872 
  pipe_rx4_elec_idle <= gt_rx_elec_idle_wire(4) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
873 
                        '1';
874 
  pipe_rx5_elec_idle <= gt_rx_elec_idle_wire(5) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
875 
                        '1';
876 
  pipe_rx6_elec_idle <= gt_rx_elec_idle_wire(6) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
877 
                        '1';
878 
  pipe_rx7_elec_idle <= gt_rx_elec_idle_wire(7) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
879 
                        '1';
880 
 
881 
  pipe_rx0_status <= gt_rx_status_wire(2 downto 0);
882 
  pipe_rx1_status <= gt_rx_status_wire(5 downto 3) when (LINK_CAP_MAX_LINK_WIDTH_int >= 2) else
883 
                     "000";
884 
  pipe_rx2_status <= gt_rx_status_wire(8 downto 6) when (LINK_CAP_MAX_LINK_WIDTH_int >= 4) else
885 
                     "000";
886 
  pipe_rx3_status <= gt_rx_status_wire(11 downto 9) when (LINK_CAP_MAX_LINK_WIDTH_int >= 4) else
887 
                     "000";
888 
  pipe_rx4_status <= gt_rx_status_wire(14 downto 12) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
889 
                     "000";
890 
  pipe_rx5_status <= gt_rx_status_wire(17 downto 15) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
891 
                     "000";
892 
  pipe_rx6_status <= gt_rx_status_wire(20 downto 18) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
893 
                     "000";
894 
  pipe_rx7_status <= gt_rx_status_wire(23 downto 21) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
895 
                     "000";
896 
 
897 
  pipe_rx0_valid <= gt_rx_valid_wire(0);
898 
  pipe_rx1_valid <= gt_rx_valid_wire(1) when (LINK_CAP_MAX_LINK_WIDTH_int >= 2) else
899 
                    '0';
900 
  pipe_rx2_valid <= gt_rx_valid_wire(2) when (LINK_CAP_MAX_LINK_WIDTH_int >= 4) else
901 
                    '0';
902 
  pipe_rx3_valid <= gt_rx_valid_wire(3) when (LINK_CAP_MAX_LINK_WIDTH_int >= 4) else
903 
                    '0';
904 
  pipe_rx4_valid <= gt_rx_valid_wire(4) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
905 
                    '0';
906 
  pipe_rx5_valid <= gt_rx_valid_wire(5) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
907 
                    '0';
908 
  pipe_rx6_valid <= gt_rx_valid_wire(6) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
909 
                    '0';
910 
  pipe_rx7_valid <= gt_rx_valid_wire(7) when (LINK_CAP_MAX_LINK_WIDTH_int >= 8) else
911 
                    '0';
912 
 
913 
 
914 
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
915 
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
916 
 
917 
gt_rx_polarity(0) <= pipe_rx0_polarity;
918 
gt_rx_polarity(1) <= pipe_rx1_polarity;
919 
gt_rx_polarity(2) <= pipe_rx2_polarity;
920 
gt_rx_polarity(3) <= pipe_rx3_polarity;
921 
gt_rx_polarity(4) <= pipe_rx4_polarity;
922 
gt_rx_polarity(5) <= pipe_rx5_polarity;
923 
gt_rx_polarity(6) <= pipe_rx6_polarity;
924 
gt_rx_polarity(7) <= pipe_rx7_polarity;
925 
 
926 
gt_power_down( 1 downto  0) <= pipe_tx0_powerdown;
927 
gt_power_down( 3 downto  2) <= pipe_tx1_powerdown;
928 
gt_power_down( 5 downto  4) <= pipe_tx2_powerdown;
929 
gt_power_down( 7 downto  6) <= pipe_tx3_powerdown;
930 
gt_power_down( 9 downto  8) <= pipe_tx4_powerdown;
931 
gt_power_down(11 downto 10) <= pipe_tx5_powerdown;
932 
gt_power_down(13 downto 12) <= pipe_tx6_powerdown;
933 
gt_power_down(15 downto 14) <= pipe_tx7_powerdown;
934 
 
935 
 gt_tx_char_disp_mode <= (pipe_tx7_compliance &
936 
                               pipe_tx6_compliance &
937 
                               pipe_tx5_compliance &
938 
                               pipe_tx4_compliance &
939 
                               pipe_tx3_compliance &
940 
                               pipe_tx2_compliance &
941 
                               pipe_tx1_compliance &
942 
                               pipe_tx0_compliance);
943 
 
944 
 
945 
 gt_tx_data_k     <= ("00" &
946 
                     pipe_tx7_char_is_k &
947 
                     "00" &
948 
                     pipe_tx6_char_is_k &
949 
                     "00" &
950 
                     pipe_tx5_char_is_k &
951 
                     "00" &
952 
                     pipe_tx4_char_is_k &
953 
                     "00" &
954 
                     pipe_tx3_char_is_k &
955 
                     "00" &
956 
                     pipe_tx2_char_is_k &
957 
                     "00" &
958 
                     pipe_tx1_char_is_k &
959 
                     "00" &
960 
                     pipe_tx0_char_is_k);
961 
 
962 
  gt_tx_data     <=  (x"0000" &
963 
                     pipe_tx7_data &
964 
                     x"0000" &
965 
                     pipe_tx6_data &
966 
                     x"0000" &
967 
                     pipe_tx5_data &
968 
                     x"0000" &
969 
                     pipe_tx4_data &
970 
                     x"0000" &
971 
                     pipe_tx3_data &
972 
                     x"0000" &
973 
                     pipe_tx2_data &
974 
                     x"0000" &
975 
                     pipe_tx1_data &
976 
                     x"0000" &
977 
                     pipe_tx0_data);
978 
 
979 
 gt_tx_detect_rx_loopback <= pipe_tx_rcvr_det;
980 
 
981 
 gt_tx_elec_idle      <= (pipe_tx7_elec_idle &
982 
                          pipe_tx6_elec_idle &
983 
                          pipe_tx5_elec_idle &
984 
                          pipe_tx4_elec_idle &
985 
                          pipe_tx3_elec_idle &
986 
                          pipe_tx2_elec_idle &
987 
                          pipe_tx1_elec_idle &
988 
                          pipe_tx0_elec_idle);
989 
 
990 
  process(pipe_clk_int,clock_locked)
991 
  begin
992 
    if (clock_locked = '0') then
993 
        reg_clock_locked <= '0' after (TCQ)*1 ps;
994 
    elsif (pipe_clk_int'event and pipe_clk_int='1') then
995 
        reg_clock_locked <= '1' after (TCQ)*1 ps;
996 
    end if;
997 
  end process;
998 
 
999 
  process(pipe_clk_int)
1000 
  begin
1001 
    if (reg_clock_locked = '0') then
1002 
        phy_rdy_n_int <= '0' after (TCQ)*1 ps;
1003 
    elsif (pipe_clk_int'event and pipe_clk_int='1') then
1004 
        phy_rdy_n_int <= all_phystatus_rst after (TCQ)*1 ps;
1005 
    end if;
1006 
  end process;
1007 
 
1008 
 all_phystatus_rst <= and_reduce(phystatus_rst);
1009 
 phy_rdy_n         <= phy_rdy_n_int;
1010 
 
1011 
 
1012 
end pcie_7x;
1013 
 

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