1 |
46 |
dsmv |
-------------------------------------------------------------------------------
|
2 |
|
|
--
|
3 |
|
|
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
|
4 |
|
|
--
|
5 |
|
|
-- This file contains confidential and proprietary information
|
6 |
|
|
-- of Xilinx, Inc. and is protected under U.S. and
|
7 |
|
|
-- international copyright and other intellectual property
|
8 |
|
|
-- laws.
|
9 |
|
|
--
|
10 |
|
|
-- DISCLAIMER
|
11 |
|
|
-- This disclaimer is not a license and does not grant any
|
12 |
|
|
-- rights to the materials distributed herewith. Except as
|
13 |
|
|
-- otherwise provided in a valid license issued to you by
|
14 |
|
|
-- Xilinx, and to the maximum extent permitted by applicable
|
15 |
|
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
16 |
|
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
17 |
|
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
18 |
|
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
19 |
|
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
20 |
|
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
21 |
|
|
-- including negligence, or under any other theory of
|
22 |
|
|
-- liability) for any loss or damage of any kind or nature
|
23 |
|
|
-- related to, arising under or in connection with these
|
24 |
|
|
-- materials, including for any direct, or any indirect,
|
25 |
|
|
-- special, incidental, or consequential loss or damage
|
26 |
|
|
-- (including loss of data, profits, goodwill, or any type of
|
27 |
|
|
-- loss or damage suffered as a result of any action brought
|
28 |
|
|
-- by a third party) even if such damage or loss was
|
29 |
|
|
-- reasonably foreseeable or Xilinx had been advised of the
|
30 |
|
|
-- possibility of the same.
|
31 |
|
|
--
|
32 |
|
|
-- CRITICAL APPLICATIONS
|
33 |
|
|
-- Xilinx products are not designed or intended to be fail-
|
34 |
|
|
-- safe, or for use in any application requiring fail-safe
|
35 |
|
|
-- performance, such as life-support or safety devices or
|
36 |
|
|
-- systems, Class III medical devices, nuclear facilities,
|
37 |
|
|
-- applications related to the deployment of airbags, or any
|
38 |
|
|
-- other applications that could lead to death, personal
|
39 |
|
|
-- injury, or severe property or environmental damage
|
40 |
|
|
-- (individually and collectively, "Critical
|
41 |
|
|
-- Applications"). Customer assumes the sole risk and
|
42 |
|
|
-- liability of any use of Xilinx products in Critical
|
43 |
|
|
-- Applications, subject only to applicable laws and
|
44 |
|
|
-- regulations governing limitations on product liability.
|
45 |
|
|
--
|
46 |
|
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
47 |
|
|
-- PART OF THIS FILE AT ALL TIMES.
|
48 |
|
|
--
|
49 |
|
|
-------------------------------------------------------------------------------
|
50 |
|
|
-- Project : Series-7 Integrated Block for PCI Express
|
51 |
|
|
-- File : cl_a7pcie_x4_pcie_7x.vhd
|
52 |
|
|
-- Version : 1.9
|
53 |
|
|
--
|
54 |
|
|
-- Description: Solution wrapper for Virtex7 Hard Block for PCI Express
|
55 |
|
|
--
|
56 |
|
|
--
|
57 |
|
|
--
|
58 |
|
|
----------------------------------------------------------------------------------
|
59 |
|
|
|
60 |
|
|
library unisim;
|
61 |
|
|
use unisim.vcomponents.all;
|
62 |
|
|
|
63 |
|
|
library IEEE;
|
64 |
|
|
use IEEE.std_logic_1164.all;
|
65 |
|
|
|
66 |
|
|
entity cl_a7pcie_x4_pcie_7x is
|
67 |
|
|
generic (
|
68 |
|
|
C_DATA_WIDTH : INTEGER range 32 to 128 := 64;
|
69 |
|
|
C_REM_WIDTH : INTEGER range 0 to 128 := 1;
|
70 |
|
|
-- PCIE_2_1 params
|
71 |
|
|
AER_BASE_PTR : bit_vector := X"140";
|
72 |
|
|
AER_CAP_ECRC_CHECK_CAPABLE : string := "FALSE";
|
73 |
|
|
AER_CAP_ECRC_GEN_CAPABLE : string := "FALSE";
|
74 |
|
|
AER_CAP_ID : bit_vector := X"0001";
|
75 |
|
|
AER_CAP_MULTIHEADER : string := "FALSE";
|
76 |
|
|
AER_CAP_NEXTPTR : bit_vector := X"178";
|
77 |
|
|
AER_CAP_ON : string := "FALSE";
|
78 |
|
|
AER_CAP_OPTIONAL_ERR_SUPPORT : bit_vector := X"000000";
|
79 |
|
|
AER_CAP_PERMIT_ROOTERR_UPDATE : string := "TRUE";
|
80 |
|
|
AER_CAP_VERSION : bit_vector := X"2";
|
81 |
|
|
ALLOW_X8_GEN2 : string := "FALSE";
|
82 |
|
|
BAR0 : bit_vector := X"FFFFFF00";
|
83 |
|
|
BAR1 : bit_vector := X"FFFF0000";
|
84 |
|
|
BAR2 : bit_vector := X"FFFF000C";
|
85 |
|
|
BAR3 : bit_vector := X"FFFFFFFF";
|
86 |
|
|
BAR4 : bit_vector := X"00000000";
|
87 |
|
|
BAR5 : bit_vector := X"00000000";
|
88 |
|
|
CAPABILITIES_PTR : bit_vector := X"40";
|
89 |
|
|
CARDBUS_CIS_POINTER : bit_vector := X"00000000";
|
90 |
|
|
CFG_ECRC_ERR_CPLSTAT : integer := 0;
|
91 |
|
|
CLASS_CODE : bit_vector := X"000000";
|
92 |
|
|
CMD_INTX_IMPLEMENTED : string := "TRUE";
|
93 |
|
|
CPL_TIMEOUT_DISABLE_SUPPORTED : string := "FALSE";
|
94 |
|
|
CPL_TIMEOUT_RANGES_SUPPORTED : bit_vector := X"0";
|
95 |
|
|
CRM_MODULE_RSTS : bit_vector := X"00";
|
96 |
|
|
DEV_CAP2_ARI_FORWARDING_SUPPORTED : string := "FALSE";
|
97 |
|
|
DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED : string := "FALSE";
|
98 |
|
|
DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED : string := "FALSE";
|
99 |
|
|
DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED : string := "FALSE";
|
100 |
|
|
DEV_CAP2_CAS128_COMPLETER_SUPPORTED : string := "FALSE";
|
101 |
|
|
DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED : string := "FALSE";
|
102 |
|
|
DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED : string := "FALSE";
|
103 |
|
|
DEV_CAP2_LTR_MECHANISM_SUPPORTED : string := "FALSE";
|
104 |
|
|
DEV_CAP2_MAX_ENDEND_TLP_PREFIXES : bit_vector := X"0";
|
105 |
|
|
DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING : string := "FALSE";
|
106 |
|
|
DEV_CAP2_TPH_COMPLETER_SUPPORTED : bit_vector := X"0";
|
107 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE : string := "TRUE";
|
108 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE : string := "TRUE";
|
109 |
|
|
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 0;
|
110 |
|
|
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 0;
|
111 |
|
|
DEV_CAP_EXT_TAG_SUPPORTED : string := "TRUE";
|
112 |
|
|
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE : string := "FALSE";
|
113 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
|
114 |
|
|
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
|
115 |
|
|
DEV_CAP_ROLE_BASED_ERROR : string := "TRUE";
|
116 |
|
|
DEV_CAP_RSVD_14_12 : integer := 0;
|
117 |
|
|
DEV_CAP_RSVD_17_16 : integer := 0;
|
118 |
|
|
DEV_CAP_RSVD_31_29 : integer := 0;
|
119 |
|
|
DEV_CONTROL_AUX_POWER_SUPPORTED : string := "FALSE";
|
120 |
|
|
DEV_CONTROL_EXT_TAG_DEFAULT : string := "FALSE";
|
121 |
|
|
DISABLE_ASPM_L1_TIMER : string := "FALSE";
|
122 |
|
|
DISABLE_BAR_FILTERING : string := "FALSE";
|
123 |
|
|
DISABLE_ERR_MSG : string := "FALSE";
|
124 |
|
|
DISABLE_ID_CHECK : string := "FALSE";
|
125 |
|
|
DISABLE_LANE_REVERSAL : string := "FALSE";
|
126 |
|
|
DISABLE_LOCKED_FILTER : string := "FALSE";
|
127 |
|
|
DISABLE_PPM_FILTER : string := "FALSE";
|
128 |
|
|
DISABLE_RX_POISONED_RESP : string := "FALSE";
|
129 |
|
|
DISABLE_RX_TC_FILTER : string := "FALSE";
|
130 |
|
|
DISABLE_SCRAMBLING : string := "FALSE";
|
131 |
|
|
DNSTREAM_LINK_NUM : bit_vector := X"00";
|
132 |
|
|
DSN_BASE_PTR : bit_vector := X"100";
|
133 |
|
|
DSN_CAP_ID : bit_vector := X"0003";
|
134 |
|
|
DSN_CAP_NEXTPTR : bit_vector := X"10C";
|
135 |
|
|
DSN_CAP_ON : string := "TRUE";
|
136 |
|
|
DSN_CAP_VERSION : bit_vector := X"1";
|
137 |
|
|
ENABLE_MSG_ROUTE : bit_vector := X"000";
|
138 |
|
|
ENABLE_RX_TD_ECRC_TRIM : string := "FALSE";
|
139 |
|
|
ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED : string := "FALSE";
|
140 |
|
|
ENTER_RVRY_EI_L0 : string := "TRUE";
|
141 |
|
|
EXIT_LOOPBACK_ON_EI : string := "TRUE";
|
142 |
|
|
EXPANSION_ROM : bit_vector := X"FFFFF001";
|
143 |
|
|
EXT_CFG_CAP_PTR : bit_vector := X"3F";
|
144 |
|
|
EXT_CFG_XP_CAP_PTR : bit_vector := X"3FF";
|
145 |
|
|
HEADER_TYPE : bit_vector := X"00";
|
146 |
|
|
INFER_EI : bit_vector := X"00";
|
147 |
|
|
INTERRUPT_PIN : bit_vector := X"01";
|
148 |
|
|
INTERRUPT_STAT_AUTO : string := "TRUE";
|
149 |
|
|
IS_SWITCH : string := "FALSE";
|
150 |
|
|
LAST_CONFIG_DWORD : bit_vector := X"3FF";
|
151 |
|
|
LINK_CAP_ASPM_OPTIONALITY : string := "TRUE";
|
152 |
|
|
LINK_CAP_ASPM_SUPPORT : integer := 1;
|
153 |
|
|
LINK_CAP_CLOCK_POWER_MANAGEMENT : string := "FALSE";
|
154 |
|
|
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP : string := "FALSE";
|
155 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
|
156 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
|
157 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_GEN1 : integer := 7;
|
158 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_GEN2 : integer := 7;
|
159 |
|
|
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 : integer := 7;
|
160 |
|
|
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 : integer := 7;
|
161 |
|
|
LINK_CAP_L1_EXIT_LATENCY_GEN1 : integer := 7;
|
162 |
|
|
LINK_CAP_L1_EXIT_LATENCY_GEN2 : integer := 7;
|
163 |
|
|
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP : string := "FALSE";
|
164 |
|
|
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
|
165 |
|
|
LINK_CAP_MAX_LINK_SPEED_int : integer := 1;
|
166 |
|
|
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
|
167 |
|
|
LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
|
168 |
|
|
LINK_CAP_RSVD_23 : integer := 0;
|
169 |
|
|
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE : string := "FALSE";
|
170 |
|
|
LINK_CONTROL_RCB : integer := 0;
|
171 |
|
|
LINK_CTRL2_DEEMPHASIS : string := "FALSE";
|
172 |
|
|
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE : string := "FALSE";
|
173 |
|
|
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
|
174 |
|
|
LINK_STATUS_SLOT_CLOCK_CONFIG : string := "TRUE";
|
175 |
|
|
LL_ACK_TIMEOUT : bit_vector := X"0000";
|
176 |
|
|
LL_ACK_TIMEOUT_EN : string := "FALSE";
|
177 |
|
|
LL_ACK_TIMEOUT_FUNC : integer := 0;
|
178 |
|
|
LL_REPLAY_TIMEOUT : bit_vector := X"0000";
|
179 |
|
|
LL_REPLAY_TIMEOUT_EN : string := "FALSE";
|
180 |
|
|
LL_REPLAY_TIMEOUT_FUNC : integer := 0;
|
181 |
|
|
LTSSM_MAX_LINK_WIDTH : bit_vector := X"01";
|
182 |
|
|
MPS_FORCE : string := "FALSE";
|
183 |
|
|
MSIX_BASE_PTR : bit_vector := X"9C";
|
184 |
|
|
MSIX_CAP_ID : bit_vector := X"11";
|
185 |
|
|
MSIX_CAP_NEXTPTR : bit_vector := X"00";
|
186 |
|
|
MSIX_CAP_ON : string := "FALSE";
|
187 |
|
|
MSIX_CAP_PBA_BIR : integer := 0;
|
188 |
|
|
MSIX_CAP_PBA_OFFSET : bit_vector := X"00000050";
|
189 |
|
|
MSIX_CAP_TABLE_BIR : integer := 0;
|
190 |
|
|
MSIX_CAP_TABLE_OFFSET : bit_vector := X"00000040";
|
191 |
|
|
MSIX_CAP_TABLE_SIZE : bit_vector := X"000";
|
192 |
|
|
MSI_BASE_PTR : bit_vector := X"48";
|
193 |
|
|
MSI_CAP_64_BIT_ADDR_CAPABLE : string := "TRUE";
|
194 |
|
|
MSI_CAP_ID : bit_vector := X"05";
|
195 |
|
|
MSI_CAP_MULTIMSGCAP : integer := 0;
|
196 |
|
|
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
|
197 |
|
|
MSI_CAP_NEXTPTR : bit_vector := X"60";
|
198 |
|
|
MSI_CAP_ON : string := "FALSE";
|
199 |
|
|
MSI_CAP_PER_VECTOR_MASKING_CAPABLE : string := "TRUE";
|
200 |
|
|
N_FTS_COMCLK_GEN1 : integer := 255;
|
201 |
|
|
N_FTS_COMCLK_GEN2 : integer := 255;
|
202 |
|
|
N_FTS_GEN1 : integer := 255;
|
203 |
|
|
N_FTS_GEN2 : integer := 255;
|
204 |
|
|
PCIE_BASE_PTR : bit_vector := X"60";
|
205 |
|
|
PCIE_CAP_CAPABILITY_ID : bit_vector := X"10";
|
206 |
|
|
PCIE_CAP_CAPABILITY_VERSION : bit_vector := X"2";
|
207 |
|
|
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := X"0";
|
208 |
|
|
PCIE_CAP_NEXTPTR : bit_vector := X"9C";
|
209 |
|
|
PCIE_CAP_ON : string := "TRUE";
|
210 |
|
|
PCIE_CAP_RSVD_15_14 : integer := 0;
|
211 |
|
|
PCIE_CAP_SLOT_IMPLEMENTED : string := "FALSE";
|
212 |
|
|
PCIE_REVISION : integer := 2;
|
213 |
|
|
PL_AUTO_CONFIG : integer := 0;
|
214 |
|
|
PL_FAST_TRAIN : string := "FALSE";
|
215 |
|
|
PM_ASPML0S_TIMEOUT : bit_vector := X"0000";
|
216 |
|
|
PM_ASPML0S_TIMEOUT_EN : string := "FALSE";
|
217 |
|
|
PM_ASPML0S_TIMEOUT_FUNC : integer := 0;
|
218 |
|
|
PM_ASPM_FASTEXIT : string := "FALSE";
|
219 |
|
|
PM_BASE_PTR : bit_vector := X"40";
|
220 |
|
|
PM_CAP_AUXCURRENT : integer := 0;
|
221 |
|
|
PM_CAP_D1SUPPORT : string := "TRUE";
|
222 |
|
|
PM_CAP_D2SUPPORT : string := "TRUE";
|
223 |
|
|
PM_CAP_DSI : string := "FALSE";
|
224 |
|
|
PM_CAP_ID : bit_vector := X"01";
|
225 |
|
|
PM_CAP_NEXTPTR : bit_vector := X"48";
|
226 |
|
|
PM_CAP_ON : string := "TRUE";
|
227 |
|
|
PM_CAP_PMESUPPORT : bit_vector := X"0F";
|
228 |
|
|
PM_CAP_PME_CLOCK : string := "FALSE";
|
229 |
|
|
PM_CAP_RSVD_04 : integer := 0;
|
230 |
|
|
PM_CAP_VERSION : integer := 3;
|
231 |
|
|
PM_CSR_B2B3 : string := "FALSE";
|
232 |
|
|
PM_CSR_BPCCEN : string := "FALSE";
|
233 |
|
|
PM_CSR_NOSOFTRST : string := "TRUE";
|
234 |
|
|
PM_DATA0 : bit_vector := X"01";
|
235 |
|
|
PM_DATA1 : bit_vector := X"01";
|
236 |
|
|
PM_DATA2 : bit_vector := X"01";
|
237 |
|
|
PM_DATA3 : bit_vector := X"01";
|
238 |
|
|
PM_DATA4 : bit_vector := X"01";
|
239 |
|
|
PM_DATA5 : bit_vector := X"01";
|
240 |
|
|
PM_DATA6 : bit_vector := X"01";
|
241 |
|
|
PM_DATA7 : bit_vector := X"01";
|
242 |
|
|
PM_DATA_SCALE0 : bit_vector := X"1";
|
243 |
|
|
PM_DATA_SCALE1 : bit_vector := X"1";
|
244 |
|
|
PM_DATA_SCALE2 : bit_vector := X"1";
|
245 |
|
|
PM_DATA_SCALE3 : bit_vector := X"1";
|
246 |
|
|
PM_DATA_SCALE4 : bit_vector := X"1";
|
247 |
|
|
PM_DATA_SCALE5 : bit_vector := X"1";
|
248 |
|
|
PM_DATA_SCALE6 : bit_vector := X"1";
|
249 |
|
|
PM_DATA_SCALE7 : bit_vector := X"1";
|
250 |
|
|
PM_MF : string := "FALSE";
|
251 |
|
|
RBAR_BASE_PTR : bit_vector := X"178";
|
252 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR0 : bit_vector := X"00";
|
253 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR1 : bit_vector := X"00";
|
254 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR2 : bit_vector := X"00";
|
255 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR3 : bit_vector := X"00";
|
256 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR4 : bit_vector := X"00";
|
257 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR5 : bit_vector := X"00";
|
258 |
|
|
RBAR_CAP_ID : bit_vector := X"0015";
|
259 |
|
|
RBAR_CAP_INDEX0 : bit_vector := X"0";
|
260 |
|
|
RBAR_CAP_INDEX1 : bit_vector := X"0";
|
261 |
|
|
RBAR_CAP_INDEX2 : bit_vector := X"0";
|
262 |
|
|
RBAR_CAP_INDEX3 : bit_vector := X"0";
|
263 |
|
|
RBAR_CAP_INDEX4 : bit_vector := X"0";
|
264 |
|
|
RBAR_CAP_INDEX5 : bit_vector := X"0";
|
265 |
|
|
RBAR_CAP_NEXTPTR : bit_vector := X"000";
|
266 |
|
|
RBAR_CAP_ON : string := "FALSE";
|
267 |
|
|
RBAR_CAP_SUP0 : bit_vector := X"00000000";
|
268 |
|
|
RBAR_CAP_SUP1 : bit_vector := X"00000000";
|
269 |
|
|
RBAR_CAP_SUP2 : bit_vector := X"00000000";
|
270 |
|
|
RBAR_CAP_SUP3 : bit_vector := X"00000000";
|
271 |
|
|
RBAR_CAP_SUP4 : bit_vector := X"00000000";
|
272 |
|
|
RBAR_CAP_SUP5 : bit_vector := X"00000000";
|
273 |
|
|
RBAR_CAP_VERSION : bit_vector := X"1";
|
274 |
|
|
RBAR_NUM : bit_vector := X"1";
|
275 |
|
|
RECRC_CHK : integer := 0;
|
276 |
|
|
RECRC_CHK_TRIM : string := "FALSE";
|
277 |
|
|
ROOT_CAP_CRS_SW_VISIBILITY : string := "FALSE";
|
278 |
|
|
RP_AUTO_SPD : bit_vector := X"1";
|
279 |
|
|
RP_AUTO_SPD_LOOPCNT : bit_vector := X"1F";
|
280 |
|
|
SELECT_DLL_IF : string := "FALSE";
|
281 |
|
|
SIM_VERSION : string := "1.0";
|
282 |
|
|
SLOT_CAP_ATT_BUTTON_PRESENT : string := "FALSE";
|
283 |
|
|
SLOT_CAP_ATT_INDICATOR_PRESENT : string := "FALSE";
|
284 |
|
|
SLOT_CAP_ELEC_INTERLOCK_PRESENT : string := "FALSE";
|
285 |
|
|
SLOT_CAP_HOTPLUG_CAPABLE : string := "FALSE";
|
286 |
|
|
SLOT_CAP_HOTPLUG_SURPRISE : string := "FALSE";
|
287 |
|
|
SLOT_CAP_MRL_SENSOR_PRESENT : string := "FALSE";
|
288 |
|
|
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT : string := "FALSE";
|
289 |
|
|
SLOT_CAP_PHYSICAL_SLOT_NUM : bit_vector := X"0000";
|
290 |
|
|
SLOT_CAP_POWER_CONTROLLER_PRESENT : string := "FALSE";
|
291 |
|
|
SLOT_CAP_POWER_INDICATOR_PRESENT : string := "FALSE";
|
292 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_SCALE : integer := 0;
|
293 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_VALUE : bit_vector := X"00";
|
294 |
|
|
SPARE_BIT0 : integer := 0;
|
295 |
|
|
SPARE_BIT1 : integer := 0;
|
296 |
|
|
SPARE_BIT2 : integer := 0;
|
297 |
|
|
SPARE_BIT3 : integer := 0;
|
298 |
|
|
SPARE_BIT4 : integer := 0;
|
299 |
|
|
SPARE_BIT5 : integer := 0;
|
300 |
|
|
SPARE_BIT6 : integer := 0;
|
301 |
|
|
SPARE_BIT7 : integer := 0;
|
302 |
|
|
SPARE_BIT8 : integer := 0;
|
303 |
|
|
SPARE_BYTE0 : bit_vector := X"00";
|
304 |
|
|
SPARE_BYTE1 : bit_vector := X"00";
|
305 |
|
|
SPARE_BYTE2 : bit_vector := X"00";
|
306 |
|
|
SPARE_BYTE3 : bit_vector := X"00";
|
307 |
|
|
SPARE_WORD0 : bit_vector := X"00000000";
|
308 |
|
|
SPARE_WORD1 : bit_vector := X"00000000";
|
309 |
|
|
SPARE_WORD2 : bit_vector := X"00000000";
|
310 |
|
|
SPARE_WORD3 : bit_vector := X"00000000";
|
311 |
|
|
SSL_MESSAGE_AUTO : string := "FALSE";
|
312 |
|
|
TECRC_EP_INV : string := "FALSE";
|
313 |
|
|
TL_RBYPASS : string := "FALSE";
|
314 |
|
|
TL_RX_RAM_RADDR_LATENCY : integer := 0;
|
315 |
|
|
TL_RX_RAM_RDATA_LATENCY : integer := 2;
|
316 |
|
|
TL_RX_RAM_WRITE_LATENCY : integer := 0;
|
317 |
|
|
TL_TFC_DISABLE : string := "FALSE";
|
318 |
|
|
TL_TX_CHECKS_DISABLE : string := "FALSE";
|
319 |
|
|
TL_TX_RAM_RADDR_LATENCY : integer := 0;
|
320 |
|
|
TL_TX_RAM_RDATA_LATENCY : integer := 2;
|
321 |
|
|
TL_TX_RAM_WRITE_LATENCY : integer := 0;
|
322 |
|
|
TRN_DW : string := "FALSE";
|
323 |
|
|
TRN_NP_FC : string := "FALSE";
|
324 |
|
|
UPCONFIG_CAPABLE : string := "TRUE";
|
325 |
|
|
UPSTREAM_FACING : string := "TRUE";
|
326 |
|
|
UR_ATOMIC : string := "TRUE";
|
327 |
|
|
UR_CFG1 : string := "TRUE";
|
328 |
|
|
UR_INV_REQ : string := "TRUE";
|
329 |
|
|
UR_PRS_RESPONSE : string := "TRUE";
|
330 |
|
|
USER_CLK2_DIV2 : string := "FALSE";
|
331 |
|
|
USER_CLK_FREQ : integer := 3;
|
332 |
|
|
USE_RID_PINS : string := "FALSE";
|
333 |
|
|
VC0_CPL_INFINITE : string := "TRUE";
|
334 |
|
|
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
|
335 |
|
|
VC0_TOTAL_CREDITS_CD : integer := 127;
|
336 |
|
|
VC0_TOTAL_CREDITS_CH : integer := 31;
|
337 |
|
|
VC0_TOTAL_CREDITS_NPD : integer := 24;
|
338 |
|
|
VC0_TOTAL_CREDITS_NPH : integer := 12;
|
339 |
|
|
VC0_TOTAL_CREDITS_PD : integer := 288;
|
340 |
|
|
VC0_TOTAL_CREDITS_PH : integer := 32;
|
341 |
|
|
VC0_TX_LASTPACKET : integer := 31;
|
342 |
|
|
VC_BASE_PTR : bit_vector := X"10C";
|
343 |
|
|
VC_CAP_ID : bit_vector := X"0002";
|
344 |
|
|
VC_CAP_NEXTPTR : bit_vector := X"000";
|
345 |
|
|
VC_CAP_ON : string := "FALSE";
|
346 |
|
|
VC_CAP_REJECT_SNOOP_TRANSACTIONS : string := "FALSE";
|
347 |
|
|
VC_CAP_VERSION : bit_vector := X"1";
|
348 |
|
|
VSEC_BASE_PTR : bit_vector := X"128";
|
349 |
|
|
VSEC_CAP_HDR_ID : bit_vector := X"1234";
|
350 |
|
|
VSEC_CAP_HDR_LENGTH : bit_vector := X"018";
|
351 |
|
|
VSEC_CAP_HDR_REVISION : bit_vector := X"1";
|
352 |
|
|
VSEC_CAP_ID : bit_vector := X"000B";
|
353 |
|
|
VSEC_CAP_IS_LINK_VISIBLE : string := "TRUE";
|
354 |
|
|
VSEC_CAP_NEXTPTR : bit_vector := X"140";
|
355 |
|
|
VSEC_CAP_ON : string := "FALSE";
|
356 |
|
|
VSEC_CAP_VERSION : bit_vector := X"1"
|
357 |
|
|
);
|
358 |
|
|
port(
|
359 |
|
|
|
360 |
|
|
trn_td : in std_logic_vector(C_DATA_WIDTH-1 downto 0);
|
361 |
|
|
trn_trem : in std_logic_vector(C_REM_WIDTH-1 downto 0);
|
362 |
|
|
trn_tsof : in std_logic;
|
363 |
|
|
trn_teof : in std_logic;
|
364 |
|
|
trn_tsrc_rdy : in std_logic;
|
365 |
|
|
trn_tsrc_dsc : in std_logic;
|
366 |
|
|
trn_terrfwd : in std_logic;
|
367 |
|
|
trn_tecrc_gen : in std_logic;
|
368 |
|
|
trn_tstr : in std_logic;
|
369 |
|
|
trn_tcfg_gnt : in std_logic;
|
370 |
|
|
trn_rdst_rdy : in std_logic;
|
371 |
|
|
trn_rnp_req : in std_logic;
|
372 |
|
|
trn_rfcp_ret : in std_logic;
|
373 |
|
|
trn_rnp_ok : in std_logic;
|
374 |
|
|
trn_fc_sel : in std_logic_vector( 2 downto 0);
|
375 |
|
|
trn_tdllp_data : in std_logic_vector(31 downto 0);
|
376 |
|
|
trn_tdllp_src_rdy : in std_logic;
|
377 |
|
|
ll2_tlp_rcv : in std_logic;
|
378 |
|
|
ll2_send_enter_l1 : in std_logic;
|
379 |
|
|
ll2_send_enter_l23 : in std_logic;
|
380 |
|
|
ll2_send_as_req_l1 : in std_logic;
|
381 |
|
|
ll2_send_pm_ack : in std_logic;
|
382 |
|
|
pl2_directed_lstate : in std_logic_vector(4 downto 0);
|
383 |
|
|
ll2_suspend_now : in std_logic;
|
384 |
|
|
tl2_ppm_suspend_req : in std_logic;
|
385 |
|
|
tl2_aspm_suspend_credit_check : in std_logic;
|
386 |
|
|
pl_directed_link_change : in std_logic_vector( 1 downto 0);
|
387 |
|
|
pl_directed_link_width : in std_logic_vector( 1 downto 0);
|
388 |
|
|
pl_directed_link_speed : in std_logic;
|
389 |
|
|
pl_directed_link_auton : in std_logic;
|
390 |
|
|
pl_upstream_prefer_deemph : in std_logic;
|
391 |
|
|
pl_downstream_deemph_source : in std_logic;
|
392 |
|
|
pl_directed_ltssm_new_vld : in std_logic;
|
393 |
|
|
pl_directed_ltssm_new : in std_logic_vector( 5 downto 0);
|
394 |
|
|
pl_directed_ltssm_stall : in std_logic;
|
395 |
|
|
pipe_rx0_char_is_k : in std_logic_vector( 1 downto 0);
|
396 |
|
|
pipe_rx1_char_is_k : in std_logic_vector( 1 downto 0);
|
397 |
|
|
pipe_rx2_char_is_k : in std_logic_vector( 1 downto 0);
|
398 |
|
|
pipe_rx3_char_is_k : in std_logic_vector( 1 downto 0);
|
399 |
|
|
pipe_rx4_char_is_k : in std_logic_vector( 1 downto 0);
|
400 |
|
|
pipe_rx5_char_is_k : in std_logic_vector( 1 downto 0);
|
401 |
|
|
pipe_rx6_char_is_k : in std_logic_vector( 1 downto 0);
|
402 |
|
|
pipe_rx7_char_is_k : in std_logic_vector( 1 downto 0);
|
403 |
|
|
pipe_rx0_valid : in std_logic;
|
404 |
|
|
pipe_rx1_valid : in std_logic;
|
405 |
|
|
pipe_rx2_valid : in std_logic;
|
406 |
|
|
pipe_rx3_valid : in std_logic;
|
407 |
|
|
pipe_rx4_valid : in std_logic;
|
408 |
|
|
pipe_rx5_valid : in std_logic;
|
409 |
|
|
pipe_rx6_valid : in std_logic;
|
410 |
|
|
pipe_rx7_valid : in std_logic;
|
411 |
|
|
pipe_rx0_data : in std_logic_vector(15 downto 0);
|
412 |
|
|
pipe_rx1_data : in std_logic_vector(15 downto 0);
|
413 |
|
|
pipe_rx2_data : in std_logic_vector(15 downto 0);
|
414 |
|
|
pipe_rx3_data : in std_logic_vector(15 downto 0);
|
415 |
|
|
pipe_rx4_data : in std_logic_vector(15 downto 0);
|
416 |
|
|
pipe_rx5_data : in std_logic_vector(15 downto 0);
|
417 |
|
|
pipe_rx6_data : in std_logic_vector(15 downto 0);
|
418 |
|
|
pipe_rx7_data : in std_logic_vector(15 downto 0);
|
419 |
|
|
pipe_rx0_chanisaligned : in std_logic;
|
420 |
|
|
pipe_rx1_chanisaligned : in std_logic;
|
421 |
|
|
pipe_rx2_chanisaligned : in std_logic;
|
422 |
|
|
pipe_rx3_chanisaligned : in std_logic;
|
423 |
|
|
pipe_rx4_chanisaligned : in std_logic;
|
424 |
|
|
pipe_rx5_chanisaligned : in std_logic;
|
425 |
|
|
pipe_rx6_chanisaligned : in std_logic;
|
426 |
|
|
pipe_rx7_chanisaligned : in std_logic;
|
427 |
|
|
pipe_rx0_status : in std_logic_vector( 2 downto 0);
|
428 |
|
|
pipe_rx1_status : in std_logic_vector( 2 downto 0);
|
429 |
|
|
pipe_rx2_status : in std_logic_vector( 2 downto 0);
|
430 |
|
|
pipe_rx3_status : in std_logic_vector( 2 downto 0);
|
431 |
|
|
pipe_rx4_status : in std_logic_vector( 2 downto 0);
|
432 |
|
|
pipe_rx5_status : in std_logic_vector( 2 downto 0);
|
433 |
|
|
pipe_rx6_status : in std_logic_vector( 2 downto 0);
|
434 |
|
|
pipe_rx7_status : in std_logic_vector( 2 downto 0);
|
435 |
|
|
pipe_rx0_phy_status : in std_logic;
|
436 |
|
|
pipe_rx1_phy_status : in std_logic;
|
437 |
|
|
pipe_rx2_phy_status : in std_logic;
|
438 |
|
|
pipe_rx3_phy_status : in std_logic;
|
439 |
|
|
pipe_rx4_phy_status : in std_logic;
|
440 |
|
|
pipe_rx5_phy_status : in std_logic;
|
441 |
|
|
pipe_rx6_phy_status : in std_logic;
|
442 |
|
|
pipe_rx7_phy_status : in std_logic;
|
443 |
|
|
pipe_rx0_elec_idle : in std_logic;
|
444 |
|
|
pipe_rx1_elec_idle : in std_logic;
|
445 |
|
|
pipe_rx2_elec_idle : in std_logic;
|
446 |
|
|
pipe_rx3_elec_idle : in std_logic;
|
447 |
|
|
pipe_rx4_elec_idle : in std_logic;
|
448 |
|
|
pipe_rx5_elec_idle : in std_logic;
|
449 |
|
|
pipe_rx6_elec_idle : in std_logic;
|
450 |
|
|
pipe_rx7_elec_idle : in std_logic;
|
451 |
|
|
pipe_clk : in std_logic;
|
452 |
|
|
user_clk : in std_logic;
|
453 |
|
|
user_clk2 : in std_logic;
|
454 |
|
|
user_clk_prebuf : in std_logic;
|
455 |
|
|
user_clk_prebuf_en : in std_logic;
|
456 |
|
|
scanmode_n : in std_logic;
|
457 |
|
|
scanenable_n : in std_logic;
|
458 |
|
|
edt_clk : in std_logic;
|
459 |
|
|
edt_bypass : in std_logic;
|
460 |
|
|
edt_update : in std_logic;
|
461 |
|
|
edt_configuration : in std_logic;
|
462 |
|
|
edt_single_bypass_chain : in std_logic;
|
463 |
|
|
edt_channels_in1 : in std_logic;
|
464 |
|
|
edt_channels_in2 : in std_logic;
|
465 |
|
|
edt_channels_in3 : in std_logic;
|
466 |
|
|
edt_channels_in4 : in std_logic;
|
467 |
|
|
edt_channels_in5 : in std_logic;
|
468 |
|
|
edt_channels_in6 : in std_logic;
|
469 |
|
|
edt_channels_in7 : in std_logic;
|
470 |
|
|
edt_channels_in8 : in std_logic;
|
471 |
|
|
pmv_enable_n : in std_logic;
|
472 |
|
|
pmv_select : in std_logic_vector( 2 downto 0);
|
473 |
|
|
pmv_divide : in std_logic_vector( 1 downto 0);
|
474 |
|
|
sys_rst_n : in std_logic;
|
475 |
|
|
cm_rst_n : in std_logic;
|
476 |
|
|
cm_sticky_rst_n : in std_logic;
|
477 |
|
|
func_lvl_rst_n : in std_logic;
|
478 |
|
|
tl_rst_n : in std_logic;
|
479 |
|
|
dl_rst_n : in std_logic;
|
480 |
|
|
pl_rst_n : in std_logic;
|
481 |
|
|
pl_transmit_hot_rst : in std_logic;
|
482 |
|
|
cfg_reset : in std_logic;
|
483 |
|
|
gwe : in std_logic;
|
484 |
|
|
grestore : in std_logic;
|
485 |
|
|
ghigh : in std_logic;
|
486 |
|
|
cfg_mgmt_di : in std_logic_vector(31 downto 0);
|
487 |
|
|
cfg_mgmt_byte_en_n : in std_logic_vector( 3 downto 0);
|
488 |
|
|
cfg_mgmt_dwaddr : in std_logic_vector( 9 downto 0);
|
489 |
|
|
cfg_mgmt_wr_rw1c_as_rw_n : in std_logic;
|
490 |
|
|
cfg_mgmt_wr_readonly_n : in std_logic;
|
491 |
|
|
cfg_mgmt_wr_en_n : in std_logic;
|
492 |
|
|
cfg_mgmt_rd_en_n : in std_logic;
|
493 |
|
|
cfg_err_malformed_n : in std_logic;
|
494 |
|
|
cfg_err_cor_n : in std_logic;
|
495 |
|
|
cfg_err_ur_n : in std_logic;
|
496 |
|
|
cfg_err_ecrc_n : in std_logic;
|
497 |
|
|
cfg_err_cpl_timeout_n : in std_logic;
|
498 |
|
|
cfg_err_cpl_abort_n : in std_logic;
|
499 |
|
|
cfg_err_cpl_unexpect_n : in std_logic;
|
500 |
|
|
cfg_err_poisoned_n : in std_logic;
|
501 |
|
|
cfg_err_acs_n : in std_logic;
|
502 |
|
|
cfg_err_atomic_egress_blocked_n : in std_logic;
|
503 |
|
|
cfg_err_mc_blocked_n : in std_logic;
|
504 |
|
|
cfg_err_internal_uncor_n : in std_logic;
|
505 |
|
|
cfg_err_internal_cor_n : in std_logic;
|
506 |
|
|
cfg_err_posted_n : in std_logic;
|
507 |
|
|
cfg_err_locked_n : in std_logic;
|
508 |
|
|
cfg_err_norecovery_n : in std_logic;
|
509 |
|
|
cfg_err_aer_headerlog : in std_logic_vector(127 downto 0);
|
510 |
|
|
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
|
511 |
|
|
cfg_interrupt_n : in std_logic;
|
512 |
|
|
cfg_interrupt_di : in std_logic_vector(7 downto 0);
|
513 |
|
|
cfg_interrupt_assert_n : in std_logic;
|
514 |
|
|
cfg_interrupt_stat_n : in std_logic;
|
515 |
|
|
cfg_ds_bus_number : in std_logic_vector(7 downto 0);
|
516 |
|
|
cfg_ds_device_number : in std_logic_vector(4 downto 0);
|
517 |
|
|
cfg_ds_function_number : in std_logic_vector( 2 downto 0);
|
518 |
|
|
cfg_port_number : in std_logic_vector(7 downto 0);
|
519 |
|
|
cfg_pm_halt_aspm_l0s_n : in std_logic;
|
520 |
|
|
cfg_pm_halt_aspm_l1_n : in std_logic;
|
521 |
|
|
cfg_pm_force_state_en_n : in std_logic;
|
522 |
|
|
cfg_pm_force_state : in std_logic_vector(1 downto 0);
|
523 |
|
|
cfg_pm_wake_n : in std_logic;
|
524 |
|
|
cfg_pm_turnoff_ok_n : in std_logic;
|
525 |
|
|
cfg_pm_send_pme_to_n : in std_logic;
|
526 |
|
|
cfg_pciecap_interrupt_msgnum : in std_logic_vector(4 downto 0);
|
527 |
|
|
cfg_trn_pending_n : in std_logic;
|
528 |
|
|
cfg_force_mps : in std_logic_vector( 2 downto 0);
|
529 |
|
|
cfg_force_common_clock_off : in std_logic;
|
530 |
|
|
cfg_force_extended_sync_on : in std_logic;
|
531 |
|
|
cfg_dsn : in std_logic_vector(63 downto 0);
|
532 |
|
|
cfg_aer_interrupt_msgnum : in std_logic_vector(4 downto 0);
|
533 |
|
|
cfg_dev_id : in std_logic_vector(15 downto 0);
|
534 |
|
|
cfg_vend_id : in std_logic_vector(15 downto 0);
|
535 |
|
|
cfg_rev_id : in std_logic_vector(7 downto 0);
|
536 |
|
|
cfg_subsys_id : in std_logic_vector(15 downto 0);
|
537 |
|
|
cfg_subsys_vend_id : in std_logic_vector(15 downto 0);
|
538 |
|
|
drp_clk : in std_logic;
|
539 |
|
|
drp_en : in std_logic;
|
540 |
|
|
drp_we : in std_logic;
|
541 |
|
|
drp_addr : in std_logic_vector(8 downto 0);
|
542 |
|
|
drp_di : in std_logic_vector(15 downto 0);
|
543 |
|
|
drp_rdy : out std_logic;
|
544 |
|
|
drp_do : out std_logic_vector(15 downto 0);
|
545 |
|
|
dbg_mode : in std_logic_vector(1 downto 0);
|
546 |
|
|
dbg_sub_mode : in std_logic;
|
547 |
|
|
pl_dbg_mode : in std_logic_vector( 2 downto 0);
|
548 |
|
|
|
549 |
|
|
trn_clk : out std_logic;
|
550 |
|
|
|
551 |
|
|
trn_tdst_rdy : out std_logic;
|
552 |
|
|
trn_terr_drop : out std_logic;
|
553 |
|
|
trn_tbuf_av : out std_logic_vector( 5 downto 0);
|
554 |
|
|
trn_tcfg_req : out std_logic;
|
555 |
|
|
|
556 |
|
|
trn_rd : out std_logic_vector(C_DATA_WIDTH- 1 downto 0);
|
557 |
|
|
trn_rrem : out std_logic_vector(C_REM_WIDTH- 1 downto 0);
|
558 |
|
|
|
559 |
|
|
trn_rsof : out std_logic;
|
560 |
|
|
trn_reof : out std_logic;
|
561 |
|
|
trn_rsrc_rdy : out std_logic;
|
562 |
|
|
trn_rsrc_dsc : out std_logic;
|
563 |
|
|
trn_recrc_err : out std_logic;
|
564 |
|
|
trn_rerrfwd : out std_logic;
|
565 |
|
|
trn_rbar_hit : out std_logic_vector( 7 downto 0);
|
566 |
|
|
trn_lnk_up : out std_logic;
|
567 |
|
|
trn_fc_ph : out std_logic_vector( 7 downto 0);
|
568 |
|
|
trn_fc_pd : out std_logic_vector(11 downto 0);
|
569 |
|
|
trn_fc_nph : out std_logic_vector( 7 downto 0);
|
570 |
|
|
trn_fc_npd : out std_logic_vector(11 downto 0);
|
571 |
|
|
trn_fc_cplh : out std_logic_vector( 7 downto 0);
|
572 |
|
|
trn_fc_cpld : out std_logic_vector(11 downto 0);
|
573 |
|
|
trn_tdllp_dst_rdy : out std_logic;
|
574 |
|
|
trn_rdllp_data : out std_logic_vector(63 downto 0);
|
575 |
|
|
trn_rdllp_src_rdy : out std_logic_vector( 1 downto 0);
|
576 |
|
|
ll2_tfc_init1_seq : out std_logic;
|
577 |
|
|
ll2_tfc_init2_seq : out std_logic;
|
578 |
|
|
pl2_suspend_ok : out std_logic;
|
579 |
|
|
pl2_recovery : out std_logic;
|
580 |
|
|
pl2_rx_elec_idle : out std_logic;
|
581 |
|
|
pl2_rx_pm_state : out std_logic_vector( 1 downto 0);
|
582 |
|
|
pl2_l0_req : out std_logic;
|
583 |
|
|
ll2_suspend_ok : out std_logic;
|
584 |
|
|
ll2_tx_idle : out std_logic;
|
585 |
|
|
ll2_link_status : out std_logic_vector( 4 downto 0);
|
586 |
|
|
tl2_ppm_suspend_ok : out std_logic;
|
587 |
|
|
tl2_aspm_suspend_req : out std_logic;
|
588 |
|
|
tl2_aspm_suspend_credit_check_ok : out std_logic;
|
589 |
|
|
pl2_link_up : out std_logic;
|
590 |
|
|
pl2_receiver_err : out std_logic;
|
591 |
|
|
ll2_receiver_err : out std_logic;
|
592 |
|
|
ll2_protocol_err : out std_logic;
|
593 |
|
|
ll2_bad_tlp_err : out std_logic;
|
594 |
|
|
ll2_bad_dllp_err : out std_logic;
|
595 |
|
|
ll2_replay_ro_err : out std_logic;
|
596 |
|
|
ll2_replay_to_err : out std_logic;
|
597 |
|
|
tl2_err_hdr : out std_logic_vector(63 downto 0);
|
598 |
|
|
tl2_err_malformed : out std_logic;
|
599 |
|
|
tl2_err_rxoverflow : out std_logic;
|
600 |
|
|
tl2_err_fcpe : out std_logic;
|
601 |
|
|
pl_sel_lnk_rate : out std_logic;
|
602 |
|
|
pl_sel_lnk_width : out std_logic_vector( 1 downto 0);
|
603 |
|
|
pl_ltssm_state : out std_logic_vector( 5 downto 0);
|
604 |
|
|
pl_lane_reversal_mode : out std_logic_vector( 1 downto 0);
|
605 |
|
|
pl_phy_lnk_up_n : out std_logic;
|
606 |
|
|
pl_tx_pm_state : out std_logic_vector( 2 downto 0);
|
607 |
|
|
pl_rx_pm_state : out std_logic_vector( 1 downto 0);
|
608 |
|
|
pl_link_upcfg_cap : out std_logic;
|
609 |
|
|
pl_link_gen2_cap : out std_logic;
|
610 |
|
|
pl_link_partner_gen2_supported : out std_logic;
|
611 |
|
|
pl_initial_link_width : out std_logic_vector( 2 downto 0);
|
612 |
|
|
pl_directed_change_done : out std_logic;
|
613 |
|
|
pipe_tx_rcvr_det : out std_logic;
|
614 |
|
|
pipe_tx_reset : out std_logic;
|
615 |
|
|
pipe_tx_rate : out std_logic;
|
616 |
|
|
pipe_tx_deemph : out std_logic;
|
617 |
|
|
pipe_tx_margin : out std_logic_vector( 2 downto 0);
|
618 |
|
|
pipe_rx0_polarity : out std_logic;
|
619 |
|
|
pipe_rx1_polarity : out std_logic;
|
620 |
|
|
pipe_rx2_polarity : out std_logic;
|
621 |
|
|
pipe_rx3_polarity : out std_logic;
|
622 |
|
|
pipe_rx4_polarity : out std_logic;
|
623 |
|
|
pipe_rx5_polarity : out std_logic;
|
624 |
|
|
pipe_rx6_polarity : out std_logic;
|
625 |
|
|
pipe_rx7_polarity : out std_logic;
|
626 |
|
|
pipe_tx0_compliance : out std_logic;
|
627 |
|
|
pipe_tx1_compliance : out std_logic;
|
628 |
|
|
pipe_tx2_compliance : out std_logic;
|
629 |
|
|
pipe_tx3_compliance : out std_logic;
|
630 |
|
|
pipe_tx4_compliance : out std_logic;
|
631 |
|
|
pipe_tx5_compliance : out std_logic;
|
632 |
|
|
pipe_tx6_compliance : out std_logic;
|
633 |
|
|
pipe_tx7_compliance : out std_logic;
|
634 |
|
|
pipe_tx0_char_is_k : out std_logic_vector( 1 downto 0);
|
635 |
|
|
pipe_tx1_char_is_k : out std_logic_vector( 1 downto 0);
|
636 |
|
|
pipe_tx2_char_is_k : out std_logic_vector( 1 downto 0);
|
637 |
|
|
pipe_tx3_char_is_k : out std_logic_vector( 1 downto 0);
|
638 |
|
|
pipe_tx4_char_is_k : out std_logic_vector( 1 downto 0);
|
639 |
|
|
pipe_tx5_char_is_k : out std_logic_vector( 1 downto 0);
|
640 |
|
|
pipe_tx6_char_is_k : out std_logic_vector( 1 downto 0);
|
641 |
|
|
pipe_tx7_char_is_k : out std_logic_vector( 1 downto 0);
|
642 |
|
|
pipe_tx0_data : out std_logic_vector(15 downto 0);
|
643 |
|
|
pipe_tx1_data : out std_logic_vector(15 downto 0);
|
644 |
|
|
pipe_tx2_data : out std_logic_vector(15 downto 0);
|
645 |
|
|
pipe_tx3_data : out std_logic_vector(15 downto 0);
|
646 |
|
|
pipe_tx4_data : out std_logic_vector(15 downto 0);
|
647 |
|
|
pipe_tx5_data : out std_logic_vector(15 downto 0);
|
648 |
|
|
pipe_tx6_data : out std_logic_vector(15 downto 0);
|
649 |
|
|
pipe_tx7_data : out std_logic_vector(15 downto 0);
|
650 |
|
|
pipe_tx0_elec_idle : out std_logic;
|
651 |
|
|
pipe_tx1_elec_idle : out std_logic;
|
652 |
|
|
pipe_tx2_elec_idle : out std_logic;
|
653 |
|
|
pipe_tx3_elec_idle : out std_logic;
|
654 |
|
|
pipe_tx4_elec_idle : out std_logic;
|
655 |
|
|
pipe_tx5_elec_idle : out std_logic;
|
656 |
|
|
pipe_tx6_elec_idle : out std_logic;
|
657 |
|
|
pipe_tx7_elec_idle : out std_logic;
|
658 |
|
|
pipe_tx0_powerdown : out std_logic_vector( 1 downto 0);
|
659 |
|
|
pipe_tx1_powerdown : out std_logic_vector( 1 downto 0);
|
660 |
|
|
pipe_tx2_powerdown : out std_logic_vector( 1 downto 0);
|
661 |
|
|
pipe_tx3_powerdown : out std_logic_vector( 1 downto 0);
|
662 |
|
|
pipe_tx4_powerdown : out std_logic_vector( 1 downto 0);
|
663 |
|
|
pipe_tx5_powerdown : out std_logic_vector( 1 downto 0);
|
664 |
|
|
pipe_tx6_powerdown : out std_logic_vector( 1 downto 0);
|
665 |
|
|
pipe_tx7_powerdown : out std_logic_vector( 1 downto 0);
|
666 |
|
|
pmv_out : out std_logic;
|
667 |
|
|
user_rst_n : out std_logic;
|
668 |
|
|
pl_received_hot_rst : out std_logic;
|
669 |
|
|
received_func_lvl_rst_n : out std_logic;
|
670 |
|
|
lnk_clk_en : out std_logic;
|
671 |
|
|
cfg_mgmt_do : out std_logic_vector(31 downto 0);
|
672 |
|
|
cfg_mgmt_rd_wr_done_n : out std_logic;
|
673 |
|
|
cfg_err_aer_headerlog_set_n : out std_logic;
|
674 |
|
|
cfg_err_cpl_rdy_n : out std_logic;
|
675 |
|
|
cfg_interrupt_rdy_n : out std_logic;
|
676 |
|
|
cfg_interrupt_mmenable : out std_logic_vector( 2 downto 0);
|
677 |
|
|
cfg_interrupt_msienable : out std_logic;
|
678 |
|
|
cfg_interrupt_do : out std_logic_vector( 7 downto 0);
|
679 |
|
|
cfg_interrupt_msixenable : out std_logic;
|
680 |
|
|
cfg_interrupt_msixfm : out std_logic;
|
681 |
|
|
cfg_msg_received : out std_logic;
|
682 |
|
|
cfg_msg_data : out std_logic_vector(15 downto 0);
|
683 |
|
|
cfg_msg_received_err_cor : out std_logic;
|
684 |
|
|
cfg_msg_received_err_non_fatal : out std_logic;
|
685 |
|
|
cfg_msg_received_err_fatal : out std_logic;
|
686 |
|
|
cfg_msg_received_assert_int_a : out std_logic;
|
687 |
|
|
cfg_msg_received_deassert_int_a : out std_logic;
|
688 |
|
|
cfg_msg_received_assert_int_b : out std_logic;
|
689 |
|
|
cfg_msg_received_deassert_int_b : out std_logic;
|
690 |
|
|
cfg_msg_received_assert_int_c : out std_logic;
|
691 |
|
|
cfg_msg_received_deassert_int_c : out std_logic;
|
692 |
|
|
cfg_msg_received_assert_int_d : out std_logic;
|
693 |
|
|
cfg_msg_received_deassert_int_d : out std_logic;
|
694 |
|
|
cfg_msg_received_pm_pme : out std_logic;
|
695 |
|
|
cfg_msg_received_pme_to_ack : out std_logic;
|
696 |
|
|
cfg_msg_received_pme_to : out std_logic;
|
697 |
|
|
cfg_msg_received_setslotpowerlimit : out std_logic;
|
698 |
|
|
cfg_msg_received_unlock : out std_logic;
|
699 |
|
|
cfg_msg_received_pm_as_nak : out std_logic;
|
700 |
|
|
cfg_pcie_link_state : out std_logic_vector( 2 downto 0);
|
701 |
|
|
cfg_pm_rcv_as_req_l1_n : out std_logic;
|
702 |
|
|
cfg_pm_rcv_enter_l1_n : out std_logic;
|
703 |
|
|
cfg_pm_rcv_enter_l23_n : out std_logic;
|
704 |
|
|
cfg_pm_rcv_req_ack_n : out std_logic;
|
705 |
|
|
cfg_pmcsr_powerstate : out std_logic_vector( 1 downto 0);
|
706 |
|
|
cfg_pmcsr_pme_en : out std_logic;
|
707 |
|
|
cfg_pmcsr_pme_status : out std_logic;
|
708 |
|
|
cfg_transaction : out std_logic;
|
709 |
|
|
cfg_transaction_type : out std_logic;
|
710 |
|
|
cfg_transaction_addr : out std_logic_vector( 6 downto 0);
|
711 |
|
|
cfg_command_io_enable : out std_logic;
|
712 |
|
|
cfg_command_mem_enable : out std_logic;
|
713 |
|
|
cfg_command_bus_master_enable : out std_logic;
|
714 |
|
|
cfg_command_interrupt_disable : out std_logic;
|
715 |
|
|
cfg_command_serr_en : out std_logic;
|
716 |
|
|
cfg_bridge_serr_en : out std_logic;
|
717 |
|
|
cfg_dev_status_corr_err_detected : out std_logic;
|
718 |
|
|
cfg_dev_status_non_fatal_err_detected : out std_logic;
|
719 |
|
|
cfg_dev_status_fatal_err_detected : out std_logic;
|
720 |
|
|
cfg_dev_status_ur_detected : out std_logic;
|
721 |
|
|
cfg_dev_control_corr_err_reporting_en : out std_logic;
|
722 |
|
|
cfg_dev_control_non_fatal_reporting_en : out std_logic;
|
723 |
|
|
cfg_dev_control_fatal_err_reporting_en : out std_logic;
|
724 |
|
|
cfg_dev_control_ur_err_reporting_en : out std_logic;
|
725 |
|
|
cfg_dev_control_enable_ro : out std_logic;
|
726 |
|
|
cfg_dev_control_max_payload : out std_logic_vector( 2 downto 0);
|
727 |
|
|
cfg_dev_control_ext_tag_en : out std_logic;
|
728 |
|
|
cfg_dev_control_phantom_en : out std_logic;
|
729 |
|
|
cfg_dev_control_aux_power_en : out std_logic;
|
730 |
|
|
cfg_dev_control_no_snoop_en : out std_logic;
|
731 |
|
|
cfg_dev_control_max_read_req : out std_logic_vector( 2 downto 0);
|
732 |
|
|
cfg_link_status_current_speed : out std_logic_vector( 1 downto 0);
|
733 |
|
|
cfg_link_status_negotiated_width : out std_logic_vector( 3 downto 0);
|
734 |
|
|
cfg_link_status_link_training : out std_logic;
|
735 |
|
|
cfg_link_status_dll_active : out std_logic;
|
736 |
|
|
cfg_link_status_bandwidth_status : out std_logic;
|
737 |
|
|
cfg_link_status_auto_bandwidth_status : out std_logic;
|
738 |
|
|
cfg_link_control_aspm_control : out std_logic_vector( 1 downto 0);
|
739 |
|
|
cfg_link_control_rcb : out std_logic;
|
740 |
|
|
cfg_link_control_link_disable : out std_logic;
|
741 |
|
|
cfg_link_control_retrain_link : out std_logic;
|
742 |
|
|
cfg_link_control_common_clock : out std_logic;
|
743 |
|
|
cfg_link_control_extended_sync : out std_logic;
|
744 |
|
|
cfg_link_control_clock_pm_en : out std_logic;
|
745 |
|
|
cfg_link_control_hw_auto_width_dis : out std_logic;
|
746 |
|
|
cfg_link_control_bandwidth_int_en : out std_logic;
|
747 |
|
|
cfg_link_control_auto_bandwidth_int_en : out std_logic;
|
748 |
|
|
cfg_dev_control2_cpl_timeout_val : out std_logic_vector( 3 downto 0);
|
749 |
|
|
cfg_dev_control2_cpl_timeout_dis : out std_logic;
|
750 |
|
|
cfg_dev_control2_ari_forward_en : out std_logic;
|
751 |
|
|
cfg_dev_control2_atomic_requester_en : out std_logic;
|
752 |
|
|
cfg_dev_control2_atomic_egress_block : out std_logic;
|
753 |
|
|
cfg_dev_control2_ido_req_en : out std_logic;
|
754 |
|
|
cfg_dev_control2_ido_cpl_en : out std_logic;
|
755 |
|
|
cfg_dev_control2_ltr_en : out std_logic;
|
756 |
|
|
cfg_dev_control2_tlp_prefix_block : out std_logic;
|
757 |
|
|
cfg_slot_control_electromech_il_ctl_pulse : out std_logic;
|
758 |
|
|
cfg_root_control_syserr_corr_err_en : out std_logic;
|
759 |
|
|
cfg_root_control_syserr_non_fatal_err_en : out std_logic;
|
760 |
|
|
cfg_root_control_syserr_fatal_err_en : out std_logic;
|
761 |
|
|
cfg_root_control_pme_int_en : out std_logic;
|
762 |
|
|
cfg_aer_ecrc_check_en : out std_logic;
|
763 |
|
|
cfg_aer_ecrc_gen_en : out std_logic;
|
764 |
|
|
cfg_aer_rooterr_corr_err_reporting_en : out std_logic;
|
765 |
|
|
cfg_aer_rooterr_non_fatal_err_reporting_en : out std_logic;
|
766 |
|
|
cfg_aer_rooterr_fatal_err_reporting_en : out std_logic;
|
767 |
|
|
cfg_aer_rooterr_corr_err_received : out std_logic;
|
768 |
|
|
cfg_aer_rooterr_non_fatal_err_received : out std_logic;
|
769 |
|
|
cfg_aer_rooterr_fatal_err_received : out std_logic;
|
770 |
|
|
cfg_vc_tcvc_map : out std_logic_vector( 6 downto 0);
|
771 |
|
|
dbg_vec_a : out std_logic_vector(63 downto 0);
|
772 |
|
|
dbg_vec_b : out std_logic_vector(63 downto 0);
|
773 |
|
|
dbg_vec_c : out std_logic_vector(11 downto 0);
|
774 |
|
|
dbg_sclr_a : out std_logic;
|
775 |
|
|
dbg_sclr_b : out std_logic;
|
776 |
|
|
dbg_sclr_c : out std_logic;
|
777 |
|
|
dbg_sclr_d : out std_logic;
|
778 |
|
|
dbg_sclr_e : out std_logic;
|
779 |
|
|
dbg_sclr_f : out std_logic;
|
780 |
|
|
dbg_sclr_g : out std_logic;
|
781 |
|
|
dbg_sclr_h : out std_logic;
|
782 |
|
|
dbg_sclr_i : out std_logic;
|
783 |
|
|
dbg_sclr_j : out std_logic;
|
784 |
|
|
dbg_sclr_k : out std_logic;
|
785 |
|
|
pl_dbg_vec : out std_logic_vector(11 downto 0);
|
786 |
|
|
xil_unconn_out : out std_logic_vector(18 downto 0)
|
787 |
|
|
);
|
788 |
|
|
|
789 |
|
|
end cl_a7pcie_x4_pcie_7x;
|
790 |
|
|
|
791 |
|
|
architecture rtl of cl_a7pcie_x4_pcie_7x is
|
792 |
|
|
---------------------------
|
793 |
|
|
-- Component Declarations
|
794 |
|
|
---------------------------
|
795 |
|
|
component cl_a7pcie_x4_pcie_bram_top_7x
|
796 |
|
|
generic (
|
797 |
|
|
LINK_CAP_MAX_LINK_SPEED : integer;
|
798 |
|
|
LINK_CAP_MAX_LINK_WIDTH : integer;
|
799 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer;
|
800 |
|
|
VC0_TX_LASTPACKET : integer;
|
801 |
|
|
TL_TX_RAM_RADDR_LATENCY : integer;
|
802 |
|
|
TL_TX_RAM_RDATA_LATENCY : integer;
|
803 |
|
|
TL_TX_RAM_WRITE_LATENCY : integer;
|
804 |
|
|
VC0_RX_RAM_LIMIT : bit_vector;
|
805 |
|
|
TL_RX_RAM_RADDR_LATENCY : integer;
|
806 |
|
|
TL_RX_RAM_RDATA_LATENCY : integer;
|
807 |
|
|
TL_RX_RAM_WRITE_LATENCY : integer
|
808 |
|
|
);
|
809 |
|
|
port (
|
810 |
|
|
user_clk_i : in std_logic;
|
811 |
|
|
reset_i : in std_logic;
|
812 |
|
|
|
813 |
|
|
mim_tx_waddr : in std_logic_vector(12 downto 0);
|
814 |
|
|
mim_tx_wen : in std_logic;
|
815 |
|
|
mim_tx_ren : in std_logic;
|
816 |
|
|
mim_tx_rce : in std_logic;
|
817 |
|
|
mim_tx_wdata : in std_logic_vector(71 downto 0);
|
818 |
|
|
mim_tx_raddr : in std_logic_vector(12 downto 0);
|
819 |
|
|
mim_tx_rdata : out std_logic_vector(71 downto 0);
|
820 |
|
|
|
821 |
|
|
mim_rx_waddr : in std_logic_vector(12 downto 0);
|
822 |
|
|
mim_rx_wen : in std_logic;
|
823 |
|
|
mim_rx_ren : in std_logic;
|
824 |
|
|
mim_rx_rce : in std_logic;
|
825 |
|
|
mim_rx_wdata : in std_logic_vector(71 downto 0);
|
826 |
|
|
mim_rx_raddr : in std_logic_vector(12 downto 0);
|
827 |
|
|
mim_rx_rdata : out std_logic_vector(71 downto 0)
|
828 |
|
|
);
|
829 |
|
|
end component;
|
830 |
|
|
|
831 |
|
|
--------------------------------------------------------------------------
|
832 |
|
|
-- BRAM --
|
833 |
|
|
--------------------------------------------------------------------------
|
834 |
|
|
|
835 |
|
|
-- transmit bram interface
|
836 |
|
|
signal mim_tx_wen : std_logic;
|
837 |
|
|
signal mim_tx_waddr : std_logic_vector(12 downto 0);
|
838 |
|
|
signal mim_tx_wdata : std_logic_vector(68 downto 0);
|
839 |
|
|
signal mim_tx_wdata_int : std_logic_vector(71 downto 0);
|
840 |
|
|
signal mim_tx_ren : std_logic;
|
841 |
|
|
signal mim_tx_rce : std_logic;
|
842 |
|
|
signal mim_tx_raddr : std_logic_vector(12 downto 0);
|
843 |
|
|
signal mim_tx_rdata : std_logic_vector(68 downto 0);
|
844 |
|
|
-- signal unused_mim_tx_rdata : std_logic_vector( 2 downto 0);
|
845 |
|
|
signal mim_tx_rdata_int : std_logic_vector(71 downto 0);
|
846 |
|
|
|
847 |
|
|
|
848 |
|
|
-- receive bram interface
|
849 |
|
|
signal mim_rx_wen : std_logic;
|
850 |
|
|
signal mim_rx_waddr : std_logic_vector(12 downto 0);
|
851 |
|
|
signal mim_rx_wdata : std_logic_vector(67 downto 0);
|
852 |
|
|
signal mim_rx_wdata_int : std_logic_vector(71 downto 0);
|
853 |
|
|
signal mim_rx_ren : std_logic;
|
854 |
|
|
signal mim_rx_rce : std_logic;
|
855 |
|
|
signal mim_rx_raddr : std_logic_vector(12 downto 0);
|
856 |
|
|
signal mim_rx_rdata : std_logic_vector(67 downto 0);
|
857 |
|
|
-- signal unused_mim_rx_rdata : std_logic_vector( 3 downto 0);
|
858 |
|
|
signal mim_rx_rdata_int : std_logic_vector(71 downto 0);
|
859 |
|
|
|
860 |
|
|
signal trn_tdst_rdy_bus : std_logic_vector( 3 downto 0);
|
861 |
|
|
signal trn_rd_int : std_logic_vector(127 downto 0);
|
862 |
|
|
signal trn_rrem_int : std_logic_vector(1 downto 0);
|
863 |
|
|
signal trn_td_int : std_logic_vector(127 downto 0);
|
864 |
|
|
signal trn_trem_int : std_logic_vector(1 downto 0);
|
865 |
|
|
|
866 |
|
|
|
867 |
|
|
begin
|
868 |
|
|
trn_rd <= trn_rd_int((C_DATA_WIDTH-1) downto 0);
|
869 |
|
|
trn_rrem <= trn_rrem_int((C_REM_WIDTH- 1) downto 0);
|
870 |
|
|
|
871 |
|
|
wire_scaling_128 : if (C_DATA_WIDTH = 128) generate
|
872 |
|
|
trn_td_int <= trn_td ;
|
873 |
|
|
trn_trem_int <= trn_trem;
|
874 |
|
|
end generate;
|
875 |
|
|
|
876 |
|
|
wire_scaling_64 : if (C_DATA_WIDTH = 64) generate
|
877 |
|
|
trn_td_int <= (X"0000000000000000" & trn_td);
|
878 |
|
|
trn_trem_int <= ('0' & trn_trem);
|
879 |
|
|
end generate;
|
880 |
|
|
|
881 |
|
|
|
882 |
|
|
-- Assignments to outputs
|
883 |
|
|
trn_clk <= user_clk2;
|
884 |
|
|
trn_tdst_rdy <= trn_tdst_rdy_bus(0);
|
885 |
|
|
|
886 |
|
|
mim_tx_wdata_int <= "000" & mim_tx_wdata;
|
887 |
|
|
mim_tx_rce <= '1';
|
888 |
|
|
mim_tx_rdata <= mim_tx_rdata_int(68 downto 0);
|
889 |
|
|
mim_rx_wdata_int <= "0000" & mim_rx_wdata;
|
890 |
|
|
mim_rx_rce <= '1';
|
891 |
|
|
mim_rx_rdata <= mim_rx_rdata_int(67 downto 0);
|
892 |
|
|
|
893 |
|
|
pcie_bram_top : cl_a7pcie_x4_pcie_bram_top_7x
|
894 |
|
|
generic map (
|
895 |
|
|
LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED_int,
|
896 |
|
|
LINK_CAP_MAX_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH_int,
|
897 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED,
|
898 |
|
|
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET,
|
899 |
|
|
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY,
|
900 |
|
|
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY,
|
901 |
|
|
TL_TX_RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY,
|
902 |
|
|
VC0_RX_RAM_LIMIT => VC0_RX_RAM_LIMIT,
|
903 |
|
|
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY,
|
904 |
|
|
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY,
|
905 |
|
|
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY
|
906 |
|
|
)
|
907 |
|
|
port map (
|
908 |
|
|
user_clk_i => user_clk,
|
909 |
|
|
reset_i => '0',
|
910 |
|
|
|
911 |
|
|
mim_tx_waddr => mim_tx_waddr,
|
912 |
|
|
mim_tx_wen => mim_tx_wen,
|
913 |
|
|
mim_tx_ren => mim_tx_ren,
|
914 |
|
|
mim_tx_rce => mim_tx_rce,
|
915 |
|
|
mim_tx_wdata => mim_tx_wdata_int,
|
916 |
|
|
mim_tx_raddr => mim_tx_raddr,
|
917 |
|
|
mim_tx_rdata => mim_tx_rdata_int,
|
918 |
|
|
|
919 |
|
|
mim_rx_waddr => mim_rx_waddr,
|
920 |
|
|
mim_rx_wen => mim_rx_wen,
|
921 |
|
|
mim_rx_ren => mim_rx_ren,
|
922 |
|
|
mim_rx_rce => mim_rx_rce,
|
923 |
|
|
mim_rx_wdata => mim_rx_wdata_int,
|
924 |
|
|
mim_rx_raddr => mim_rx_raddr,
|
925 |
|
|
mim_rx_rdata => mim_rx_rdata_int
|
926 |
|
|
);
|
927 |
|
|
|
928 |
|
|
---------------------------------------------------------
|
929 |
|
|
-- Virtex7 PCI Express Block Module
|
930 |
|
|
---------------------------------------------------------
|
931 |
|
|
|
932 |
|
|
pcie_block_i : PCIE_2_1
|
933 |
|
|
generic map (
|
934 |
|
|
AER_BASE_PTR => AER_BASE_PTR ,
|
935 |
|
|
AER_CAP_ECRC_CHECK_CAPABLE => AER_CAP_ECRC_CHECK_CAPABLE ,
|
936 |
|
|
AER_CAP_ECRC_GEN_CAPABLE => AER_CAP_ECRC_GEN_CAPABLE ,
|
937 |
|
|
AER_CAP_ID => AER_CAP_ID ,
|
938 |
|
|
AER_CAP_MULTIHEADER => AER_CAP_MULTIHEADER ,
|
939 |
|
|
AER_CAP_NEXTPTR => AER_CAP_NEXTPTR ,
|
940 |
|
|
AER_CAP_ON => AER_CAP_ON ,
|
941 |
|
|
AER_CAP_OPTIONAL_ERR_SUPPORT => AER_CAP_OPTIONAL_ERR_SUPPORT ,
|
942 |
|
|
AER_CAP_PERMIT_ROOTERR_UPDATE => AER_CAP_PERMIT_ROOTERR_UPDATE ,
|
943 |
|
|
AER_CAP_VERSION => AER_CAP_VERSION ,
|
944 |
|
|
ALLOW_X8_GEN2 => ALLOW_X8_GEN2 ,
|
945 |
|
|
BAR0 => BAR0 ,
|
946 |
|
|
BAR1 => BAR1 ,
|
947 |
|
|
BAR2 => BAR2 ,
|
948 |
|
|
BAR3 => BAR3 ,
|
949 |
|
|
BAR4 => BAR4 ,
|
950 |
|
|
BAR5 => BAR5 ,
|
951 |
|
|
CAPABILITIES_PTR => CAPABILITIES_PTR ,
|
952 |
|
|
CARDBUS_CIS_POINTER => CARDBUS_CIS_POINTER ,
|
953 |
|
|
CFG_ECRC_ERR_CPLSTAT => CFG_ECRC_ERR_CPLSTAT ,
|
954 |
|
|
CLASS_CODE => CLASS_CODE ,
|
955 |
|
|
CMD_INTX_IMPLEMENTED => CMD_INTX_IMPLEMENTED ,
|
956 |
|
|
CPL_TIMEOUT_DISABLE_SUPPORTED => CPL_TIMEOUT_DISABLE_SUPPORTED ,
|
957 |
|
|
CPL_TIMEOUT_RANGES_SUPPORTED => CPL_TIMEOUT_RANGES_SUPPORTED ,
|
958 |
|
|
CRM_MODULE_RSTS => CRM_MODULE_RSTS ,
|
959 |
|
|
DEV_CAP2_ARI_FORWARDING_SUPPORTED => DEV_CAP2_ARI_FORWARDING_SUPPORTED ,
|
960 |
|
|
DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED => DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ,
|
961 |
|
|
DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED => DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ,
|
962 |
|
|
DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED => DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ,
|
963 |
|
|
DEV_CAP2_CAS128_COMPLETER_SUPPORTED => DEV_CAP2_CAS128_COMPLETER_SUPPORTED ,
|
964 |
|
|
DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED => DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ,
|
965 |
|
|
DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED => DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ,
|
966 |
|
|
DEV_CAP2_LTR_MECHANISM_SUPPORTED => DEV_CAP2_LTR_MECHANISM_SUPPORTED ,
|
967 |
|
|
DEV_CAP2_MAX_ENDEND_TLP_PREFIXES => DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ,
|
968 |
|
|
DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING => DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ,
|
969 |
|
|
DEV_CAP2_TPH_COMPLETER_SUPPORTED => DEV_CAP2_TPH_COMPLETER_SUPPORTED ,
|
970 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ,
|
971 |
|
|
DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE => DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ,
|
972 |
|
|
DEV_CAP_ENDPOINT_L0S_LATENCY => DEV_CAP_ENDPOINT_L0S_LATENCY ,
|
973 |
|
|
DEV_CAP_ENDPOINT_L1_LATENCY => DEV_CAP_ENDPOINT_L1_LATENCY ,
|
974 |
|
|
DEV_CAP_EXT_TAG_SUPPORTED => DEV_CAP_EXT_TAG_SUPPORTED ,
|
975 |
|
|
DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE => DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ,
|
976 |
|
|
DEV_CAP_MAX_PAYLOAD_SUPPORTED => DEV_CAP_MAX_PAYLOAD_SUPPORTED ,
|
977 |
|
|
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ,
|
978 |
|
|
DEV_CAP_ROLE_BASED_ERROR => DEV_CAP_ROLE_BASED_ERROR ,
|
979 |
|
|
DEV_CAP_RSVD_14_12 => DEV_CAP_RSVD_14_12 ,
|
980 |
|
|
DEV_CAP_RSVD_17_16 => DEV_CAP_RSVD_17_16 ,
|
981 |
|
|
DEV_CAP_RSVD_31_29 => DEV_CAP_RSVD_31_29 ,
|
982 |
|
|
DEV_CONTROL_AUX_POWER_SUPPORTED => DEV_CONTROL_AUX_POWER_SUPPORTED ,
|
983 |
|
|
DEV_CONTROL_EXT_TAG_DEFAULT => DEV_CONTROL_EXT_TAG_DEFAULT ,
|
984 |
|
|
DISABLE_ASPM_L1_TIMER => DISABLE_ASPM_L1_TIMER ,
|
985 |
|
|
DISABLE_BAR_FILTERING => DISABLE_BAR_FILTERING ,
|
986 |
|
|
DISABLE_ERR_MSG => DISABLE_ERR_MSG ,
|
987 |
|
|
DISABLE_ID_CHECK => DISABLE_ID_CHECK ,
|
988 |
|
|
DISABLE_LANE_REVERSAL => DISABLE_LANE_REVERSAL ,
|
989 |
|
|
DISABLE_LOCKED_FILTER => DISABLE_LOCKED_FILTER ,
|
990 |
|
|
DISABLE_PPM_FILTER => DISABLE_PPM_FILTER ,
|
991 |
|
|
DISABLE_RX_POISONED_RESP => DISABLE_RX_POISONED_RESP ,
|
992 |
|
|
DISABLE_RX_TC_FILTER => DISABLE_RX_TC_FILTER ,
|
993 |
|
|
DISABLE_SCRAMBLING => DISABLE_SCRAMBLING ,
|
994 |
|
|
DNSTREAM_LINK_NUM => DNSTREAM_LINK_NUM ,
|
995 |
|
|
DSN_BASE_PTR => DSN_BASE_PTR ,
|
996 |
|
|
DSN_CAP_ID => DSN_CAP_ID ,
|
997 |
|
|
DSN_CAP_NEXTPTR => DSN_CAP_NEXTPTR ,
|
998 |
|
|
DSN_CAP_ON => DSN_CAP_ON ,
|
999 |
|
|
DSN_CAP_VERSION => DSN_CAP_VERSION ,
|
1000 |
|
|
ENABLE_MSG_ROUTE => ENABLE_MSG_ROUTE ,
|
1001 |
|
|
ENABLE_RX_TD_ECRC_TRIM => ENABLE_RX_TD_ECRC_TRIM ,
|
1002 |
|
|
ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED => ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ,
|
1003 |
|
|
ENTER_RVRY_EI_L0 => ENTER_RVRY_EI_L0 ,
|
1004 |
|
|
EXIT_LOOPBACK_ON_EI => EXIT_LOOPBACK_ON_EI ,
|
1005 |
|
|
EXPANSION_ROM => EXPANSION_ROM ,
|
1006 |
|
|
EXT_CFG_CAP_PTR => EXT_CFG_CAP_PTR ,
|
1007 |
|
|
EXT_CFG_XP_CAP_PTR => EXT_CFG_XP_CAP_PTR ,
|
1008 |
|
|
HEADER_TYPE => HEADER_TYPE ,
|
1009 |
|
|
INFER_EI => INFER_EI ,
|
1010 |
|
|
INTERRUPT_PIN => INTERRUPT_PIN ,
|
1011 |
|
|
INTERRUPT_STAT_AUTO => INTERRUPT_STAT_AUTO ,
|
1012 |
|
|
IS_SWITCH => IS_SWITCH ,
|
1013 |
|
|
LAST_CONFIG_DWORD => LAST_CONFIG_DWORD ,
|
1014 |
|
|
LINK_CAP_ASPM_OPTIONALITY => LINK_CAP_ASPM_OPTIONALITY ,
|
1015 |
|
|
LINK_CAP_ASPM_SUPPORT => LINK_CAP_ASPM_SUPPORT ,
|
1016 |
|
|
LINK_CAP_CLOCK_POWER_MANAGEMENT => LINK_CAP_CLOCK_POWER_MANAGEMENT ,
|
1017 |
|
|
LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP => LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ,
|
1018 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ,
|
1019 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ,
|
1020 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_GEN1 => LINK_CAP_L0S_EXIT_LATENCY_GEN1 ,
|
1021 |
|
|
LINK_CAP_L0S_EXIT_LATENCY_GEN2 => LINK_CAP_L0S_EXIT_LATENCY_GEN2 ,
|
1022 |
|
|
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ,
|
1023 |
|
|
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 => LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ,
|
1024 |
|
|
LINK_CAP_L1_EXIT_LATENCY_GEN1 => LINK_CAP_L1_EXIT_LATENCY_GEN1 ,
|
1025 |
|
|
LINK_CAP_L1_EXIT_LATENCY_GEN2 => LINK_CAP_L1_EXIT_LATENCY_GEN2 ,
|
1026 |
|
|
LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP => LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ,
|
1027 |
|
|
LINK_CAP_MAX_LINK_SPEED => LINK_CAP_MAX_LINK_SPEED ,
|
1028 |
|
|
LINK_CAP_MAX_LINK_WIDTH => LINK_CAP_MAX_LINK_WIDTH ,
|
1029 |
|
|
LINK_CAP_RSVD_23 => LINK_CAP_RSVD_23 ,
|
1030 |
|
|
LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE => LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ,
|
1031 |
|
|
LINK_CONTROL_RCB => LINK_CONTROL_RCB ,
|
1032 |
|
|
LINK_CTRL2_DEEMPHASIS => LINK_CTRL2_DEEMPHASIS ,
|
1033 |
|
|
LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE => LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ,
|
1034 |
|
|
LINK_CTRL2_TARGET_LINK_SPEED => LINK_CTRL2_TARGET_LINK_SPEED ,
|
1035 |
|
|
LINK_STATUS_SLOT_CLOCK_CONFIG => LINK_STATUS_SLOT_CLOCK_CONFIG ,
|
1036 |
|
|
LL_ACK_TIMEOUT => LL_ACK_TIMEOUT ,
|
1037 |
|
|
LL_ACK_TIMEOUT_EN => LL_ACK_TIMEOUT_EN ,
|
1038 |
|
|
LL_ACK_TIMEOUT_FUNC => LL_ACK_TIMEOUT_FUNC ,
|
1039 |
|
|
LL_REPLAY_TIMEOUT => LL_REPLAY_TIMEOUT ,
|
1040 |
|
|
LL_REPLAY_TIMEOUT_EN => LL_REPLAY_TIMEOUT_EN ,
|
1041 |
|
|
LL_REPLAY_TIMEOUT_FUNC => LL_REPLAY_TIMEOUT_FUNC ,
|
1042 |
|
|
LTSSM_MAX_LINK_WIDTH => LTSSM_MAX_LINK_WIDTH ,
|
1043 |
|
|
MPS_FORCE => MPS_FORCE ,
|
1044 |
|
|
MSIX_BASE_PTR => MSIX_BASE_PTR ,
|
1045 |
|
|
MSIX_CAP_ID => MSIX_CAP_ID ,
|
1046 |
|
|
MSIX_CAP_NEXTPTR => MSIX_CAP_NEXTPTR ,
|
1047 |
|
|
MSIX_CAP_ON => MSIX_CAP_ON ,
|
1048 |
|
|
MSIX_CAP_PBA_BIR => MSIX_CAP_PBA_BIR ,
|
1049 |
|
|
MSIX_CAP_PBA_OFFSET => MSIX_CAP_PBA_OFFSET ,
|
1050 |
|
|
MSIX_CAP_TABLE_BIR => MSIX_CAP_TABLE_BIR ,
|
1051 |
|
|
MSIX_CAP_TABLE_OFFSET => MSIX_CAP_TABLE_OFFSET ,
|
1052 |
|
|
MSIX_CAP_TABLE_SIZE => MSIX_CAP_TABLE_SIZE ,
|
1053 |
|
|
MSI_BASE_PTR => MSI_BASE_PTR ,
|
1054 |
|
|
MSI_CAP_64_BIT_ADDR_CAPABLE => MSI_CAP_64_BIT_ADDR_CAPABLE ,
|
1055 |
|
|
MSI_CAP_ID => MSI_CAP_ID ,
|
1056 |
|
|
MSI_CAP_MULTIMSGCAP => MSI_CAP_MULTIMSGCAP ,
|
1057 |
|
|
MSI_CAP_MULTIMSG_EXTENSION => MSI_CAP_MULTIMSG_EXTENSION ,
|
1058 |
|
|
MSI_CAP_NEXTPTR => MSI_CAP_NEXTPTR ,
|
1059 |
|
|
MSI_CAP_ON => MSI_CAP_ON ,
|
1060 |
|
|
MSI_CAP_PER_VECTOR_MASKING_CAPABLE => MSI_CAP_PER_VECTOR_MASKING_CAPABLE ,
|
1061 |
|
|
N_FTS_COMCLK_GEN1 => N_FTS_COMCLK_GEN1 ,
|
1062 |
|
|
N_FTS_COMCLK_GEN2 => N_FTS_COMCLK_GEN2 ,
|
1063 |
|
|
N_FTS_GEN1 => N_FTS_GEN1 ,
|
1064 |
|
|
N_FTS_GEN2 => N_FTS_GEN2 ,
|
1065 |
|
|
PCIE_BASE_PTR => PCIE_BASE_PTR ,
|
1066 |
|
|
PCIE_CAP_CAPABILITY_ID => PCIE_CAP_CAPABILITY_ID ,
|
1067 |
|
|
PCIE_CAP_CAPABILITY_VERSION => PCIE_CAP_CAPABILITY_VERSION ,
|
1068 |
|
|
PCIE_CAP_DEVICE_PORT_TYPE => PCIE_CAP_DEVICE_PORT_TYPE ,
|
1069 |
|
|
PCIE_CAP_NEXTPTR => PCIE_CAP_NEXTPTR ,
|
1070 |
|
|
PCIE_CAP_ON => PCIE_CAP_ON ,
|
1071 |
|
|
PCIE_CAP_RSVD_15_14 => PCIE_CAP_RSVD_15_14 ,
|
1072 |
|
|
PCIE_CAP_SLOT_IMPLEMENTED => PCIE_CAP_SLOT_IMPLEMENTED ,
|
1073 |
|
|
PCIE_REVISION => PCIE_REVISION ,
|
1074 |
|
|
PL_AUTO_CONFIG => PL_AUTO_CONFIG ,
|
1075 |
|
|
PL_FAST_TRAIN => PL_FAST_TRAIN ,
|
1076 |
|
|
PM_ASPML0S_TIMEOUT => PM_ASPML0S_TIMEOUT ,
|
1077 |
|
|
PM_ASPML0S_TIMEOUT_EN => PM_ASPML0S_TIMEOUT_EN ,
|
1078 |
|
|
PM_ASPML0S_TIMEOUT_FUNC => PM_ASPML0S_TIMEOUT_FUNC ,
|
1079 |
|
|
PM_ASPM_FASTEXIT => PM_ASPM_FASTEXIT ,
|
1080 |
|
|
PM_BASE_PTR => PM_BASE_PTR ,
|
1081 |
|
|
PM_CAP_AUXCURRENT => PM_CAP_AUXCURRENT ,
|
1082 |
|
|
PM_CAP_D1SUPPORT => PM_CAP_D1SUPPORT ,
|
1083 |
|
|
PM_CAP_D2SUPPORT => PM_CAP_D2SUPPORT ,
|
1084 |
|
|
PM_CAP_DSI => PM_CAP_DSI ,
|
1085 |
|
|
PM_CAP_ID => PM_CAP_ID ,
|
1086 |
|
|
PM_CAP_NEXTPTR => PM_CAP_NEXTPTR ,
|
1087 |
|
|
PM_CAP_ON => PM_CAP_ON ,
|
1088 |
|
|
PM_CAP_PMESUPPORT => PM_CAP_PMESUPPORT ,
|
1089 |
|
|
PM_CAP_PME_CLOCK => PM_CAP_PME_CLOCK ,
|
1090 |
|
|
PM_CAP_RSVD_04 => PM_CAP_RSVD_04 ,
|
1091 |
|
|
PM_CAP_VERSION => PM_CAP_VERSION ,
|
1092 |
|
|
PM_CSR_B2B3 => PM_CSR_B2B3 ,
|
1093 |
|
|
PM_CSR_BPCCEN => PM_CSR_BPCCEN ,
|
1094 |
|
|
PM_CSR_NOSOFTRST => PM_CSR_NOSOFTRST ,
|
1095 |
|
|
PM_DATA0 => PM_DATA0 ,
|
1096 |
|
|
PM_DATA1 => PM_DATA1 ,
|
1097 |
|
|
PM_DATA2 => PM_DATA2 ,
|
1098 |
|
|
PM_DATA3 => PM_DATA3 ,
|
1099 |
|
|
PM_DATA4 => PM_DATA4 ,
|
1100 |
|
|
PM_DATA5 => PM_DATA5 ,
|
1101 |
|
|
PM_DATA6 => PM_DATA6 ,
|
1102 |
|
|
PM_DATA7 => PM_DATA7 ,
|
1103 |
|
|
PM_DATA_SCALE0 => PM_DATA_SCALE0 ,
|
1104 |
|
|
PM_DATA_SCALE1 => PM_DATA_SCALE1 ,
|
1105 |
|
|
PM_DATA_SCALE2 => PM_DATA_SCALE2 ,
|
1106 |
|
|
PM_DATA_SCALE3 => PM_DATA_SCALE3 ,
|
1107 |
|
|
PM_DATA_SCALE4 => PM_DATA_SCALE4 ,
|
1108 |
|
|
PM_DATA_SCALE5 => PM_DATA_SCALE5 ,
|
1109 |
|
|
PM_DATA_SCALE6 => PM_DATA_SCALE6 ,
|
1110 |
|
|
PM_DATA_SCALE7 => PM_DATA_SCALE7 ,
|
1111 |
|
|
PM_MF => PM_MF ,
|
1112 |
|
|
RBAR_BASE_PTR => RBAR_BASE_PTR ,
|
1113 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR0 => RBAR_CAP_CONTROL_ENCODEDBAR0 ,
|
1114 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR1 => RBAR_CAP_CONTROL_ENCODEDBAR1 ,
|
1115 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR2 => RBAR_CAP_CONTROL_ENCODEDBAR2 ,
|
1116 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR3 => RBAR_CAP_CONTROL_ENCODEDBAR3 ,
|
1117 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR4 => RBAR_CAP_CONTROL_ENCODEDBAR4 ,
|
1118 |
|
|
RBAR_CAP_CONTROL_ENCODEDBAR5 => RBAR_CAP_CONTROL_ENCODEDBAR5 ,
|
1119 |
|
|
RBAR_CAP_ID => RBAR_CAP_ID ,
|
1120 |
|
|
RBAR_CAP_INDEX0 => RBAR_CAP_INDEX0 ,
|
1121 |
|
|
RBAR_CAP_INDEX1 => RBAR_CAP_INDEX1 ,
|
1122 |
|
|
RBAR_CAP_INDEX2 => RBAR_CAP_INDEX2 ,
|
1123 |
|
|
RBAR_CAP_INDEX3 => RBAR_CAP_INDEX3 ,
|
1124 |
|
|
RBAR_CAP_INDEX4 => RBAR_CAP_INDEX4 ,
|
1125 |
|
|
RBAR_CAP_INDEX5 => RBAR_CAP_INDEX5 ,
|
1126 |
|
|
RBAR_CAP_NEXTPTR => RBAR_CAP_NEXTPTR ,
|
1127 |
|
|
RBAR_CAP_ON => RBAR_CAP_ON ,
|
1128 |
|
|
RBAR_CAP_SUP0 => RBAR_CAP_SUP0 ,
|
1129 |
|
|
RBAR_CAP_SUP1 => RBAR_CAP_SUP1 ,
|
1130 |
|
|
RBAR_CAP_SUP2 => RBAR_CAP_SUP2 ,
|
1131 |
|
|
RBAR_CAP_SUP3 => RBAR_CAP_SUP3 ,
|
1132 |
|
|
RBAR_CAP_SUP4 => RBAR_CAP_SUP4 ,
|
1133 |
|
|
RBAR_CAP_SUP5 => RBAR_CAP_SUP5 ,
|
1134 |
|
|
RBAR_CAP_VERSION => RBAR_CAP_VERSION ,
|
1135 |
|
|
RBAR_NUM => RBAR_NUM ,
|
1136 |
|
|
RECRC_CHK => RECRC_CHK ,
|
1137 |
|
|
RECRC_CHK_TRIM => RECRC_CHK_TRIM ,
|
1138 |
|
|
ROOT_CAP_CRS_SW_VISIBILITY => ROOT_CAP_CRS_SW_VISIBILITY ,
|
1139 |
|
|
RP_AUTO_SPD => RP_AUTO_SPD ,
|
1140 |
|
|
RP_AUTO_SPD_LOOPCNT => RP_AUTO_SPD_LOOPCNT ,
|
1141 |
|
|
SELECT_DLL_IF => SELECT_DLL_IF ,
|
1142 |
|
|
SIM_VERSION => SIM_VERSION ,--
|
1143 |
|
|
SLOT_CAP_ATT_BUTTON_PRESENT => SLOT_CAP_ATT_BUTTON_PRESENT ,
|
1144 |
|
|
SLOT_CAP_ATT_INDICATOR_PRESENT => SLOT_CAP_ATT_INDICATOR_PRESENT ,
|
1145 |
|
|
SLOT_CAP_ELEC_INTERLOCK_PRESENT => SLOT_CAP_ELEC_INTERLOCK_PRESENT ,
|
1146 |
|
|
SLOT_CAP_HOTPLUG_CAPABLE => SLOT_CAP_HOTPLUG_CAPABLE ,
|
1147 |
|
|
SLOT_CAP_HOTPLUG_SURPRISE => SLOT_CAP_HOTPLUG_SURPRISE ,
|
1148 |
|
|
SLOT_CAP_MRL_SENSOR_PRESENT => SLOT_CAP_MRL_SENSOR_PRESENT ,
|
1149 |
|
|
SLOT_CAP_NO_CMD_COMPLETED_SUPPORT => SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ,
|
1150 |
|
|
SLOT_CAP_PHYSICAL_SLOT_NUM => SLOT_CAP_PHYSICAL_SLOT_NUM ,
|
1151 |
|
|
SLOT_CAP_POWER_CONTROLLER_PRESENT => SLOT_CAP_POWER_CONTROLLER_PRESENT ,
|
1152 |
|
|
SLOT_CAP_POWER_INDICATOR_PRESENT => SLOT_CAP_POWER_INDICATOR_PRESENT ,
|
1153 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_SCALE => SLOT_CAP_SLOT_POWER_LIMIT_SCALE ,
|
1154 |
|
|
SLOT_CAP_SLOT_POWER_LIMIT_VALUE => SLOT_CAP_SLOT_POWER_LIMIT_VALUE ,
|
1155 |
|
|
SPARE_BIT0 => SPARE_BIT0 ,
|
1156 |
|
|
SPARE_BIT1 => SPARE_BIT1 ,
|
1157 |
|
|
SPARE_BIT2 => SPARE_BIT2 ,
|
1158 |
|
|
SPARE_BIT3 => SPARE_BIT3 ,
|
1159 |
|
|
SPARE_BIT4 => SPARE_BIT4 ,
|
1160 |
|
|
SPARE_BIT5 => SPARE_BIT5 ,
|
1161 |
|
|
SPARE_BIT6 => SPARE_BIT6 ,
|
1162 |
|
|
SPARE_BIT7 => SPARE_BIT7 ,
|
1163 |
|
|
SPARE_BIT8 => SPARE_BIT8 ,
|
1164 |
|
|
SPARE_BYTE0 => SPARE_BYTE0 ,
|
1165 |
|
|
SPARE_BYTE1 => SPARE_BYTE1 ,
|
1166 |
|
|
SPARE_BYTE2 => SPARE_BYTE2 ,
|
1167 |
|
|
SPARE_BYTE3 => SPARE_BYTE3 ,
|
1168 |
|
|
SPARE_WORD0 => SPARE_WORD0 ,
|
1169 |
|
|
SPARE_WORD1 => SPARE_WORD1 ,
|
1170 |
|
|
SPARE_WORD2 => SPARE_WORD2 ,
|
1171 |
|
|
SPARE_WORD3 => SPARE_WORD3 ,
|
1172 |
|
|
SSL_MESSAGE_AUTO => SSL_MESSAGE_AUTO ,
|
1173 |
|
|
TECRC_EP_INV => TECRC_EP_INV ,
|
1174 |
|
|
TL_RBYPASS => TL_RBYPASS ,
|
1175 |
|
|
TL_RX_RAM_RADDR_LATENCY => TL_RX_RAM_RADDR_LATENCY ,
|
1176 |
|
|
TL_RX_RAM_RDATA_LATENCY => TL_RX_RAM_RDATA_LATENCY ,
|
1177 |
|
|
TL_RX_RAM_WRITE_LATENCY => TL_RX_RAM_WRITE_LATENCY ,
|
1178 |
|
|
TL_TFC_DISABLE => TL_TFC_DISABLE ,
|
1179 |
|
|
TL_TX_CHECKS_DISABLE => TL_TX_CHECKS_DISABLE ,
|
1180 |
|
|
TL_TX_RAM_RADDR_LATENCY => TL_TX_RAM_RADDR_LATENCY ,
|
1181 |
|
|
TL_TX_RAM_RDATA_LATENCY => TL_TX_RAM_RDATA_LATENCY ,
|
1182 |
|
|
TL_TX_RAM_WRITE_LATENCY => TL_TX_RAM_WRITE_LATENCY ,
|
1183 |
|
|
TRN_DW => TRN_DW ,
|
1184 |
|
|
TRN_NP_FC => TRN_NP_FC ,
|
1185 |
|
|
UPCONFIG_CAPABLE => UPCONFIG_CAPABLE ,
|
1186 |
|
|
UPSTREAM_FACING => UPSTREAM_FACING ,
|
1187 |
|
|
UR_ATOMIC => UR_ATOMIC ,
|
1188 |
|
|
UR_CFG1 => UR_CFG1 ,
|
1189 |
|
|
UR_INV_REQ => UR_INV_REQ ,
|
1190 |
|
|
UR_PRS_RESPONSE => UR_PRS_RESPONSE ,
|
1191 |
|
|
USER_CLK2_DIV2 => USER_CLK2_DIV2 ,
|
1192 |
|
|
USER_CLK_FREQ => USER_CLK_FREQ ,
|
1193 |
|
|
USE_RID_PINS => USE_RID_PINS ,
|
1194 |
|
|
VC0_CPL_INFINITE => VC0_CPL_INFINITE ,
|
1195 |
|
|
VC0_RX_RAM_LIMIT => VC0_RX_RAM_LIMIT ,
|
1196 |
|
|
VC0_TOTAL_CREDITS_CD => VC0_TOTAL_CREDITS_CD ,
|
1197 |
|
|
VC0_TOTAL_CREDITS_CH => VC0_TOTAL_CREDITS_CH ,
|
1198 |
|
|
VC0_TOTAL_CREDITS_NPD => VC0_TOTAL_CREDITS_NPD ,
|
1199 |
|
|
VC0_TOTAL_CREDITS_NPH => VC0_TOTAL_CREDITS_NPH ,
|
1200 |
|
|
VC0_TOTAL_CREDITS_PD => VC0_TOTAL_CREDITS_PD ,
|
1201 |
|
|
VC0_TOTAL_CREDITS_PH => VC0_TOTAL_CREDITS_PH ,
|
1202 |
|
|
VC0_TX_LASTPACKET => VC0_TX_LASTPACKET ,
|
1203 |
|
|
VC_BASE_PTR => VC_BASE_PTR ,
|
1204 |
|
|
VC_CAP_ID => VC_CAP_ID ,
|
1205 |
|
|
VC_CAP_NEXTPTR => VC_CAP_NEXTPTR ,
|
1206 |
|
|
VC_CAP_ON => VC_CAP_ON ,
|
1207 |
|
|
VC_CAP_REJECT_SNOOP_TRANSACTIONS => VC_CAP_REJECT_SNOOP_TRANSACTIONS ,
|
1208 |
|
|
VC_CAP_VERSION => VC_CAP_VERSION ,
|
1209 |
|
|
VSEC_BASE_PTR => VSEC_BASE_PTR ,
|
1210 |
|
|
VSEC_CAP_HDR_ID => VSEC_CAP_HDR_ID ,
|
1211 |
|
|
VSEC_CAP_HDR_LENGTH => VSEC_CAP_HDR_LENGTH ,--
|
1212 |
|
|
VSEC_CAP_HDR_REVISION => VSEC_CAP_HDR_REVISION ,
|
1213 |
|
|
VSEC_CAP_ID => VSEC_CAP_ID ,
|
1214 |
|
|
VSEC_CAP_IS_LINK_VISIBLE => VSEC_CAP_IS_LINK_VISIBLE ,
|
1215 |
|
|
VSEC_CAP_NEXTPTR => VSEC_CAP_NEXTPTR ,
|
1216 |
|
|
VSEC_CAP_ON => VSEC_CAP_ON ,
|
1217 |
|
|
VSEC_CAP_VERSION => VSEC_CAP_VERSION
|
1218 |
|
|
)
|
1219 |
|
|
port map (
|
1220 |
|
|
CFGAERECRCCHECKEN => cfg_aer_ecrc_check_en,
|
1221 |
|
|
CFGAERECRCGENEN => cfg_aer_ecrc_gen_en,
|
1222 |
|
|
CFGAERROOTERRCORRERRRECEIVED => cfg_aer_rooterr_corr_err_received,
|
1223 |
|
|
CFGAERROOTERRCORRERRREPORTINGEN => cfg_aer_rooterr_corr_err_reporting_en,
|
1224 |
|
|
CFGAERROOTERRFATALERRRECEIVED => cfg_aer_rooterr_fatal_err_received,
|
1225 |
|
|
CFGAERROOTERRFATALERRREPORTINGEN => cfg_aer_rooterr_fatal_err_reporting_en,
|
1226 |
|
|
CFGAERROOTERRNONFATALERRRECEIVED => cfg_aer_rooterr_non_fatal_err_received,
|
1227 |
|
|
CFGAERROOTERRNONFATALERRREPORTINGEN => cfg_aer_rooterr_non_fatal_err_reporting_en,
|
1228 |
|
|
CFGBRIDGESERREN => cfg_bridge_serr_en,
|
1229 |
|
|
CFGCOMMANDBUSMASTERENABLE => cfg_command_bus_master_enable,
|
1230 |
|
|
CFGCOMMANDINTERRUPTDISABLE => cfg_command_interrupt_disable,
|
1231 |
|
|
CFGCOMMANDIOENABLE => cfg_command_io_enable,
|
1232 |
|
|
CFGCOMMANDMEMENABLE => cfg_command_mem_enable,
|
1233 |
|
|
CFGCOMMANDSERREN => cfg_command_serr_en,
|
1234 |
|
|
CFGDEVCONTROL2ARIFORWARDEN => cfg_dev_control2_ari_forward_en,
|
1235 |
|
|
CFGDEVCONTROL2ATOMICEGRESSBLOCK => cfg_dev_control2_atomic_egress_block,
|
1236 |
|
|
CFGDEVCONTROL2ATOMICREQUESTEREN => cfg_dev_control2_atomic_requester_en,
|
1237 |
|
|
CFGDEVCONTROL2CPLTIMEOUTDIS => cfg_dev_control2_cpl_timeout_dis,
|
1238 |
|
|
CFGDEVCONTROL2CPLTIMEOUTVAL => cfg_dev_control2_cpl_timeout_val,
|
1239 |
|
|
CFGDEVCONTROL2IDOCPLEN => cfg_dev_control2_ido_cpl_en,
|
1240 |
|
|
CFGDEVCONTROL2IDOREQEN => cfg_dev_control2_ido_req_en,
|
1241 |
|
|
CFGDEVCONTROL2LTREN => cfg_dev_control2_ltr_en,
|
1242 |
|
|
CFGDEVCONTROL2TLPPREFIXBLOCK => cfg_dev_control2_tlp_prefix_block,
|
1243 |
|
|
CFGDEVCONTROLAUXPOWEREN => cfg_dev_control_aux_power_en,
|
1244 |
|
|
CFGDEVCONTROLCORRERRREPORTINGEN => cfg_dev_control_corr_err_reporting_en,
|
1245 |
|
|
CFGDEVCONTROLENABLERO => cfg_dev_control_enable_ro,
|
1246 |
|
|
CFGDEVCONTROLEXTTAGEN => cfg_dev_control_ext_tag_en,
|
1247 |
|
|
CFGDEVCONTROLFATALERRREPORTINGEN => cfg_dev_control_fatal_err_reporting_en,
|
1248 |
|
|
CFGDEVCONTROLMAXPAYLOAD => cfg_dev_control_max_payload,
|
1249 |
|
|
CFGDEVCONTROLMAXREADREQ => cfg_dev_control_max_read_req,
|
1250 |
|
|
CFGDEVCONTROLNONFATALREPORTINGEN => cfg_dev_control_non_fatal_reporting_en,
|
1251 |
|
|
CFGDEVCONTROLNOSNOOPEN => cfg_dev_control_no_snoop_en,
|
1252 |
|
|
CFGDEVCONTROLPHANTOMEN => cfg_dev_control_phantom_en,
|
1253 |
|
|
CFGDEVCONTROLURERRREPORTINGEN => cfg_dev_control_ur_err_reporting_en,
|
1254 |
|
|
CFGDEVSTATUSCORRERRDETECTED => cfg_dev_status_corr_err_detected,
|
1255 |
|
|
CFGDEVSTATUSFATALERRDETECTED => cfg_dev_status_fatal_err_detected,
|
1256 |
|
|
CFGDEVSTATUSNONFATALERRDETECTED => cfg_dev_status_non_fatal_err_detected,
|
1257 |
|
|
CFGDEVSTATUSURDETECTED => cfg_dev_status_ur_detected,
|
1258 |
|
|
CFGERRAERHEADERLOGSETN => cfg_err_aer_headerlog_set_n,
|
1259 |
|
|
CFGERRCPLRDYN => cfg_err_cpl_rdy_n,
|
1260 |
|
|
CFGINTERRUPTDO => cfg_interrupt_do,
|
1261 |
|
|
CFGINTERRUPTMMENABLE => cfg_interrupt_mmenable,
|
1262 |
|
|
CFGINTERRUPTMSIENABLE => cfg_interrupt_msienable,
|
1263 |
|
|
CFGINTERRUPTMSIXENABLE => cfg_interrupt_msixenable,
|
1264 |
|
|
CFGINTERRUPTMSIXFM => cfg_interrupt_msixfm,
|
1265 |
|
|
CFGINTERRUPTRDYN => cfg_interrupt_rdy_n,
|
1266 |
|
|
CFGLINKCONTROLASPMCONTROL => cfg_link_control_aspm_control,
|
1267 |
|
|
CFGLINKCONTROLAUTOBANDWIDTHINTEN => cfg_link_control_auto_bandwidth_int_en,
|
1268 |
|
|
CFGLINKCONTROLBANDWIDTHINTEN => cfg_link_control_bandwidth_int_en,
|
1269 |
|
|
CFGLINKCONTROLCLOCKPMEN => cfg_link_control_clock_pm_en,
|
1270 |
|
|
CFGLINKCONTROLCOMMONCLOCK => cfg_link_control_common_clock,
|
1271 |
|
|
CFGLINKCONTROLEXTENDEDSYNC => cfg_link_control_extended_sync,
|
1272 |
|
|
CFGLINKCONTROLHWAUTOWIDTHDIS => cfg_link_control_hw_auto_width_dis,
|
1273 |
|
|
CFGLINKCONTROLLINKDISABLE => cfg_link_control_link_disable,
|
1274 |
|
|
CFGLINKCONTROLRCB => cfg_link_control_rcb,
|
1275 |
|
|
CFGLINKCONTROLRETRAINLINK => cfg_link_control_retrain_link,
|
1276 |
|
|
CFGLINKSTATUSAUTOBANDWIDTHSTATUS => cfg_link_status_auto_bandwidth_status,
|
1277 |
|
|
CFGLINKSTATUSBANDWIDTHSTATUS => cfg_link_status_bandwidth_status,
|
1278 |
|
|
CFGLINKSTATUSCURRENTSPEED => cfg_link_status_current_speed,
|
1279 |
|
|
CFGLINKSTATUSDLLACTIVE => cfg_link_status_dll_active,
|
1280 |
|
|
CFGLINKSTATUSLINKTRAINING => cfg_link_status_link_training,
|
1281 |
|
|
CFGLINKSTATUSNEGOTIATEDWIDTH => cfg_link_status_negotiated_width,
|
1282 |
|
|
CFGMGMTDO => cfg_mgmt_do,
|
1283 |
|
|
CFGMGMTRDWRDONEN => cfg_mgmt_rd_wr_done_n,
|
1284 |
|
|
CFGMSGDATA => cfg_msg_data,
|
1285 |
|
|
CFGMSGRECEIVED => cfg_msg_received,
|
1286 |
|
|
CFGMSGRECEIVEDASSERTINTA => cfg_msg_received_assert_int_a,
|
1287 |
|
|
CFGMSGRECEIVEDASSERTINTB => cfg_msg_received_assert_int_b,
|
1288 |
|
|
CFGMSGRECEIVEDASSERTINTC => cfg_msg_received_assert_int_c,
|
1289 |
|
|
CFGMSGRECEIVEDASSERTINTD => cfg_msg_received_assert_int_d,
|
1290 |
|
|
CFGMSGRECEIVEDDEASSERTINTA => cfg_msg_received_deassert_int_a,
|
1291 |
|
|
CFGMSGRECEIVEDDEASSERTINTB => cfg_msg_received_deassert_int_b,
|
1292 |
|
|
CFGMSGRECEIVEDDEASSERTINTC => cfg_msg_received_deassert_int_c,
|
1293 |
|
|
CFGMSGRECEIVEDDEASSERTINTD => cfg_msg_received_deassert_int_d,
|
1294 |
|
|
CFGMSGRECEIVEDERRCOR => cfg_msg_received_err_cor,
|
1295 |
|
|
CFGMSGRECEIVEDERRFATAL => cfg_msg_received_err_fatal,
|
1296 |
|
|
CFGMSGRECEIVEDERRNONFATAL => cfg_msg_received_err_non_fatal,
|
1297 |
|
|
CFGMSGRECEIVEDPMASNAK => cfg_msg_received_pm_as_nak,
|
1298 |
|
|
CFGMSGRECEIVEDPMETO => cfg_msg_received_pme_to,
|
1299 |
|
|
CFGMSGRECEIVEDPMETOACK => cfg_msg_received_pme_to_ack,
|
1300 |
|
|
CFGMSGRECEIVEDPMPME => cfg_msg_received_pm_pme,
|
1301 |
|
|
CFGMSGRECEIVEDSETSLOTPOWERLIMIT => cfg_msg_received_setslotpowerlimit,
|
1302 |
|
|
CFGMSGRECEIVEDUNLOCK => cfg_msg_received_unlock,
|
1303 |
|
|
CFGPCIELINKSTATE => cfg_pcie_link_state,
|
1304 |
|
|
CFGPMCSRPMEEN => cfg_pmcsr_pme_en,
|
1305 |
|
|
CFGPMCSRPMESTATUS => cfg_pmcsr_pme_status,
|
1306 |
|
|
CFGPMCSRPOWERSTATE => cfg_pmcsr_powerstate,
|
1307 |
|
|
CFGPMRCVASREQL1N => cfg_pm_rcv_as_req_l1_n,
|
1308 |
|
|
CFGPMRCVENTERL1N => cfg_pm_rcv_enter_l1_n,
|
1309 |
|
|
CFGPMRCVENTERL23N => cfg_pm_rcv_enter_l23_n,
|
1310 |
|
|
CFGPMRCVREQACKN => cfg_pm_rcv_req_ack_n,
|
1311 |
|
|
CFGROOTCONTROLPMEINTEN => cfg_root_control_pme_int_en,
|
1312 |
|
|
CFGROOTCONTROLSYSERRCORRERREN => cfg_root_control_syserr_corr_err_en,
|
1313 |
|
|
CFGROOTCONTROLSYSERRFATALERREN => cfg_root_control_syserr_fatal_err_en,
|
1314 |
|
|
CFGROOTCONTROLSYSERRNONFATALERREN => cfg_root_control_syserr_non_fatal_err_en,
|
1315 |
|
|
CFGSLOTCONTROLELECTROMECHILCTLPULSE => cfg_slot_control_electromech_il_ctl_pulse,
|
1316 |
|
|
CFGTRANSACTION => cfg_transaction,
|
1317 |
|
|
CFGTRANSACTIONADDR => cfg_transaction_addr,
|
1318 |
|
|
CFGTRANSACTIONTYPE => cfg_transaction_type,
|
1319 |
|
|
CFGVCTCVCMAP => cfg_vc_tcvc_map,
|
1320 |
|
|
DBGSCLRA => dbg_sclr_a,
|
1321 |
|
|
DBGSCLRB => dbg_sclr_b,
|
1322 |
|
|
DBGSCLRC => dbg_sclr_c,
|
1323 |
|
|
DBGSCLRD => dbg_sclr_d,
|
1324 |
|
|
DBGSCLRE => dbg_sclr_e,
|
1325 |
|
|
DBGSCLRF => dbg_sclr_f,
|
1326 |
|
|
DBGSCLRG => dbg_sclr_g,
|
1327 |
|
|
DBGSCLRH => dbg_sclr_h,
|
1328 |
|
|
DBGSCLRI => dbg_sclr_i,
|
1329 |
|
|
DBGSCLRJ => dbg_sclr_j,
|
1330 |
|
|
DBGSCLRK => dbg_sclr_k,
|
1331 |
|
|
DBGVECA => dbg_vec_a,
|
1332 |
|
|
DBGVECB => dbg_vec_b,
|
1333 |
|
|
DBGVECC => dbg_vec_c,
|
1334 |
|
|
LL2BADDLLPERR => ll2_bad_dllp_err,
|
1335 |
|
|
LL2BADTLPERR => ll2_bad_tlp_err,
|
1336 |
|
|
LL2LINKSTATUS => ll2_link_status,
|
1337 |
|
|
LL2PROTOCOLERR => ll2_protocol_err,
|
1338 |
|
|
LL2RECEIVERERR => ll2_receiver_err,
|
1339 |
|
|
LL2REPLAYROERR => ll2_replay_ro_err,
|
1340 |
|
|
LL2REPLAYTOERR => ll2_replay_to_err,
|
1341 |
|
|
LL2SUSPENDOK => ll2_suspend_ok,
|
1342 |
|
|
LL2TFCINIT1SEQ => ll2_tfc_init1_seq,
|
1343 |
|
|
LL2TFCINIT2SEQ => ll2_tfc_init2_seq,
|
1344 |
|
|
LL2TXIDLE => ll2_tx_idle,
|
1345 |
|
|
LNKCLKEN => lnk_clk_en,
|
1346 |
|
|
MIMRXRADDR => mim_rx_raddr,
|
1347 |
|
|
MIMRXREN => mim_rx_ren,
|
1348 |
|
|
MIMRXWADDR => mim_rx_waddr,
|
1349 |
|
|
MIMRXWDATA => mim_rx_wdata,
|
1350 |
|
|
MIMRXWEN => mim_rx_wen,
|
1351 |
|
|
MIMTXRADDR => mim_tx_raddr,
|
1352 |
|
|
MIMTXREN => mim_tx_ren,
|
1353 |
|
|
MIMTXWADDR => mim_tx_waddr,
|
1354 |
|
|
MIMTXWDATA => mim_tx_wdata,
|
1355 |
|
|
MIMTXWEN => mim_tx_wen,
|
1356 |
|
|
PIPERX0POLARITY => pipe_rx0_polarity,
|
1357 |
|
|
PIPERX1POLARITY => pipe_rx1_polarity,
|
1358 |
|
|
PIPERX2POLARITY => pipe_rx2_polarity,
|
1359 |
|
|
PIPERX3POLARITY => pipe_rx3_polarity,
|
1360 |
|
|
PIPERX4POLARITY => pipe_rx4_polarity,
|
1361 |
|
|
PIPERX5POLARITY => pipe_rx5_polarity,
|
1362 |
|
|
PIPERX6POLARITY => pipe_rx6_polarity,
|
1363 |
|
|
PIPERX7POLARITY => pipe_rx7_polarity,
|
1364 |
|
|
PIPETX0CHARISK => pipe_tx0_char_is_k,
|
1365 |
|
|
PIPETX0COMPLIANCE => pipe_tx0_compliance,
|
1366 |
|
|
PIPETX0DATA => pipe_tx0_data,
|
1367 |
|
|
PIPETX0ELECIDLE => pipe_tx0_elec_idle,
|
1368 |
|
|
PIPETX0POWERDOWN => pipe_tx0_powerdown,
|
1369 |
|
|
PIPETX1CHARISK => pipe_tx1_char_is_k,
|
1370 |
|
|
PIPETX1COMPLIANCE => pipe_tx1_compliance,
|
1371 |
|
|
PIPETX1DATA => pipe_tx1_data,
|
1372 |
|
|
PIPETX1ELECIDLE => pipe_tx1_elec_idle,
|
1373 |
|
|
PIPETX1POWERDOWN => pipe_tx1_powerdown,
|
1374 |
|
|
PIPETX2CHARISK => pipe_tx2_char_is_k,
|
1375 |
|
|
PIPETX2COMPLIANCE => pipe_tx2_compliance,
|
1376 |
|
|
PIPETX2DATA => pipe_tx2_data,
|
1377 |
|
|
PIPETX2ELECIDLE => pipe_tx2_elec_idle,
|
1378 |
|
|
PIPETX2POWERDOWN => pipe_tx2_powerdown,
|
1379 |
|
|
PIPETX3CHARISK => pipe_tx3_char_is_k,
|
1380 |
|
|
PIPETX3COMPLIANCE => pipe_tx3_compliance,
|
1381 |
|
|
PIPETX3DATA => pipe_tx3_data,
|
1382 |
|
|
PIPETX3ELECIDLE => pipe_tx3_elec_idle,
|
1383 |
|
|
PIPETX3POWERDOWN => pipe_tx3_powerdown,
|
1384 |
|
|
PIPETX4CHARISK => pipe_tx4_char_is_k,
|
1385 |
|
|
PIPETX4COMPLIANCE => pipe_tx4_compliance,
|
1386 |
|
|
PIPETX4DATA => pipe_tx4_data,
|
1387 |
|
|
PIPETX4ELECIDLE => pipe_tx4_elec_idle,
|
1388 |
|
|
PIPETX4POWERDOWN => pipe_tx4_powerdown,
|
1389 |
|
|
PIPETX5CHARISK => pipe_tx5_char_is_k,
|
1390 |
|
|
PIPETX5COMPLIANCE => pipe_tx5_compliance,
|
1391 |
|
|
PIPETX5DATA => pipe_tx5_data,
|
1392 |
|
|
PIPETX5ELECIDLE => pipe_tx5_elec_idle,
|
1393 |
|
|
PIPETX5POWERDOWN => pipe_tx5_powerdown,
|
1394 |
|
|
PIPETX6CHARISK => pipe_tx6_char_is_k,
|
1395 |
|
|
PIPETX6COMPLIANCE => pipe_tx6_compliance,
|
1396 |
|
|
PIPETX6DATA => pipe_tx6_data,
|
1397 |
|
|
PIPETX6ELECIDLE => pipe_tx6_elec_idle,
|
1398 |
|
|
PIPETX6POWERDOWN => pipe_tx6_powerdown,
|
1399 |
|
|
PIPETX7CHARISK => pipe_tx7_char_is_k,
|
1400 |
|
|
PIPETX7COMPLIANCE => pipe_tx7_compliance,
|
1401 |
|
|
PIPETX7DATA => pipe_tx7_data,
|
1402 |
|
|
PIPETX7ELECIDLE => pipe_tx7_elec_idle,
|
1403 |
|
|
PIPETX7POWERDOWN => pipe_tx7_powerdown,
|
1404 |
|
|
PIPETXDEEMPH => pipe_tx_deemph,
|
1405 |
|
|
PIPETXMARGIN => pipe_tx_margin,
|
1406 |
|
|
PIPETXRATE => pipe_tx_rate,
|
1407 |
|
|
PIPETXRCVRDET => pipe_tx_rcvr_det,
|
1408 |
|
|
PIPETXRESET => pipe_tx_reset,
|
1409 |
|
|
PL2L0REQ => pl2_l0_req,
|
1410 |
|
|
PL2LINKUP => pl2_link_up,
|
1411 |
|
|
PL2RECEIVERERR => pl2_receiver_err,
|
1412 |
|
|
PL2RECOVERY => pl2_recovery,
|
1413 |
|
|
PL2RXELECIDLE => pl2_rx_elec_idle,
|
1414 |
|
|
PL2RXPMSTATE => pl2_rx_pm_state,
|
1415 |
|
|
PL2SUSPENDOK => pl2_suspend_ok,
|
1416 |
|
|
PLDBGVEC => pl_dbg_vec,
|
1417 |
|
|
PLDIRECTEDCHANGEDONE => pl_directed_change_done,
|
1418 |
|
|
PLINITIALLINKWIDTH => pl_initial_link_width,
|
1419 |
|
|
PLLANEREVERSALMODE => pl_lane_reversal_mode,
|
1420 |
|
|
PLLINKGEN2CAP => pl_link_gen2_cap,
|
1421 |
|
|
PLLINKPARTNERGEN2SUPPORTED => pl_link_partner_gen2_supported,
|
1422 |
|
|
PLLINKUPCFGCAP => pl_link_upcfg_cap,
|
1423 |
|
|
PLLTSSMSTATE => pl_ltssm_state,
|
1424 |
|
|
PLPHYLNKUPN => pl_phy_lnk_up_n,
|
1425 |
|
|
PLRECEIVEDHOTRST => pl_received_hot_rst,
|
1426 |
|
|
PLRXPMSTATE => pl_rx_pm_state,
|
1427 |
|
|
PLSELLNKRATE => pl_sel_lnk_rate,
|
1428 |
|
|
PLSELLNKWIDTH => pl_sel_lnk_width,
|
1429 |
|
|
PLTXPMSTATE => pl_tx_pm_state,
|
1430 |
|
|
RECEIVEDFUNCLVLRSTN => received_func_lvl_rst_n,
|
1431 |
|
|
TL2ASPMSUSPENDCREDITCHECKOK => tl2_aspm_suspend_credit_check_ok,
|
1432 |
|
|
TL2ASPMSUSPENDREQ => tl2_aspm_suspend_req,
|
1433 |
|
|
TL2ERRFCPE => tl2_err_fcpe,
|
1434 |
|
|
TL2ERRHDR => tl2_err_hdr,
|
1435 |
|
|
TL2ERRMALFORMED => tl2_err_malformed,
|
1436 |
|
|
TL2ERRRXOVERFLOW => tl2_err_rxoverflow,
|
1437 |
|
|
TL2PPMSUSPENDOK => tl2_ppm_suspend_ok,
|
1438 |
|
|
TRNFCCPLD => trn_fc_cpld,
|
1439 |
|
|
TRNFCCPLH => trn_fc_cplh,
|
1440 |
|
|
TRNFCNPD => trn_fc_npd,
|
1441 |
|
|
TRNFCNPH => trn_fc_nph,
|
1442 |
|
|
TRNFCPD => trn_fc_pd,
|
1443 |
|
|
TRNFCPH => trn_fc_ph,
|
1444 |
|
|
TRNLNKUP => trn_lnk_up,
|
1445 |
|
|
TRNRBARHIT => trn_rbar_hit,
|
1446 |
|
|
TRNRD => trn_rd_int,
|
1447 |
|
|
TRNRDLLPDATA => trn_rdllp_data,
|
1448 |
|
|
TRNRDLLPSRCRDY => trn_rdllp_src_rdy,
|
1449 |
|
|
TRNRECRCERR => trn_recrc_err,
|
1450 |
|
|
TRNREOF => trn_reof,
|
1451 |
|
|
TRNRERRFWD => trn_rerrfwd,
|
1452 |
|
|
TRNRREM => trn_rrem_int,
|
1453 |
|
|
TRNRSOF => trn_rsof,
|
1454 |
|
|
TRNRSRCDSC => trn_rsrc_dsc,
|
1455 |
|
|
TRNRSRCRDY => trn_rsrc_rdy,
|
1456 |
|
|
TRNTBUFAV => trn_tbuf_av,
|
1457 |
|
|
TRNTCFGREQ => trn_tcfg_req,
|
1458 |
|
|
TRNTDLLPDSTRDY => trn_tdllp_dst_rdy,
|
1459 |
|
|
TRNTDSTRDY => trn_tdst_rdy_bus,
|
1460 |
|
|
TRNTERRDROP => trn_terr_drop,
|
1461 |
|
|
USERRSTN => user_rst_n,
|
1462 |
|
|
CFGAERINTERRUPTMSGNUM => cfg_aer_interrupt_msgnum,
|
1463 |
|
|
CFGDEVID => cfg_dev_id,
|
1464 |
|
|
CFGDSBUSNUMBER => cfg_ds_bus_number,
|
1465 |
|
|
CFGDSDEVICENUMBER => cfg_ds_device_number,
|
1466 |
|
|
CFGDSFUNCTIONNUMBER => cfg_ds_function_number,
|
1467 |
|
|
CFGDSN => cfg_dsn,
|
1468 |
|
|
CFGERRACSN => cfg_err_acs_n,
|
1469 |
|
|
CFGERRAERHEADERLOG => cfg_err_aer_headerlog,
|
1470 |
|
|
CFGERRATOMICEGRESSBLOCKEDN => cfg_err_atomic_egress_blocked_n,
|
1471 |
|
|
CFGERRCORN => cfg_err_cor_n,
|
1472 |
|
|
CFGERRCPLABORTN => cfg_err_cpl_abort_n,
|
1473 |
|
|
CFGERRCPLTIMEOUTN => cfg_err_cpl_timeout_n,
|
1474 |
|
|
CFGERRCPLUNEXPECTN => cfg_err_cpl_unexpect_n,
|
1475 |
|
|
CFGERRECRCN => cfg_err_ecrc_n,
|
1476 |
|
|
CFGERRINTERNALCORN => cfg_err_internal_cor_n,
|
1477 |
|
|
CFGERRINTERNALUNCORN => cfg_err_internal_uncor_n,
|
1478 |
|
|
CFGERRLOCKEDN => cfg_err_locked_n,
|
1479 |
|
|
CFGERRMALFORMEDN => cfg_err_malformed_n,
|
1480 |
|
|
CFGERRMCBLOCKEDN => cfg_err_mc_blocked_n,
|
1481 |
|
|
CFGERRNORECOVERYN => cfg_err_norecovery_n,
|
1482 |
|
|
CFGERRPOISONEDN => cfg_err_poisoned_n,
|
1483 |
|
|
CFGERRPOSTEDN => cfg_err_posted_n,
|
1484 |
|
|
CFGERRTLPCPLHEADER => cfg_err_tlp_cpl_header,
|
1485 |
|
|
CFGERRURN => cfg_err_ur_n,
|
1486 |
|
|
CFGFORCECOMMONCLOCKOFF => cfg_force_common_clock_off,
|
1487 |
|
|
CFGFORCEEXTENDEDSYNCON => cfg_force_extended_sync_on,
|
1488 |
|
|
CFGFORCEMPS => cfg_force_mps,
|
1489 |
|
|
CFGINTERRUPTASSERTN => cfg_interrupt_assert_n,
|
1490 |
|
|
CFGINTERRUPTDI => cfg_interrupt_di,
|
1491 |
|
|
CFGINTERRUPTN => cfg_interrupt_n,
|
1492 |
|
|
CFGINTERRUPTSTATN => cfg_interrupt_stat_n,
|
1493 |
|
|
CFGMGMTBYTEENN => cfg_mgmt_byte_en_n,
|
1494 |
|
|
CFGMGMTDI => cfg_mgmt_di,
|
1495 |
|
|
CFGMGMTDWADDR => cfg_mgmt_dwaddr,
|
1496 |
|
|
CFGMGMTRDENN => cfg_mgmt_rd_en_n,
|
1497 |
|
|
CFGMGMTWRENN => cfg_mgmt_wr_en_n,
|
1498 |
|
|
CFGMGMTWRREADONLYN => cfg_mgmt_wr_readonly_n,
|
1499 |
|
|
CFGMGMTWRRW1CASRWN => cfg_mgmt_wr_rw1c_as_rw_n,
|
1500 |
|
|
CFGPCIECAPINTERRUPTMSGNUM => cfg_pciecap_interrupt_msgnum,
|
1501 |
|
|
CFGPMFORCESTATE => cfg_pm_force_state,
|
1502 |
|
|
CFGPMFORCESTATEENN => cfg_pm_force_state_en_n,
|
1503 |
|
|
CFGPMHALTASPML0SN => cfg_pm_halt_aspm_l0s_n,
|
1504 |
|
|
CFGPMHALTASPML1N => cfg_pm_halt_aspm_l1_n,
|
1505 |
|
|
CFGPMSENDPMETON => cfg_pm_send_pme_to_n,
|
1506 |
|
|
CFGPMTURNOFFOKN => cfg_pm_turnoff_ok_n,
|
1507 |
|
|
CFGPMWAKEN => cfg_pm_wake_n,
|
1508 |
|
|
CFGPORTNUMBER => cfg_port_number,
|
1509 |
|
|
CFGREVID => cfg_rev_id,
|
1510 |
|
|
CFGSUBSYSID => cfg_subsys_id,
|
1511 |
|
|
CFGSUBSYSVENDID => cfg_subsys_vend_id,
|
1512 |
|
|
CFGTRNPENDINGN => cfg_trn_pending_n,
|
1513 |
|
|
CFGVENDID => cfg_vend_id,
|
1514 |
|
|
CMRSTN => cm_rst_n,
|
1515 |
|
|
CMSTICKYRSTN => cm_sticky_rst_n,
|
1516 |
|
|
DBGMODE => dbg_mode,
|
1517 |
|
|
DBGSUBMODE => dbg_sub_mode,
|
1518 |
|
|
DLRSTN => dl_rst_n,
|
1519 |
|
|
DRPADDR => "000000000",
|
1520 |
|
|
DRPCLK => '0',
|
1521 |
|
|
DRPDI => X"0000",
|
1522 |
|
|
DRPEN => '0',
|
1523 |
|
|
DRPWE => '0',
|
1524 |
|
|
DRPDO => open,
|
1525 |
|
|
DRPRDY => open,
|
1526 |
|
|
FUNCLVLRSTN => func_lvl_rst_n,
|
1527 |
|
|
LL2SENDASREQL1 => ll2_send_as_req_l1,
|
1528 |
|
|
LL2SENDENTERL1 => ll2_send_enter_l1,
|
1529 |
|
|
LL2SENDENTERL23 => ll2_send_enter_l23,
|
1530 |
|
|
LL2SENDPMACK => ll2_send_pm_ack,
|
1531 |
|
|
LL2SUSPENDNOW => ll2_suspend_now,
|
1532 |
|
|
LL2TLPRCV => ll2_tlp_rcv,
|
1533 |
|
|
MIMRXRDATA => mim_rx_rdata,
|
1534 |
|
|
MIMTXRDATA => mim_tx_rdata,
|
1535 |
|
|
PIPECLK => pipe_clk,
|
1536 |
|
|
PIPERX0CHANISALIGNED => pipe_rx0_chanisaligned,
|
1537 |
|
|
PIPERX0CHARISK => pipe_rx0_char_is_k,
|
1538 |
|
|
PIPERX0DATA => pipe_rx0_data,
|
1539 |
|
|
PIPERX0ELECIDLE => pipe_rx0_elec_idle,
|
1540 |
|
|
PIPERX0PHYSTATUS => pipe_rx0_phy_status,
|
1541 |
|
|
PIPERX0STATUS => pipe_rx0_status,
|
1542 |
|
|
PIPERX0VALID => pipe_rx0_valid,
|
1543 |
|
|
PIPERX1CHANISALIGNED => pipe_rx1_chanisaligned,
|
1544 |
|
|
PIPERX1CHARISK => pipe_rx1_char_is_k,
|
1545 |
|
|
PIPERX1DATA => pipe_rx1_data,
|
1546 |
|
|
PIPERX1ELECIDLE => pipe_rx1_elec_idle,
|
1547 |
|
|
PIPERX1PHYSTATUS => pipe_rx1_phy_status,
|
1548 |
|
|
PIPERX1STATUS => pipe_rx1_status,
|
1549 |
|
|
PIPERX1VALID => pipe_rx1_valid,
|
1550 |
|
|
PIPERX2CHANISALIGNED => pipe_rx2_chanisaligned,
|
1551 |
|
|
PIPERX2CHARISK => pipe_rx2_char_is_k,
|
1552 |
|
|
PIPERX2DATA => pipe_rx2_data,
|
1553 |
|
|
PIPERX2ELECIDLE => pipe_rx2_elec_idle,
|
1554 |
|
|
PIPERX2PHYSTATUS => pipe_rx2_phy_status,
|
1555 |
|
|
PIPERX2STATUS => pipe_rx2_status,
|
1556 |
|
|
PIPERX2VALID => pipe_rx2_valid,
|
1557 |
|
|
PIPERX3CHANISALIGNED => pipe_rx3_chanisaligned,
|
1558 |
|
|
PIPERX3CHARISK => pipe_rx3_char_is_k,
|
1559 |
|
|
PIPERX3DATA => pipe_rx3_data,
|
1560 |
|
|
PIPERX3ELECIDLE => pipe_rx3_elec_idle,
|
1561 |
|
|
PIPERX3PHYSTATUS => pipe_rx3_phy_status,
|
1562 |
|
|
PIPERX3STATUS => pipe_rx3_status,
|
1563 |
|
|
PIPERX3VALID => pipe_rx3_valid,
|
1564 |
|
|
PIPERX4CHANISALIGNED => pipe_rx4_chanisaligned,
|
1565 |
|
|
PIPERX4CHARISK => pipe_rx4_char_is_k,
|
1566 |
|
|
PIPERX4DATA => pipe_rx4_data,
|
1567 |
|
|
PIPERX4ELECIDLE => pipe_rx4_elec_idle,
|
1568 |
|
|
PIPERX4PHYSTATUS => pipe_rx4_phy_status,
|
1569 |
|
|
PIPERX4STATUS => pipe_rx4_status,
|
1570 |
|
|
PIPERX4VALID => pipe_rx4_valid,
|
1571 |
|
|
PIPERX5CHANISALIGNED => pipe_rx5_chanisaligned,
|
1572 |
|
|
PIPERX5CHARISK => pipe_rx5_char_is_k,
|
1573 |
|
|
PIPERX5DATA => pipe_rx5_data,
|
1574 |
|
|
PIPERX5ELECIDLE => pipe_rx5_elec_idle,
|
1575 |
|
|
PIPERX5PHYSTATUS => pipe_rx5_phy_status,
|
1576 |
|
|
PIPERX5STATUS => pipe_rx5_status,
|
1577 |
|
|
PIPERX5VALID => pipe_rx5_valid,
|
1578 |
|
|
PIPERX6CHANISALIGNED => pipe_rx6_chanisaligned,
|
1579 |
|
|
PIPERX6CHARISK => pipe_rx6_char_is_k,
|
1580 |
|
|
PIPERX6DATA => pipe_rx6_data,
|
1581 |
|
|
PIPERX6ELECIDLE => pipe_rx6_elec_idle,
|
1582 |
|
|
PIPERX6PHYSTATUS => pipe_rx6_phy_status,
|
1583 |
|
|
PIPERX6STATUS => pipe_rx6_status,
|
1584 |
|
|
PIPERX6VALID => pipe_rx6_valid,
|
1585 |
|
|
PIPERX7CHANISALIGNED => pipe_rx7_chanisaligned,
|
1586 |
|
|
PIPERX7CHARISK => pipe_rx7_char_is_k,
|
1587 |
|
|
PIPERX7DATA => pipe_rx7_data,
|
1588 |
|
|
PIPERX7ELECIDLE => pipe_rx7_elec_idle,
|
1589 |
|
|
PIPERX7PHYSTATUS => pipe_rx7_phy_status,
|
1590 |
|
|
PIPERX7STATUS => pipe_rx7_status,
|
1591 |
|
|
PIPERX7VALID => pipe_rx7_valid,
|
1592 |
|
|
PL2DIRECTEDLSTATE => pl2_directed_lstate,
|
1593 |
|
|
PLDBGMODE => pl_dbg_mode,
|
1594 |
|
|
PLDIRECTEDLINKAUTON => pl_directed_link_auton,
|
1595 |
|
|
PLDIRECTEDLINKCHANGE => pl_directed_link_change,
|
1596 |
|
|
PLDIRECTEDLINKSPEED => pl_directed_link_speed,
|
1597 |
|
|
PLDIRECTEDLINKWIDTH => pl_directed_link_width,
|
1598 |
|
|
PLDIRECTEDLTSSMNEW => pl_directed_ltssm_new,
|
1599 |
|
|
PLDIRECTEDLTSSMNEWVLD => pl_directed_ltssm_new_vld,
|
1600 |
|
|
PLDIRECTEDLTSSMSTALL => pl_directed_ltssm_stall,
|
1601 |
|
|
PLDOWNSTREAMDEEMPHSOURCE => pl_downstream_deemph_source,
|
1602 |
|
|
PLRSTN => pl_rst_n,
|
1603 |
|
|
PLTRANSMITHOTRST => pl_transmit_hot_rst,
|
1604 |
|
|
PLUPSTREAMPREFERDEEMPH => pl_upstream_prefer_deemph,
|
1605 |
|
|
SYSRSTN => sys_rst_n,
|
1606 |
|
|
TL2ASPMSUSPENDCREDITCHECK => tl2_aspm_suspend_credit_check,
|
1607 |
|
|
TL2PPMSUSPENDREQ => tl2_ppm_suspend_req,
|
1608 |
|
|
TLRSTN => tl_rst_n,
|
1609 |
|
|
TRNFCSEL => trn_fc_sel,
|
1610 |
|
|
TRNRDSTRDY => trn_rdst_rdy,
|
1611 |
|
|
TRNRFCPRET => trn_rfcp_ret,
|
1612 |
|
|
TRNRNPOK => trn_rnp_ok,
|
1613 |
|
|
TRNRNPREQ => trn_rnp_req,
|
1614 |
|
|
TRNTCFGGNT => trn_tcfg_gnt,
|
1615 |
|
|
TRNTD => trn_td_int,
|
1616 |
|
|
TRNTDLLPDATA => trn_tdllp_data,
|
1617 |
|
|
TRNTDLLPSRCRDY => trn_tdllp_src_rdy,
|
1618 |
|
|
TRNTECRCGEN => trn_tecrc_gen,
|
1619 |
|
|
TRNTEOF => trn_teof,
|
1620 |
|
|
TRNTERRFWD => trn_terrfwd,
|
1621 |
|
|
TRNTREM => trn_trem_int,
|
1622 |
|
|
TRNTSOF => trn_tsof,
|
1623 |
|
|
TRNTSRCDSC => trn_tsrc_dsc,
|
1624 |
|
|
TRNTSRCRDY => trn_tsrc_rdy,
|
1625 |
|
|
TRNTSTR => trn_tstr,
|
1626 |
|
|
USERCLK => user_clk,
|
1627 |
|
|
USERCLK2 => user_clk2
|
1628 |
|
|
);
|
1629 |
|
|
|
1630 |
|
|
end rtl;
|