Subversion Repositories pcie_ds_dma

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-- Project    : Series-7 Integrated Block for PCI Express

-- File       : cl_a7pcie_x4_pcie_pipe_misc.vhd

-- Version    : 1.10

-- Description: Misc PIPE module for 7-SeriesPCIe Block

--

--

--

----------------------------------------------------------------------------------

library ieee;

   use ieee.std_logic_1164.all;

entity cl_a7pcie_x4_pcie_pipe_misc is

  generic (

     PIPE_PIPELINE_STAGES                         : integer := 0  -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages

  );

  port (

    pipe_tx_rcvr_det_i                           : in std_logic;                        -- PIPE Tx Receiver Detect

    pipe_tx_reset_i                              : in std_logic;                        -- PIPE Tx Reset

    pipe_tx_rate_i                               : in std_logic;                        -- PIPE Tx Rate

    pipe_tx_deemph_i                             : in std_logic;                        -- PIPE Tx Deemphasis

    pipe_tx_margin_i                             : in std_logic_vector(2 downto 0);     -- PIPE Tx Margin

    pipe_tx_swing_i                              : in std_logic;                        -- PIPE Tx Swing

    pipe_tx_rcvr_det_o                           : out std_logic;                       -- Pipelined PIPE Tx Receiver Detect

    pipe_tx_reset_o                              : out std_logic;                       -- Pipelined PIPE Tx Reset

    pipe_tx_rate_o                               : out std_logic;                       -- Pipelined PIPE Tx Rate

    pipe_tx_deemph_o                             : out std_logic;                       -- Pipelined PIPE Tx Deemphasis

    pipe_tx_margin_o                             : out std_logic_vector(2 downto 0);    -- Pipelined PIPE Tx Margin

    pipe_tx_swing_o                              : out std_logic;                       -- Pipelined PIPE Tx Swing

    pipe_clk                                     : in std_logic;                        -- PIPE Clock

    rst_n                                        : in std_logic                         -- Reset

  );

end cl_a7pcie_x4_pcie_pipe_misc;

architecture rtl of cl_a7pcie_x4_pcie_pipe_misc is

  --******************************************************************//

  -- Reality check.                                                   //

  --******************************************************************//

  constant TCQ                                    : integer := 1;  -- clock to out delay model

  signal pipe_tx_rcvr_det_q                       : std_logic;

  signal pipe_tx_reset_q                          : std_logic;

  signal pipe_tx_rate_q                           : std_logic;

  signal pipe_tx_deemph_q                         : std_logic;

  signal pipe_tx_margin_q                         : std_logic_vector(2 downto 0);

  signal pipe_tx_swing_q                          : std_logic;

  signal pipe_tx_rcvr_det_qq                      : std_logic;

  signal pipe_tx_reset_qq                         : std_logic;

  signal pipe_tx_rate_qq                          : std_logic;

  signal pipe_tx_deemph_qq                        : std_logic;

  signal pipe_tx_margin_qq                        : std_logic_vector(2 downto 0);

  signal pipe_tx_swing_qq                         : std_logic;

begin

  pipe_stages_0 : if (PIPE_PIPELINE_STAGES = 0) generate

    pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_i;

    pipe_tx_reset_o <= pipe_tx_reset_i;

    pipe_tx_rate_o <= pipe_tx_rate_i;

    pipe_tx_deemph_o <= pipe_tx_deemph_i;

    pipe_tx_margin_o <= pipe_tx_margin_i;

    pipe_tx_swing_o <= pipe_tx_swing_i;

  end generate;                         -- pipe_stages_0

  pipe_stages_1 : if (PIPE_PIPELINE_STAGES = 1) generate

    process (pipe_clk)

    begin

      if (pipe_clk'event and pipe_clk = '1') then

        if (rst_n = '1') then

          pipe_tx_rcvr_det_q <= '0' after (TCQ)*1 ps;

          pipe_tx_reset_q <= '1' after (TCQ)*1 ps;

          pipe_tx_rate_q <= '0' after (TCQ)*1 ps;

          pipe_tx_deemph_q <= '1' after (TCQ)*1 ps;

          pipe_tx_margin_q <= "000" after (TCQ)*1 ps;

          pipe_tx_swing_q <= '0' after (TCQ)*1 ps;

        else

          pipe_tx_rcvr_det_q <= pipe_tx_rcvr_det_i after (TCQ)*1 ps;

          pipe_tx_reset_q <= pipe_tx_reset_i after (TCQ)*1 ps;

          pipe_tx_rate_q <= pipe_tx_rate_i after (TCQ)*1 ps;

          pipe_tx_deemph_q <= pipe_tx_deemph_i after (TCQ)*1 ps;

          pipe_tx_margin_q <= pipe_tx_margin_i after (TCQ)*1 ps;

          pipe_tx_swing_q <= pipe_tx_swing_i after (TCQ)*1 ps;

        end if;

      end if;

    end process;

    pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_q;

    pipe_tx_reset_o <= pipe_tx_reset_q;

    pipe_tx_rate_o <= pipe_tx_rate_q;

    pipe_tx_deemph_o <= pipe_tx_deemph_q;

    pipe_tx_margin_o <= pipe_tx_margin_q;

    pipe_tx_swing_o <= pipe_tx_swing_q;

  end generate;                        -- pipe_stages_1

  pipe_stages_2 : if (PIPE_PIPELINE_STAGES = 2) generate

    process (pipe_clk)

    begin

      if (pipe_clk'event and pipe_clk = '1') then

        if (rst_n = '1') then

          pipe_tx_rcvr_det_q <= '0' after (TCQ)*1 ps;

          pipe_tx_reset_q <= '1' after (TCQ)*1 ps;

          pipe_tx_rate_q <= '0' after (TCQ)*1 ps;

          pipe_tx_deemph_q <= '1' after (TCQ)*1 ps;

          pipe_tx_margin_q <= "000" after (TCQ)*1 ps;

          pipe_tx_swing_q <= '0' after (TCQ)*1 ps;

          pipe_tx_rcvr_det_qq <= '0' after (TCQ)*1 ps;

          pipe_tx_reset_qq <= '1' after (TCQ)*1 ps;

          pipe_tx_rate_qq <= '0' after (TCQ)*1 ps;

          pipe_tx_deemph_qq <= '1' after (TCQ)*1 ps;

          pipe_tx_margin_qq <= "000" after (TCQ)*1 ps;

          pipe_tx_swing_qq <= '0' after (TCQ)*1 ps;

        else

          pipe_tx_rcvr_det_q <= pipe_tx_rcvr_det_i after (TCQ)*1 ps;

          pipe_tx_reset_q <= pipe_tx_reset_i after (TCQ)*1 ps;

          pipe_tx_rate_q <= pipe_tx_rate_i after (TCQ)*1 ps;

          pipe_tx_deemph_q <= pipe_tx_deemph_i after (TCQ)*1 ps;

          pipe_tx_margin_q <= pipe_tx_margin_i after (TCQ)*1 ps;

          pipe_tx_swing_q <= pipe_tx_swing_i after (TCQ)*1 ps;

          pipe_tx_rcvr_det_qq <= pipe_tx_rcvr_det_q after (TCQ)*1 ps;

          pipe_tx_reset_qq <= pipe_tx_reset_q after (TCQ)*1 ps;

          pipe_tx_rate_qq <= pipe_tx_rate_q after (TCQ)*1 ps;

          pipe_tx_deemph_qq <= pipe_tx_deemph_q after (TCQ)*1 ps;

          pipe_tx_margin_qq <= pipe_tx_margin_q after (TCQ)*1 ps;

          pipe_tx_swing_qq <= pipe_tx_swing_q after (TCQ)*1 ps;

        end if;

      end if;

    end process;

    pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_qq;

    pipe_tx_reset_o <= pipe_tx_reset_qq;

    pipe_tx_rate_o <= pipe_tx_rate_qq;

    pipe_tx_deemph_o <= pipe_tx_deemph_qq;

    pipe_tx_margin_o <= pipe_tx_margin_qq;

    pipe_tx_swing_o <= pipe_tx_swing_qq;

  end generate;                        -- pipe_stages_2

end rtl;