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dsmv |
[Project]
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Current Flow=Multivendor
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VCS=0
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version=3
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Current Config=compile
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[Configurations]
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compile=sp605_lx45t_wishbone
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[Library]
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sp605_lx45t_wishbone=.\sp605_lx45t_wishbone.LIB
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dsmv |
sp605_lx45t_wishbone_post_synthesis=.\sp605_lx45t_wishbone_post_synthesis\sp605_lx45t_wishbone_post_synthesis.lib
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dsmv |
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14 |
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[Settings]
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15 |
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AccessRead=0
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16 |
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AccessReadWrite=0
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17 |
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AccessACCB=0
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18 |
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AccessACCR=0
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19 |
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AccessReadWriteSLP=0
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20 |
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AccessReadTopLevel=1
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21 |
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DisableC=1
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22 |
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ENABLE_ADV_DATAFLOW=0
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38 |
dsmv |
SYNTH_TOOL=MV_XST132
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IMPL_TOOL=MV_ISE132
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dsmv |
CSYNTH_TOOL=
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PHYSSYNTH_TOOL=
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FLOW_TYPE=HDL
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LANGUAGE=VHDL
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FLOWTOOLS=IMPL_WITH_SYNTH
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ON_SERVERFARM_SYNTH=0
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ON_SERVERFARM_IMPL=0
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32 |
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ON_SERVERFARM_SIM=0
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33 |
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DVM_DISPLAY=NO
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34 |
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REFRESH_FLOW=1
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35 |
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dsmv |
FAMILY=Xilinx13x SPARTAN6
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36 |
2 |
dsmv |
RUN_MODE_SYNTH=0
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37 |
38 |
dsmv |
VerilogDirsChanged=0
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38 |
2 |
dsmv |
WireDelay=2
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39 |
10 |
dsmv |
NoTchkMsg=1
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40 |
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NoTimingChecks=1
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41 |
2 |
dsmv |
HESPrepare=0
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42 |
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EnableXtrace=0
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43 |
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SplitNetVectors=0
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44 |
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StackMemorySize=32
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RetvalMemorySize=32
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53 |
dsmv |
VsimAdditionalOptions=-relax -g test_id=2
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2 |
dsmv |
ReportAssertionsActivations=0
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48 |
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TrackAssertionFailures=1
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ReportAssertionsFailures=1
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50 |
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AssertionFailureLimit=0
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51 |
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AssertionFailureAction=Continue
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52 |
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TrackAssertionPasses=1
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53 |
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ReportAssertionPasses=0
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54 |
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AssertionPassLimit=0
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55 |
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ReportUnfinishedAssertions=1
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56 |
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TrackCoverMatches=1
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57 |
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ReportCoverMatches=1
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58 |
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CoverAction=Continue
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59 |
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ReportDroppedCoverEvaluations=0
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60 |
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ReportActivatedCoverEvaluations=0
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61 |
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fileopeninsrc=1
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fileopenfolder=E:\prog\ds_dma_project\sp605_lx45t_wishbone
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dsmv |
DisableVitalMsg=1
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64 |
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VitalAccel=1
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VitalGlitches=1
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66 |
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DisableIEEEWarnings=1
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67 |
38 |
dsmv |
SYNTH_STATUS=warnings
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IMPL_STATUS=warnings
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69 |
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PHYSSYNTH_STATUS=none
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70 |
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PCBINTERFACE_STATUS=NONE
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71 |
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FUNCTIONAL_SIMULATION_STATUS=
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POSTSYNTHESIS_SIMULATION_STATUS=
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TIMING_SIMULATION_STATUS=
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FUNC_LIB=sp605_lx45t_wishbone
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POST_LIB=sp605_lx45t_wishbone_post_synthesis
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RUN_MODE_IMPL=0
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LAST_IMPL_STATUS=warnings
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53 |
dsmv |
resolution=Auto
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79 |
2 |
dsmv |
|
80 |
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[LocalVerilogSets]
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EnableSLP=1
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82 |
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EnableDebug=1
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VerilogLanguage=4
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84 |
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Strict=0
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85 |
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Strict2001=
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86 |
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SystemVerilog3=
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StrictLRMMode=
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VerilogNoSpecify=0
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89 |
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WarningPrnLevel=1
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90 |
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ErrorOutputLimit=0
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91 |
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OptimizationLevel=2
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92 |
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ProtectLevel=0
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93 |
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AdditionalOptions=
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94 |
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MonitoringOfEventsUDP=0
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95 |
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DisablePulseError=0
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96 |
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HasInitialRegsValue=0
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InitialRegsValue=X
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98 |
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99 |
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[LocalVhdlSets]
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100 |
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CompileWithDebug=1
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101 |
10 |
dsmv |
DisableVHDL87Key=0
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102 |
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EnableVHDL93Key=0
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103 |
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EnableVHDL2002Key=1
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104 |
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EnableVHDL2006Key=0
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105 |
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EnableVHDL2008Key=0
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106 |
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NetlistCompilation=1
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107 |
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Syntax RelaxLRM=0
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108 |
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MaxErrorsKey=100
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109 |
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OptimizationLevel=3
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110 |
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DisableRangeChecks=0
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111 |
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ProtectLevel=0
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112 |
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AdditionalOptions=
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113 |
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IncrementalCompilation=0
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114 |
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ReorderOnFirstRebuild=1
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115 |
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ElaborationAfterCompilation=0
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116 |
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PrintErrWarnOnly=0
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117 |
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GenMultiplatformLib=0
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118 |
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VhdlChangeEvalAsynchronous=0
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119 |
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VhdlDisableAssertionsProcessing=0
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120 |
2 |
dsmv |
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121 |
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[$LibMap$]
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sp605_lx45t_wishbone=.
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123 |
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dsmv |
Active_lib=SPARTAN6
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124 |
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xilinxun=SPARTAN6
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125 |
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UnlinkedDesignLibrary=SPARTAN6
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126 |
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DESIGNS=SPARTAN6
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127 |
2 |
dsmv |
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128 |
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[IMPLEMENTATION_XILINX12]
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129 |
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impl_opt(dont_run_translate)=0
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130 |
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impl_opt(dont_run_map)=0
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131 |
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impl_opt(dont_run_place)=0
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132 |
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impl_opt(dont_run_trace)=0
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133 |
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impl_opt(dont_run_simulation)=0
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134 |
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impl_opt(dont_run_fit)=0
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135 |
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impl_opt(dont_run_bitgen)=1
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136 |
38 |
dsmv |
impl_opt(use_partitions_in_flow)=0
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137 |
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impl_opt(partitions_file)=synthesis\xpartition.pxml
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138 |
2 |
dsmv |
|
139 |
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[HierarchyViewer]
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140 |
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SortInfo=u
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141 |
53 |
dsmv |
HierarchyInformation=pcie_core64_m6|pcie_core64_m6|0 stend_sp605_wishbone|stend_sp605_wishbone|0
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142 |
2 |
dsmv |
ShowHide=ShowTopLevel
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143 |
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Selected=
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144 |
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145 |
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[DefineMacro]
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146 |
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Global=
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147 |
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148 |
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[Folders]
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149 |
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Name3=Makefiles
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150 |
51 |
dsmv |
Directory3=E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
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151 |
2 |
dsmv |
Extension3=mak
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152 |
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Name4=Memory
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153 |
51 |
dsmv |
Directory4=E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\src
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154 |
2 |
dsmv |
Extension4=mem;mif;hex
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155 |
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Name5=Dll Libraries
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156 |
51 |
dsmv |
Directory5=E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
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157 |
2 |
dsmv |
Extension5=dll
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158 |
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Name6=PDF
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159 |
51 |
dsmv |
Directory6=E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
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160 |
2 |
dsmv |
Extension6=pdf
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161 |
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Name7=HTML
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162 |
51 |
dsmv |
Directory7=E:\prog\pcie_ds_dma\trunk\projects\sp605_lx45t_wishbone\
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163 |
2 |
dsmv |
Extension7=
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164 |
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165 |
10 |
dsmv |
[Verilog Library]
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166 |
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ovi_unimacro=
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167 |
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ovi_unisim=
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168 |
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ovi_xilinxcorelib=
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169 |
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|
170 |
38 |
dsmv |
[SYNTHESIS]
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171 |
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TOPLEVEL=sp605_lx45t_wishbone
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172 |
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FAMILY=Xilinx13x SPARTAN6
|
173 |
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DEVICE=6slx45tfgg484
|
174 |
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SPEED=-3
|
175 |
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OBSOLETE_ALIASES=1
|
176 |
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FILTER_MESSAGES=
|
177 |
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FSM_ENCODE=
|
178 |
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PACK_IO_REGISTERS=Auto
|
179 |
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SIMOUTFORM=1
|
180 |
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AUTO_CLOSE_GUI=0
|
181 |
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USE_DEF_UCF_FILE=1
|
182 |
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UCF_FILENAME=
|
183 |
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LSO_FILENAME=
|
184 |
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HDL_INI_FILENAME=
|
185 |
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XST_INCLUDE_PATH=src
|
186 |
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CORES_SEARCH_DIR=
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187 |
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OTHER_COMMAND_LINE_OPT=
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188 |
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XST_WORK_DIR=synthesis\xst
|
189 |
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PARTITIONS_FILE=
|
190 |
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Show_OptimizationGoalCombo=Speed
|
191 |
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Show_OptimizationEffortCombo=Normal
|
192 |
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Show_KeepHierarchyFPGA=Yes
|
193 |
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Show_Timing_Constraint=0
|
194 |
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Show_FSM_Encoding_Algorithm=Auto
|
195 |
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|
Show_MuxExtractionCombo=Yes
|
196 |
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|
Show_Resource_Sharing=1
|
197 |
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Show_Rom_Extraction=1
|
198 |
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Show_Ram_Extraction=1
|
199 |
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|
Show_RamStyleCombo=Auto
|
200 |
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|
Show_Shift_Register_Extraction=1
|
201 |
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|
Show_Add_IO_Buffer=1
|
202 |
|
|
Show_Equivalent_Register_Removal=0
|
203 |
|
|
Show_Max_Fanout=1000000
|
204 |
|
|
Show_Register_Duplication=0
|
205 |
|
|
Show_Register_Balancing=No
|
206 |
|
|
Show_Pack_IO_Registers_Into_IOBs=Auto
|
207 |
|
|
Show_Macro_Preserve=1
|
208 |
|
|
Show_Xor_Preserve=1
|
209 |
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|
Show_WysiwygCombo=None
|
210 |
|
|
Show_Case_Implementation_Style=None
|
211 |
|
|
Show_Global_Optimalization_Goal=AllClockNets
|
212 |
|
|
Show_JobDescription=SynthesisTask
|
213 |
|
|
Show_IncludeInputFiles=*.*
|
214 |
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|
Show_ExcludeInputFiles=log*.*:implement*.*
|
215 |
|
|
Show_UseSynthesisConstraintsFile=1
|
216 |
|
|
Show_CrossClockAnalysis=0
|
217 |
|
|
Show_HierarchySeparator=/
|
218 |
|
|
Show_BusDelimiter=<>
|
219 |
|
|
Show_GenerateRtlSchematic=Yes
|
220 |
|
|
Show_CaseVhdl=Maintain
|
221 |
|
|
Show_Verilog2001=1
|
222 |
|
|
Show_RomStyle=Auto
|
223 |
|
|
Show_ReadCores=1
|
224 |
|
|
Show_MaxNoBufgs16=0
|
225 |
|
|
Show_OptimizeInstantiatedPrimitives=0
|
226 |
|
|
Show_MoveFirstFlipFlopStage=
|
227 |
|
|
Show_MoveLastFlipFlopStage=
|
228 |
|
|
Show_FSMStyle=LUT
|
229 |
|
|
Show_SimulationOutputFormat=1
|
230 |
|
|
Show_KeepHierarchyCPLD=Yes
|
231 |
|
|
Show_SafeImplementation=No
|
232 |
|
|
Show_UseClockEnable=Auto
|
233 |
|
|
Show_UseSynchronousSet=Auto
|
234 |
|
|
Show_UseSynchronousReset=Auto
|
235 |
|
|
Show_FilterMessages=0
|
236 |
|
|
Show_DspUtilizationRatio=100
|
237 |
|
|
Show_LUT_FF_PairsUtilizationRatio=100
|
238 |
|
|
Show_PowerReduction=0
|
239 |
|
|
Show_BRAMUtilizationRatio=100
|
240 |
|
|
Show_AutomaticBRAMPacking=0
|
241 |
|
|
Show_AsynchronousToSynchronous=0
|
242 |
|
|
Show_NetlistHierarchy=As Optimized
|
243 |
|
|
Show_LUTCombining=Auto
|
244 |
|
|
Show_ReduceControlSets=Auto
|
245 |
|
|
Show_UseIseWithPartitions=0
|
246 |
|
|
Show_GenerateIseWithPartitions=1
|
247 |
|
|
Show_Add_Special_Library_Sources=1
|
248 |
|
|
Show_UseDSPBlock_S6_V6=Auto
|
249 |
|
|
Show_ShiftRegisterMinimumSize=2
|
250 |
|
|
Show_OptimizationEffortCombo_Fast=High
|
251 |
|
|
RAM_STYLE=Auto
|
252 |
|
|
ROM_STYLE=Auto
|
253 |
|
|
MUX_STYLE=Auto
|
254 |
|
|
MOVE_FIRST_FF_STAGE=1
|
255 |
|
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MOVE_LAST_FF_STAGE=1
|
256 |
|
|
JOB_DESCRIPTION=SynthesisTask
|
257 |
|
|
SERVERFARM_INCLUDE_INPUT_FILES=*.*
|
258 |
|
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SERVERFARM_EXCLUDE_INPUT_FILES=log*.*:implement*.*
|
259 |
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JOB_SFM_RESOURCE=
|
260 |
51 |
dsmv |
LAST_RUN=1375386863
|
261 |
38 |
dsmv |
OUTPUT_NETLIST=synthesis\sp605_lx45t_wishbone.ngc
|
262 |
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OUTPUT_SIMUL_NETLIST=synthesis\sp605_lx45t_wishbone.vhd
|
263 |
|
|
|
264 |
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[PHYS_SYNTHESIS]
|
265 |
|
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FAMILY=Xilinx13x SPARTAN6
|
266 |
|
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DEVICE=6slx45tfgg484
|
267 |
|
|
SPEED=-3
|
268 |
|
|
SCRIPTS_COPIED=0
|
269 |
|
|
IN_DESIGN=synthesis\sp605_lx45t_wishbone.ngc
|
270 |
|
|
OUT_DESIGN=
|
271 |
|
|
IN_CONSTRAINT=
|
272 |
|
|
OUT_CONSTRAINT=
|
273 |
|
|
REPORT=
|
274 |
|
|
|
275 |
|
|
[IMPLEMENTATION]
|
276 |
|
|
FLOW_STEPS_RESET=0
|
277 |
|
|
FAMILY=Xilinx13x SPARTAN6
|
278 |
|
|
DEVICE=6slx45tfgg484
|
279 |
|
|
SPEED=-3
|
280 |
|
|
NETLIST=synthesis\sp605_lx45t_wishbone.ngc
|
281 |
|
|
IS_BAT_MODE=0
|
282 |
|
|
BAT_FILE=
|
283 |
|
|
UCF=src\top\sp605_lx45t_wishbone.ucf
|
284 |
|
|
DEF_UCF=2
|
285 |
|
|
OLD_FAMILY=Xilinx13x SPARTAN6
|
286 |
|
|
wasChanged_Change_Device_Speed=0
|
287 |
|
|
wasChanged_Change_Device_Speed_To=0
|
288 |
|
|
wasChanged_Change_Device_Speed_To2=1
|
289 |
|
|
Place_And_Route_Mode_old_value=Route Only
|
290 |
|
|
JOB_DESCRIPTION=ImplementationTask
|
291 |
|
|
SERVERFARM_INCLUDE_INPUT_FILES=*.*
|
292 |
|
|
SERVERFARM_EXCLUDE_INPUT_FILES=log\*.*
|
293 |
|
|
JOB_SFM_RESOURCE=
|
294 |
|
|
SYNTH_TOOL_RESET=0
|
295 |
51 |
dsmv |
LAST_RUN=1375387391
|
296 |
38 |
dsmv |
|
297 |
|
|
[IMPLEMENTATION_XILINX13]
|
298 |
|
|
impl_opt(dont_run_translate)=0
|
299 |
|
|
impl_opt(dont_run_map)=0
|
300 |
|
|
impl_opt(dont_run_place)=0
|
301 |
|
|
impl_opt(dont_run_trace)=0
|
302 |
|
|
impl_opt(dont_run_simulation)=1
|
303 |
|
|
impl_opt(dont_run_fit)=0
|
304 |
|
|
impl_opt(dont_run_bitgen)=0
|
305 |
|
|
Macro_Search_Path={src\wishbone\coregen} {src\pcie_src\components\coregen}
|
306 |
|
|
impl_opt(partitions_file)=
|
307 |
|
|
impl_opt(use_partitions_file)=0
|
308 |
51 |
dsmv |
impl_opt(smart_guide_file)=implement\ver1\rev1\sp605_lx45t_wishbone_guide.ncd
|
309 |
38 |
dsmv |
impl_opt(use_smart_guide)=0
|
310 |
|
|
impl_opt(edif_str)=synthesis\sp605_lx45t_wishbone.ngc
|
311 |
|
|
impl_opt(_family_sel)=Xilinx13x SPARTAN6
|
312 |
|
|
impl_opt(_device_sel)=6slx45tfgg484
|
313 |
|
|
impl_opt(_speed_sel)=-3
|
314 |
51 |
dsmv |
impl_opt(Effort_Level)=High
|
315 |
38 |
dsmv |
impl_opt(netlist_format)=1
|
316 |
|
|
impl_opt(auto_close)=0
|
317 |
|
|
impl_opt(override_existing_project)=1
|
318 |
|
|
impl_opt(bat_file_name)=
|
319 |
|
|
impl_opt(is_bat_mode)=0
|
320 |
|
|
impl_opt(def_ucf)=Custom constraint file
|
321 |
|
|
impl_opt(ucf_str)=src\top\sp605_lx45t_wishbone.ucf
|
322 |
|
|
impl_opt(version_sel)=ver1
|
323 |
|
|
impl_opt(revision_sel)=rev1
|
324 |
|
|
impl_opt(insert_pads)=0
|
325 |
|
|
impl_opt(Pack_IO_Registers_Latches)=For Inputs and Outputs
|
326 |
|
|
impl_opt(ignore_rloc_constraints)=1
|
327 |
|
|
impl_opt(create_detailed_report)=0
|
328 |
|
|
impl_opt(ngdbuild_file_str)=
|
329 |
|
|
impl_opt(use_ngdbuild_file)=0
|
330 |
|
|
impl_opt(map_file_str)=
|
331 |
|
|
impl_opt(use_map_file)=0
|
332 |
|
|
impl_opt(par_file_str)=
|
333 |
|
|
impl_opt(use_par_file)=0
|
334 |
|
|
impl_opt(trace_file_str)=
|
335 |
|
|
impl_opt(use_trace_file)=0
|
336 |
|
|
impl_opt(netgen_file_str)=
|
337 |
|
|
impl_opt(use_netgen_file)=0
|
338 |
|
|
impl_opt(bitgen_file_str)=
|
339 |
|
|
impl_opt(use_bitgen_file)=0
|
340 |
|
|
impl_opt(Allow_Unmatched_LOC_Constraint)=1
|
341 |
|
|
impl_opt(Show_Trim_Unconnected_Signals)=1
|
342 |
|
|
impl_opt(Place_And_Route_Mode)=Route Only
|
343 |
|
|
impl_opt(Show_Generate_Multiple_Hierarchical_Netlist_Files)=0
|
344 |
|
|
impl_opt(Show_Bring_Out_Global_Trisate_Net_As_Ports)=
|
345 |
|
|
impl_opt(Use_Show_Bring_Out_Global_Trisate_Net_As_Ports)=0
|
346 |
|
|
impl_opt(Show_Bring_Out_Global_Set_Reset_Net_As_Ports)=
|
347 |
|
|
impl_opt(Use_Show_Bring_Out_Global_Set_Reset_Net_As_Ports)=0
|
348 |
|
|
impl_opt(Show_Generate_Testbench_File)=UUT
|
349 |
|
|
impl_opt(Use_Show_Generate_Testbench_File)=0
|
350 |
|
|
impl_opt(Netlist_Translation_Type)=Timestamp
|
351 |
|
|
impl_opt(Allow_Unexpanded_Blocks)=0
|
352 |
|
|
impl_opt(Other_Ngdbuild_Options)=
|
353 |
|
|
impl_opt(Map_Effort_Level)=High
|
354 |
|
|
impl_opt(Allow_Logic_Opt_Across_Hier)=1
|
355 |
|
|
impl_opt(Use_Rloc_Constraints)=Yes
|
356 |
|
|
impl_opt(Show_Map_Slice_Logic_Into_Unused_Blocks)=0
|
357 |
|
|
impl_opt(Other_Map_Options)=
|
358 |
51 |
dsmv |
impl_opt(Extra_Effort)=Normal
|
359 |
38 |
dsmv |
impl_opt(Retain_Hiearchy)=1
|
360 |
|
|
impl_opt(Change_Device_Speed)=3
|
361 |
|
|
impl_opt(Tristate_Configuration_Pulsee)=0
|
362 |
|
|
impl_opt(Reset_Configuration_Pulsee)=100
|
363 |
|
|
impl_opt(Generate_Architecture_Only)=0
|
364 |
|
|
impl_opt(Include_Uselib_Directive)=0
|
365 |
|
|
impl_opt(Do_Not_Escape_Signal)=0
|
366 |
|
|
impl_opt(Other_Netgen_Command)=
|
367 |
|
|
impl_opt(Show_Other_Place_Route_Command)=
|
368 |
|
|
impl_opt(Use_Rules_File_For_Nelist)=
|
369 |
|
|
impl_opt(Path_Used_In_Sdf)=implement
|
370 |
|
|
impl_opt(Insert_ChipScope_Core)=0
|
371 |
|
|
impl_opt(Run_ChipScope_Core_Inserter_GUI)=1
|
372 |
|
|
impl_opt(ChipScope_Core_Inserter_Project_File)=synthesis\sp605_lx45t_wishbone.cdc
|
373 |
|
|
impl_opt(_use_filter_messages)=0
|
374 |
|
|
impl_opt(_filter_messages)=
|
375 |
51 |
dsmv |
impl_opt(AdvMap_Extra_Effort)=Normal
|
376 |
38 |
dsmv |
impl_opt(Map_Starting_Placer_Cost_Table)=1
|
377 |
|
|
impl_opt(Show_Register_Duplication)=0
|
378 |
|
|
impl_opt(Include_Function_In_Verilog_File)=1
|
379 |
|
|
impl_opt(Include_Simprim_Models_In_Verilog_File)=0
|
380 |
|
|
impl_opt(Show_Equivalent_Register_Removal)=1
|
381 |
|
|
impl_opt(run_design_rules_checker)=1
|
382 |
|
|
impl_opt(create_bit_file)=1
|
383 |
|
|
impl_opt(create_binary_config_file)=0
|
384 |
|
|
impl_opt(create_ascii_config_file)=0
|
385 |
|
|
impl_opt(create_ieee_1532_config_file_fpga)=0
|
386 |
|
|
impl_opt(enable_bitstream_compression)=1
|
387 |
|
|
impl_opt(enable_debugging_of_serial_mode_bitstream)=0
|
388 |
|
|
impl_opt(enable_cyclic_redundancy_checking)=1
|
389 |
|
|
impl_opt(other_bitgen_command_line_options)=
|
390 |
|
|
impl_opt(security)=Enable Readback and Reconfiguration
|
391 |
|
|
impl_opt(create_readback_data_files)=0
|
392 |
|
|
impl_opt(allow_selectmap_pins_to_persist)=0
|
393 |
|
|
impl_opt(create_logic_allocation_file)=0
|
394 |
|
|
impl_opt(create_mask_file)=0
|
395 |
|
|
impl_opt(encrypt_bitstream)=0
|
396 |
|
|
impl_opt(key_0)=
|
397 |
|
|
impl_opt(input_encryption_key_file)=
|
398 |
|
|
impl_opt(starting_cbc_value)=
|
399 |
|
|
impl_opt(fpga_start_up_clock)=CCLK
|
400 |
|
|
impl_opt(enable_internal_done_pipe)=0
|
401 |
|
|
impl_opt(done_output_events)=4
|
402 |
|
|
impl_opt(enable_outputs)=5
|
403 |
|
|
impl_opt(release_write_enable)=6
|
404 |
|
|
impl_opt(drive_done_pin_high)=1
|
405 |
|
|
impl_opt(configuration_rate)=2
|
406 |
|
|
impl_opt(configuration_pin_program)=Pull Up
|
407 |
|
|
impl_opt(configuration_pin_done)=Pull Up
|
408 |
|
|
impl_opt(jtag_pin_tck)=Pull Up
|
409 |
|
|
impl_opt(jtag_pin_tdi)=Pull Up
|
410 |
|
|
impl_opt(jtag_pin_tdo)=Pull Up
|
411 |
|
|
impl_opt(jtag_pin_tms)=Pull Up
|
412 |
|
|
impl_opt(unused_iob_pins)=Pull Up
|
413 |
|
|
impl_opt(userid_code)=0xFFFFFFFF
|
414 |
|
|
impl_opt(merge_netlists_before_insertion)=1
|
415 |
|
|
impl_opt(chipscope_bat_file_str)=
|
416 |
|
|
impl_opt(use_chipscope_bat_file)=0
|
417 |
|
|
impl_opt(Rename_Top_Level_Architecture_to)=Structure
|
418 |
|
|
impl_opt(Rename_Top_Level_Entity_to)=
|
419 |
|
|
impl_opt(Rename_Top_Level_Module_to)=
|
420 |
|
|
impl_opt(Combinatorial_Logic_Optimization)=1
|
421 |
|
|
impl_opt(Generate_Asynchronous_Delay_Report)=0
|
422 |
|
|
impl_opt(Generate_Clock_Region_Report)=0
|
423 |
|
|
impl_opt(Power_Reduction_Par)=0
|
424 |
|
|
impl_opt(Enable_Incremental_Design_Flow)=0
|
425 |
|
|
impl_opt(Run_Guided_Incremental_Design_Flow)=0
|
426 |
|
|
impl_opt(Report_Type)=Verbose report
|
427 |
|
|
impl_opt(Number_of_items_in_Error_Verbose_Report)=3
|
428 |
|
|
impl_opt(Perform_Advanced_Analysis)=0
|
429 |
|
|
impl_opt(Change_Device_Speed_To)=3
|
430 |
|
|
impl_opt(Report_Uncovered_Paths)=
|
431 |
|
|
impl_opt(Report_Fastest_Path_in_Each_Constraint)=1
|
432 |
|
|
impl_opt(post_map_file_str)=
|
433 |
|
|
impl_opt(use_post_map_file)=0
|
434 |
|
|
impl_opt(Report_Type2)=Error report
|
435 |
|
|
impl_opt(Number_of_items_in_Error_Verbose_Report2)=3
|
436 |
|
|
impl_opt(Perform_Advanced_Analysis2)=0
|
437 |
|
|
impl_opt(Change_Device_Speed_To2)=3
|
438 |
|
|
impl_opt(Report_Uncovered_Paths2)=
|
439 |
|
|
impl_opt(Report_Fastest_Path_in_Each_Constraint2)=1
|
440 |
|
|
impl_opt(Stamp_Timing_Model_Filename)=
|
441 |
|
|
impl_opt(Constraints_Interaction_Report_File2)=
|
442 |
|
|
impl_opt(dont_run_post_map_trace)=1
|
443 |
|
|
impl_opt(automatically_insert_glbl_module)=1
|
444 |
|
|
impl_opt(maximum_compression)=0
|
445 |
|
|
impl_opt(Output_Extended_Identifiers)=0
|
446 |
|
|
impl_opt(enable_suspend_wake_global_set_reset)=0
|
447 |
|
|
impl_opt(drive_awake_pin_during_suspend_wake_sequence)=0
|
448 |
|
|
impl_opt(wakeup_control)=Startup Clock
|
449 |
|
|
impl_opt(gwe_cycle_during_suspend_wakeup_sequence)=5
|
450 |
|
|
impl_opt(gts_cycle_during_suspend_wakeup_sequence)=4
|
451 |
|
|
impl_opt(ChipScope_Overwrite_Project_File)=0
|
452 |
|
|
impl_opt(insert_buffers_to_prevent_pulse_swallowing)=1
|
453 |
|
|
impl_opt(Report_Paths_By_Endpoint)=3
|
454 |
|
|
impl_opt(Generate_Datasheet_Section)=1
|
455 |
|
|
impl_opt(Generate_Timegroups_Section)=0
|
456 |
|
|
impl_opt(Constraints_Interaction_Report_File)=
|
457 |
|
|
impl_opt(Ignore_User_Timing_Constraints_Map)=0
|
458 |
|
|
impl_opt(Power_Activity_File_Map)=
|
459 |
|
|
impl_opt(Ignore_User_Timing_Constraints_Par)=0
|
460 |
|
|
impl_opt(Timing_Mode_Par)=Performance Evaluation
|
461 |
|
|
impl_opt(Power_Activity_File_Par)=
|
462 |
|
|
impl_opt(Report_Paths_By_Endpoint2)=3
|
463 |
|
|
impl_opt(Generate_Datasheet_Section2)=1
|
464 |
|
|
impl_opt(Generate_Timegroups_Section2)=0
|
465 |
|
|
impl_opt(retry_configuration_if_crc_error_occurs)=0
|
466 |
|
|
impl_opt(place_multiboot_settings_into_bitstream)=0
|
467 |
|
|
impl_opt(multiboot_starting_address_for_next_configuration)=0x00000000
|
468 |
|
|
impl_opt(multiboot_use_new_mode_for_next_configuration)=1
|
469 |
|
|
impl_opt(multiboot_next_configuration_mode)=001
|
470 |
|
|
impl_opt(Timing_Mode_Map_Virtex5)=Performance Evaluation
|
471 |
|
|
impl_opt(LUT_Combining)=Auto
|
472 |
|
|
impl_opt(Global_Optimization_Virtex5)=Off
|
473 |
|
|
impl_opt(Enable_Multi_Threading_Map)=Off
|
474 |
|
|
impl_opt(enable_external_master_clock)=0
|
475 |
|
|
impl_opt(setup_external_master_clock_division)=1
|
476 |
|
|
impl_opt(set_spi_configuration_bus_width)=1
|
477 |
|
|
impl_opt(multiboot_starting_address_for_golden_configuration)=0x00000000
|
478 |
|
|
impl_opt(multiboot_user_defined_register_for_failsafe_scheme)=0x0000
|
479 |
|
|
impl_opt(wait_for_dcm_and_pll_lock)=NoWait
|
480 |
|
|
impl_opt(enable_multi_pin_wake_up_suspend_mode)=0
|
481 |
|
|
impl_opt(mask_pins_for_multi_pin_wake_up_suspend_mode)=0x00
|
482 |
|
|
impl_opt(encrypt_key_select)=BBRAM
|
483 |
|
|
impl_opt(Watchdog_Timer_Value_Spartan6)=0xFFFF
|
484 |
|
|
impl_opt(Allow_Unmatched_Timing_Group_Constraints)=0
|
485 |
|
|
impl_opt(Extra_Cost_Tables)=0
|
486 |
|
|
impl_opt(Enable_Multi_Threading_Par)=Off
|
487 |
|
|
impl_opt(Power_Reduction_Map_Virtex6)=Off
|
488 |
|
|
impl_opt(Register_Ordering)=4
|
489 |
|
|
|
490 |
|
|
[PCB_INTERFACE]
|
491 |
|
|
FAMILY=
|
492 |
|
|
|
493 |
51 |
dsmv |
[Groups]
|
494 |
|
|
pcie_src=1
|
495 |
|
|
pcie_src\components=1
|
496 |
|
|
pcie_src\components\block_main=1
|
497 |
|
|
pcie_src\components\pcie_core=1
|
498 |
|
|
pcie_src\components\rtl=1
|
499 |
|
|
pcie_src\pcie_core64_m1=1
|
500 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl=1
|
501 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext=1
|
502 |
|
|
pcie_src\pcie_core64_m1\source=0
|
503 |
|
|
pcie_src\pcie_core64_m1\source_s6=1
|
504 |
|
|
pcie_src\pcie_core64_m1\source_virtex6=1
|
505 |
|
|
pcie_src\pcie_core64_m1\top=1
|
506 |
|
|
pcie_src\pcie_sim=1
|
507 |
|
|
pcie_src\pcie_sim\dsport=1
|
508 |
|
|
pcie_src\pcie_sim\sim=1
|
509 |
|
|
testbench=1
|
510 |
|
|
testbench\modelsim=1
|
511 |
|
|
testbench\modelsim\zz_do=1
|
512 |
|
|
testbench\modelsim\required_tests=1
|
513 |
|
|
testbench\modelsim\required_tests\test0=1
|
514 |
|
|
testbench\modelsim\required_tests\test0\zz_do=1
|
515 |
|
|
testbench\ahdl=1
|
516 |
|
|
testbench\log=1
|
517 |
|
|
top=1
|
518 |
|
|
wishbone=1
|
519 |
|
|
wishbone\block_test_check=1
|
520 |
|
|
wishbone\block_test_generate=1
|
521 |
|
|
wishbone\cross=1
|
522 |
|
|
wishbone\doc=1
|
523 |
|
|
wishbone\coregen=1
|
524 |
53 |
dsmv |
wishbone\testbecnh=0
|
525 |
51 |
dsmv |
wishbone\testbecnh\dev_pb_wishbone_ctrl=1
|
526 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim=1
|
527 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do=1
|
528 |
|
|
wishbone\testbecnh\dev_test_check=1
|
529 |
|
|
wishbone\testbecnh\dev_test_check\sim=1
|
530 |
|
|
wishbone\testbecnh\dev_test_check\sim\zz_do=1
|
531 |
|
|
wishbone\testbecnh\dev_test_gen=1
|
532 |
|
|
wishbone\testbecnh\dev_test_gen\sim=1
|
533 |
|
|
wishbone\testbecnh\dev_test_gen\sim\zz_do=1
|
534 |
|
|
wishbone\testbecnh\dev_wb_cross=1
|
535 |
|
|
wishbone\testbecnh\dev_wb_cross\sim=1
|
536 |
|
|
wishbone\testbecnh\dev_wb_cross\sim\zz_do=1
|
537 |
53 |
dsmv |
post-synthesis=0
|
538 |
51 |
dsmv |
DESIGN_STATUS=1
|
539 |
|
|
DESIGN_STATUS\2013_07_26_01_18=1
|
540 |
|
|
DESIGN_STATUS\2013_08_02_00_11=1
|
541 |
53 |
dsmv |
wishbone\doc\en=1
|
542 |
|
|
wishbone\doc\ru=1
|
543 |
|
|
pcie_src\components\coregen_s6=1
|
544 |
51 |
dsmv |
|
545 |
2 |
dsmv |
[Files]
|
546 |
|
|
pcie_src\components\block_main/block_pe_main.vhd=-1
|
547 |
|
|
pcie_src\components\pcie_core/pcie_core64_m2.vhd=-1
|
548 |
|
|
pcie_src\components\pcie_core/pcie_core64_m5.vhd=-1
|
549 |
|
|
pcie_src\components\pcie_core/pcie_core64_m7.vhd=-1
|
550 |
|
|
pcie_src\components\pcie_core/pcie_core64_wishbone.vhd=-1
|
551 |
38 |
dsmv |
pcie_src\components\pcie_core/pcie_core64_wishbone_m8.vhd=-1
|
552 |
2 |
dsmv |
pcie_src\components\rtl/host_pkg.vhd=-1
|
553 |
|
|
pcie_src\components\rtl/core64_pb_transaction.vhd=-1
|
554 |
|
|
pcie_src\components\rtl/ctrl_ram16_v1.vhd=-1
|
555 |
|
|
pcie_src\components\rtl/core64_pb_wishbone.vhd=-1
|
556 |
|
|
pcie_src\components\rtl/core64_pb_wishbone_ctrl.v=-1
|
557 |
53 |
dsmv |
pcie_src\components\coregen_s6/ctrl_fifo512x64st_v0.ngc=-1
|
558 |
|
|
pcie_src\components\coregen_s6/ctrl_fifo512x64st_v0.vhd=-1
|
559 |
|
|
pcie_src\components\coregen_s6/ctrl_fifo512x64st_v0.xco=-1
|
560 |
|
|
pcie_src\components\coregen_s6/ctrl_fifo64x34fw.ngc=-1
|
561 |
|
|
pcie_src\components\coregen_s6/ctrl_fifo64x34fw.vhd=-1
|
562 |
|
|
pcie_src\components\coregen_s6/ctrl_fifo64x34fw.xco=-1
|
563 |
|
|
pcie_src\components\coregen_s6/ctrl_fifo64x37st.ngc=-1
|
564 |
|
|
pcie_src\components\coregen_s6/ctrl_fifo64x37st.vhd=-1
|
565 |
|
|
pcie_src\components\coregen_s6/ctrl_fifo64x37st.xco=-1
|
566 |
2 |
dsmv |
pcie_src\pcie_core64_m1\pcie_ctrl/core64_type_pkg.vhd=-1
|
567 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_interrupt.vhd=-1
|
568 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_pb_disp.vhd=-1
|
569 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_reg_access.vhd=-1
|
570 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_rx_engine.vhd=-1
|
571 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_rx_engine_m2.vhd=-1
|
572 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_rx_engine_m4.vhd=-1
|
573 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_tx_engine.vhd=-1
|
574 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_tx_engine_m2.vhd=-1
|
575 |
|
|
pcie_src\pcie_core64_m1\pcie_ctrl/core64_tx_engine_m4.vhd=-1
|
576 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_dma_adr.vhd=-1
|
577 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_dma_ext_cmd.vhd=-1
|
578 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ext_descriptor.vhd=-1
|
579 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_main.vhd=-1
|
580 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ram_cmd_pb.vhd=-1
|
581 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ram_cmd.vhd=-1
|
582 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/ctrl_ext_ram.vhd=-1
|
583 |
|
|
pcie_src\pcie_core64_m1\pcie_fifo_ext/block_pe_fifo_ext.vhd=-1
|
584 |
|
|
pcie_src\pcie_core64_m1\source/bram_common.v=-1
|
585 |
|
|
pcie_src\pcie_core64_m1\source/cfg_wr_enable.v=-1
|
586 |
|
|
pcie_src\pcie_core64_m1\source/cmm_decoder.v=-1
|
587 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_cnt_en.v=-1
|
588 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_cnt_nfl_en.v=-1
|
589 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_cor.v=-1
|
590 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_cpl.v=-1
|
591 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_ftl.v=-1
|
592 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_nfl.v=-1
|
593 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_ram4x26.v=-1
|
594 |
|
|
pcie_src\pcie_core64_m1\source/cmm_errman_ram8x26.v=-1
|
595 |
|
|
pcie_src\pcie_core64_m1\source/cmm_intr.v=-1
|
596 |
|
|
pcie_src\pcie_core64_m1\source/ctrl_pcie_x8.v=-1
|
597 |
|
|
pcie_src\pcie_core64_m1\source/ctrl_pcie_x8.xco=-1
|
598 |
|
|
pcie_src\pcie_core64_m1\source/extend_clk.v=-1
|
599 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_cf.v=-1
|
600 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_cf_arb.v=-1
|
601 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_cf_err.v=-1
|
602 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_cf_mgmt.v=-1
|
603 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_cf_pwr.v=-1
|
604 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_if.v=-1
|
605 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll.v=-1
|
606 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll_arb.v=-1
|
607 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll_credit.v=-1
|
608 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll_oqbqfifo.v=-1
|
609 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll_tx.v=-1
|
610 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_ll_tx_arb.v=-1
|
611 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_plus_ll_rx.v=-1
|
612 |
|
|
pcie_src\pcie_core64_m1\source/pcie_blk_plus_ll_tx.v=-1
|
613 |
|
|
pcie_src\pcie_core64_m1\source/pcie_clocking.v=-1
|
614 |
|
|
pcie_src\pcie_core64_m1\source/pcie_ep.v=-1
|
615 |
|
|
pcie_src\pcie_core64_m1\source/pcie_gtx_wrapper.v=-1
|
616 |
|
|
pcie_src\pcie_core64_m1\source/pcie_gt_wrapper.v=-1
|
617 |
|
|
pcie_src\pcie_core64_m1\source/pcie_gt_wrapper_top.v=-1
|
618 |
|
|
pcie_src\pcie_core64_m1\source/pcie_mim_wrapper.v=-1
|
619 |
|
|
pcie_src\pcie_core64_m1\source/pcie_reset_logic.v=-1
|
620 |
|
|
pcie_src\pcie_core64_m1\source/pcie_soft_int.v=-1
|
621 |
|
|
pcie_src\pcie_core64_m1\source/pcie_top.v=-1
|
622 |
|
|
pcie_src\pcie_core64_m1\source/prod_fixes.v=-1
|
623 |
|
|
pcie_src\pcie_core64_m1\source/sync_fifo.v=-1
|
624 |
|
|
pcie_src\pcie_core64_m1\source/tlm_rx_data_snk.v=-1
|
625 |
|
|
pcie_src\pcie_core64_m1\source/tlm_rx_data_snk_bar.v=-1
|
626 |
|
|
pcie_src\pcie_core64_m1\source/tlm_rx_data_snk_mal.v=-1
|
627 |
|
|
pcie_src\pcie_core64_m1\source/tlm_rx_data_snk_pwr_mgmt.v=-1
|
628 |
|
|
pcie_src\pcie_core64_m1\source/tx_sync_gtp.v=-1
|
629 |
|
|
pcie_src\pcie_core64_m1\source/tx_sync_gtx.v=-1
|
630 |
|
|
pcie_src\pcie_core64_m1\source/use_newinterrupt.v=-1
|
631 |
|
|
pcie_src\pcie_core64_m1\source_s6/cl_s6pcie_m2.vhd=-1
|
632 |
|
|
pcie_src\pcie_core64_m1\source_s6/gtpa1_dual_wrapper.vhd=-1
|
633 |
|
|
pcie_src\pcie_core64_m1\source_s6/gtpa1_dual_wrapper_tile.vhd=-1
|
634 |
|
|
pcie_src\pcie_core64_m1\source_s6/pcie_brams_s6.vhd=-1
|
635 |
|
|
pcie_src\pcie_core64_m1\source_s6/pcie_bram_s6.vhd=-1
|
636 |
|
|
pcie_src\pcie_core64_m1\source_s6/pcie_bram_top_s6.vhd=-1
|
637 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_rx.vhd=-1
|
638 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_rx_null_gen.vhd=-1
|
639 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_rx_pipeline.vhd=-1
|
640 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_top.vhd=-1
|
641 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_tx.vhd=-1
|
642 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_tx_pipeline.vhd=-1
|
643 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/axi_basic_tx_thrtl_ctl.vhd=-1
|
644 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/cl_v6pcie_m1.vhd=-1
|
645 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/cl_v6pcie_x4.vhd=-1
|
646 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/cl_v6pcie_x4.xco=-1
|
647 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/gtx_drp_chanalign_fix_3752_v6.vhd=-1
|
648 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/gtx_rx_valid_filter_v6.vhd=-1
|
649 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/gtx_tx_sync_rate_v6.vhd=-1
|
650 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/gtx_wrapper_v6.vhd=-1
|
651 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_2_0_v6.vhd=-1
|
652 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_brams_v6.vhd=-1
|
653 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_bram_top_v6.vhd=-1
|
654 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_bram_v6.vhd=-1
|
655 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_clocking_v6.vhd=-1
|
656 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_gtx_v6.vhd=-1
|
657 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_pipe_lane_v6.vhd=-1
|
658 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_pipe_misc_v6.vhd=-1
|
659 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_pipe_v6.vhd=-1
|
660 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_reset_delay_v6.vhd=-1
|
661 |
|
|
pcie_src\pcie_core64_m1\source_virtex6/pcie_upconfig_fix_3451_v6.vhd=-1
|
662 |
|
|
pcie_src\pcie_core64_m1\top/pcie_core64_m1.vhd=-1
|
663 |
|
|
pcie_src\pcie_core64_m1\top/pcie_core64_m4.vhd=-1
|
664 |
|
|
pcie_src\pcie_core64_m1\top/pcie_core64_m6.vhd=-1
|
665 |
|
|
pcie_src\pcie_sim\dsport/glbl.v=-1
|
666 |
|
|
pcie_src\pcie_sim\dsport/pcie_2_0_rport_v6.vhd=-1
|
667 |
|
|
pcie_src\pcie_sim\dsport/pcie_2_0_v6_rp.vhd=-1
|
668 |
|
|
pcie_src\pcie_sim\dsport/pci_exp_usrapp_cfg.vhd=-1
|
669 |
|
|
pcie_src\pcie_sim\dsport/pci_exp_usrapp_pl.vhd=-1
|
670 |
|
|
pcie_src\pcie_sim\dsport/pci_exp_usrapp_rx_m2.vhd=-1
|
671 |
|
|
pcie_src\pcie_sim\dsport/pci_exp_usrapp_tx_m2.vhd=-1
|
672 |
|
|
pcie_src\pcie_sim\dsport/test_interface.vhd=-1
|
673 |
|
|
pcie_src\pcie_sim\dsport/xilinx_pcie_rport_m2.vhd=-1
|
674 |
|
|
pcie_src\pcie_sim\sim/block_pkg.vhd=-1
|
675 |
|
|
pcie_src\pcie_sim\sim/cmd_sim_pkg.vhd=-1
|
676 |
|
|
pcie_src\pcie_sim\sim/root_memory_pkg.vhd=-1
|
677 |
|
|
pcie_src\pcie_sim\sim/trd_pcie_pkg.vhd=-1
|
678 |
4 |
dsmv |
testbench/wb_block_pkg.vhd=-1
|
679 |
|
|
testbench/test_pkg.vhd=-1
|
680 |
2 |
dsmv |
testbench/stend_sp605_wishbone.vhd=-1
|
681 |
|
|
testbench\modelsim/delete.bat=-1
|
682 |
|
|
testbench\modelsim/start.bat=-1
|
683 |
|
|
testbench\modelsim/wave.do=-1
|
684 |
|
|
testbench\modelsim\zz_do/delete.do=-1
|
685 |
|
|
testbench\modelsim\zz_do/setup_sim.do=-1
|
686 |
|
|
testbench\modelsim\required_tests/SciTE.session=-1
|
687 |
|
|
testbench\modelsim\required_tests\test0/block_check_wb_burst_slave_0.v=-1
|
688 |
|
|
testbench\modelsim\required_tests\test0/delete.bat=-1
|
689 |
|
|
testbench\modelsim\required_tests\test0/read.me=-1
|
690 |
|
|
testbench\modelsim\required_tests\test0/start.bat=-1
|
691 |
|
|
testbench\modelsim\required_tests\test0/wave.do=-1
|
692 |
|
|
testbench\modelsim\required_tests\test0\zz_do/delete.do=-1
|
693 |
|
|
testbench\modelsim\required_tests\test0\zz_do/setup_sim.do=-1
|
694 |
4 |
dsmv |
testbench\ahdl/test_gen.awf=-1
|
695 |
|
|
testbench\ahdl/pb_wishbone.awf=-1
|
696 |
|
|
testbench\ahdl/rx.awf=-1
|
697 |
|
|
testbench\ahdl/tx.awf=-1
|
698 |
10 |
dsmv |
testbench\ahdl/run_ahdl.tcl=-1
|
699 |
38 |
dsmv |
testbench\log/console_test_adm_read_8kb.log=-1
|
700 |
|
|
testbench\log/console_test_dsc_incorrect.log=-1
|
701 |
|
|
testbench\log/console_test_read 4 kB.log=-1
|
702 |
|
|
testbench\log/console_test_read_4kB.log=-1
|
703 |
|
|
testbench\log/file_id_0.log=-1
|
704 |
|
|
testbench\log/file_id_1.log=-1
|
705 |
|
|
testbench\log/file_id_2.log=-1
|
706 |
|
|
testbench\log/global_tc_summary.log=-1
|
707 |
51 |
dsmv |
testbench\log/console_test_read_reg.log=-1
|
708 |
|
|
testbench\log/file_id_3.log=-1
|
709 |
2 |
dsmv |
top/sp605_lx45t_wishbone.ucf=-1
|
710 |
|
|
top/sp605_lx45t_wishbone_sopc_wb.vhd=-1
|
711 |
|
|
top/sp605_lx45t_wishbone.vhd=-1
|
712 |
|
|
wishbone\block_test_check/block_check_wb_pkg.vhd=-1
|
713 |
|
|
wishbone\block_test_check/block_check_wb_burst_slave.v=-1
|
714 |
|
|
wishbone\block_test_check/block_check_wb_config_slave.vhd=-1
|
715 |
|
|
wishbone\block_test_check/cl_test_check.vhd=-1
|
716 |
|
|
wishbone\block_test_check/block_test_check_wb.vhd=-1
|
717 |
|
|
wishbone\block_test_generate/block_generate_wb_burst_slave.v=-1
|
718 |
|
|
wishbone\block_test_generate/block_generate_wb_config_slave.vhd=-1
|
719 |
|
|
wishbone\block_test_generate/block_generate_wb_pkg.vhd=-1
|
720 |
|
|
wishbone\block_test_generate/cl_test_generate.vhd=-1
|
721 |
|
|
wishbone\block_test_generate/block_test_generate_wb.vhd=-1
|
722 |
|
|
wishbone\cross/read.me=-1
|
723 |
|
|
wishbone\cross/wb_conmax_arb.v=-1
|
724 |
|
|
wishbone\cross/wb_conmax_defines.v=-1
|
725 |
|
|
wishbone\cross/wb_conmax_master_if.v=-1
|
726 |
|
|
wishbone\cross/wb_conmax_msel.v=-1
|
727 |
|
|
wishbone\cross/wb_conmax_pri_dec.v=-1
|
728 |
|
|
wishbone\cross/wb_conmax_pri_enc.v=-1
|
729 |
|
|
wishbone\cross/wb_conmax_rf.v=-1
|
730 |
|
|
wishbone\cross/wb_conmax_slave_if.v=-1
|
731 |
|
|
wishbone\cross/wb_conmax_top.v=-1
|
732 |
|
|
wishbone\cross/wb_conmax_top_pkg.vhd=-1
|
733 |
53 |
dsmv |
wishbone\doc\en/block_test_check_en.htm=-1
|
734 |
|
|
wishbone\doc\en/block_test_generate_en.htm=-1
|
735 |
|
|
wishbone\doc\en/style.css=-1
|
736 |
|
|
wishbone\doc\en/wishbone_test_en.htm=-1
|
737 |
|
|
wishbone\doc\ru/block_test_check.htm=-1
|
738 |
|
|
wishbone\doc\ru/block_test_generate.htm=-1
|
739 |
|
|
wishbone\doc\ru/style.css=-1
|
740 |
|
|
wishbone\doc\ru/wishbonbe_test.htm=-1
|
741 |
2 |
dsmv |
wishbone\coregen/ctrl_fifo1024x64_st_v1.ngc=-1
|
742 |
|
|
wishbone\coregen/ctrl_fifo1024x64_st_v1.vhd=-1
|
743 |
|
|
wishbone\coregen/ctrl_fifo1024x64_st_v1.xco=-1
|
744 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl/SciTE.session=-1
|
745 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/delete.bat=-1
|
746 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/ds_dma_pb_if.v=-1
|
747 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/start.bat=-1
|
748 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/tb.v=-1
|
749 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/wave.do=-1
|
750 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/wb_simple_ram_slave_if.v=-1
|
751 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim/wb_slave_if.v=-1
|
752 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do/delete.do=-1
|
753 |
|
|
wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do/setup_sim.do=-1
|
754 |
|
|
wishbone\testbecnh\dev_test_check/SciTE.session=-1
|
755 |
|
|
wishbone\testbecnh\dev_test_check\sim/delete.bat=-1
|
756 |
|
|
wishbone\testbecnh\dev_test_check\sim/ds_dma_test_check_burst_master_if.v=-1
|
757 |
|
|
wishbone\testbecnh\dev_test_check\sim/ds_dma_test_check_burst_master_if.vPreview=-1
|
758 |
|
|
wishbone\testbecnh\dev_test_check\sim/start.bat=-1
|
759 |
|
|
wishbone\testbecnh\dev_test_check\sim/tb.v=-1
|
760 |
|
|
wishbone\testbecnh\dev_test_check\sim/wave.do=-1
|
761 |
|
|
wishbone\testbecnh\dev_test_check\sim\zz_do/delete.do=-1
|
762 |
|
|
wishbone\testbecnh\dev_test_check\sim\zz_do/setup_sim.do=-1
|
763 |
|
|
wishbone\testbecnh\dev_test_gen/SciTE.session=-1
|
764 |
|
|
wishbone\testbecnh\dev_test_gen\sim/delete.bat=-1
|
765 |
|
|
wishbone\testbecnh\dev_test_gen\sim/ds_dma_test_gen_burst_master_if.v=-1
|
766 |
|
|
wishbone\testbecnh\dev_test_gen\sim/start.bat=-1
|
767 |
|
|
wishbone\testbecnh\dev_test_gen\sim/tb.v=-1
|
768 |
|
|
wishbone\testbecnh\dev_test_gen\sim/wave.do=-1
|
769 |
|
|
wishbone\testbecnh\dev_test_gen\sim\zz_do/delete.do=-1
|
770 |
|
|
wishbone\testbecnh\dev_test_gen\sim\zz_do/setup_sim.do=-1
|
771 |
|
|
wishbone\testbecnh\dev_wb_cross/SciTE.session=-1
|
772 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/delete.bat=-1
|
773 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/start.bat=-1
|
774 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/tb.v=-1
|
775 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/wave.do=-1
|
776 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/wb_intf.sv=-1
|
777 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/wb_tb_simple_master.sv=-1
|
778 |
|
|
wishbone\testbecnh\dev_wb_cross\sim/wb_tb_simple_ram_slave.v=-1
|
779 |
|
|
wishbone\testbecnh\dev_wb_cross\sim\zz_do/delete.do=-1
|
780 |
|
|
wishbone\testbecnh\dev_wb_cross\sim\zz_do/setup_sim.do=-1
|
781 |
38 |
dsmv |
post-synthesis/..\..\synthesis\sp605_lx45t_wishbone.vhd=-1
|
782 |
|
|
DESIGN_STATUS\2013_07_26_01_18/ComputerInformation.txt=-1
|
783 |
|
|
DESIGN_STATUS\2013_07_26_01_18/DesignInformation.txt=-1
|
784 |
|
|
DESIGN_STATUS\2013_07_26_01_18/DesignFiles.txt=-1
|
785 |
|
|
DESIGN_STATUS\2013_07_26_01_18/LibrariesList.txt=-1
|
786 |
|
|
DESIGN_STATUS\2013_07_26_01_18/synthesis_synthesis.dfml=-1
|
787 |
|
|
DESIGN_STATUS\2013_07_26_01_18/implement_ver1_rev1_implementation.dfml=-1
|
788 |
51 |
dsmv |
DESIGN_STATUS\2013_08_02_00_11/ComputerInformation.txt=-1
|
789 |
|
|
DESIGN_STATUS\2013_08_02_00_11/DesignInformation.txt=-1
|
790 |
|
|
DESIGN_STATUS\2013_08_02_00_11/DesignFiles.txt=-1
|
791 |
|
|
DESIGN_STATUS\2013_08_02_00_11/LibrariesList.txt=-1
|
792 |
|
|
DESIGN_STATUS\2013_08_02_00_11/synthesis_synthesis.dfml=-1
|
793 |
|
|
DESIGN_STATUS\2013_08_02_00_11/implement_ver1_rev1_implementation.dfml=-1
|
794 |
2 |
dsmv |
|
795 |
|
|
[Files.Data]
|
796 |
|
|
.\src\pcie_src\components\block_main\block_pe_main.vhd=VHDL Source Code
|
797 |
|
|
.\src\pcie_src\components\pcie_core\pcie_core64_m2.vhd=VHDL Source Code
|
798 |
|
|
.\src\pcie_src\components\pcie_core\pcie_core64_m5.vhd=VHDL Source Code
|
799 |
|
|
.\src\pcie_src\components\pcie_core\pcie_core64_m7.vhd=VHDL Source Code
|
800 |
|
|
.\src\pcie_src\components\pcie_core\pcie_core64_wishbone.vhd=VHDL Source Code
|
801 |
38 |
dsmv |
.\src\pcie_src\components\pcie_core\pcie_core64_wishbone_m8.vhd=VHDL Source Code
|
802 |
2 |
dsmv |
.\src\pcie_src\components\rtl\host_pkg.vhd=VHDL Source Code
|
803 |
|
|
.\src\pcie_src\components\rtl\core64_pb_transaction.vhd=VHDL Source Code
|
804 |
|
|
.\src\pcie_src\components\rtl\ctrl_ram16_v1.vhd=VHDL Source Code
|
805 |
|
|
.\src\pcie_src\components\rtl\core64_pb_wishbone.vhd=VHDL Source Code
|
806 |
|
|
.\src\pcie_src\components\rtl\core64_pb_wishbone_ctrl.v=Verilog Source Code
|
807 |
53 |
dsmv |
.\src\pcie_src\components\coregen_s6\ctrl_fifo512x64st_v0.ngc=External File
|
808 |
|
|
.\src\pcie_src\components\coregen_s6\ctrl_fifo512x64st_v0.vhd=VHDL Source Code
|
809 |
|
|
.\src\pcie_src\components\coregen_s6\ctrl_fifo512x64st_v0.xco=External File
|
810 |
|
|
.\src\pcie_src\components\coregen_s6\ctrl_fifo64x34fw.ngc=External File
|
811 |
|
|
.\src\pcie_src\components\coregen_s6\ctrl_fifo64x34fw.vhd=VHDL Source Code
|
812 |
|
|
.\src\pcie_src\components\coregen_s6\ctrl_fifo64x34fw.xco=External File
|
813 |
|
|
.\src\pcie_src\components\coregen_s6\ctrl_fifo64x37st.ngc=External File
|
814 |
|
|
.\src\pcie_src\components\coregen_s6\ctrl_fifo64x37st.vhd=VHDL Source Code
|
815 |
|
|
.\src\pcie_src\components\coregen_s6\ctrl_fifo64x37st.xco=External File
|
816 |
2 |
dsmv |
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_type_pkg.vhd=VHDL Source Code
|
817 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_interrupt.vhd=VHDL Source Code
|
818 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_pb_disp.vhd=VHDL Source Code
|
819 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_reg_access.vhd=VHDL Source Code
|
820 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_rx_engine.vhd=VHDL Source Code
|
821 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_rx_engine_m2.vhd=VHDL Source Code
|
822 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_rx_engine_m4.vhd=VHDL Source Code
|
823 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_tx_engine.vhd=VHDL Source Code
|
824 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_tx_engine_m2.vhd=VHDL Source Code
|
825 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_ctrl\core64_tx_engine_m4.vhd=VHDL Source Code
|
826 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_dma_adr.vhd=VHDL Source Code
|
827 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_dma_ext_cmd.vhd=VHDL Source Code
|
828 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ext_descriptor.vhd=VHDL Source Code
|
829 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_main.vhd=VHDL Source Code
|
830 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ram_cmd_pb.vhd=VHDL Source Code
|
831 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ram_cmd.vhd=VHDL Source Code
|
832 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\ctrl_ext_ram.vhd=VHDL Source Code
|
833 |
|
|
.\src\pcie_src\pcie_core64_m1\pcie_fifo_ext\block_pe_fifo_ext.vhd=VHDL Source Code
|
834 |
|
|
.\src\pcie_src\pcie_core64_m1\source\bram_common.v=Verilog Source Code
|
835 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cfg_wr_enable.v=Verilog Source Code
|
836 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_decoder.v=Verilog Source Code
|
837 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cnt_en.v=Verilog Source Code
|
838 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cnt_nfl_en.v=Verilog Source Code
|
839 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cor.v=Verilog Source Code
|
840 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_cpl.v=Verilog Source Code
|
841 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_ftl.v=Verilog Source Code
|
842 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_nfl.v=Verilog Source Code
|
843 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_ram4x26.v=Verilog Source Code
|
844 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_errman_ram8x26.v=Verilog Source Code
|
845 |
|
|
.\src\pcie_src\pcie_core64_m1\source\cmm_intr.v=Verilog Source Code
|
846 |
|
|
.\src\pcie_src\pcie_core64_m1\source\ctrl_pcie_x8.v=Verilog Source Code
|
847 |
|
|
.\src\pcie_src\pcie_core64_m1\source\ctrl_pcie_x8.xco=External File
|
848 |
|
|
.\src\pcie_src\pcie_core64_m1\source\extend_clk.v=Verilog Source Code
|
849 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf.v=Verilog Source Code
|
850 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_arb.v=Verilog Source Code
|
851 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_err.v=Verilog Source Code
|
852 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_mgmt.v=Verilog Source Code
|
853 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_cf_pwr.v=Verilog Source Code
|
854 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_if.v=Verilog Source Code
|
855 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll.v=Verilog Source Code
|
856 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_arb.v=Verilog Source Code
|
857 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_credit.v=Verilog Source Code
|
858 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_oqbqfifo.v=Verilog Source Code
|
859 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_tx.v=Verilog Source Code
|
860 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_ll_tx_arb.v=Verilog Source Code
|
861 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_plus_ll_rx.v=Verilog Source Code
|
862 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_blk_plus_ll_tx.v=Verilog Source Code
|
863 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_clocking.v=Verilog Source Code
|
864 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_ep.v=Verilog Source Code
|
865 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_gtx_wrapper.v=Verilog Source Code
|
866 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_gt_wrapper.v=Verilog Source Code
|
867 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_gt_wrapper_top.v=Verilog Source Code
|
868 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_mim_wrapper.v=Verilog Source Code
|
869 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_reset_logic.v=Verilog Source Code
|
870 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_soft_int.v=Verilog Source Code
|
871 |
|
|
.\src\pcie_src\pcie_core64_m1\source\pcie_top.v=Verilog Source Code
|
872 |
|
|
.\src\pcie_src\pcie_core64_m1\source\prod_fixes.v=Verilog Source Code
|
873 |
|
|
.\src\pcie_src\pcie_core64_m1\source\sync_fifo.v=Verilog Source Code
|
874 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk.v=Verilog Source Code
|
875 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk_bar.v=Verilog Source Code
|
876 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk_mal.v=Verilog Source Code
|
877 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tlm_rx_data_snk_pwr_mgmt.v=Verilog Source Code
|
878 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tx_sync_gtp.v=Verilog Source Code
|
879 |
|
|
.\src\pcie_src\pcie_core64_m1\source\tx_sync_gtx.v=Verilog Source Code
|
880 |
|
|
.\src\pcie_src\pcie_core64_m1\source\use_newinterrupt.v=Verilog Source Code
|
881 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\cl_s6pcie_m2.vhd=VHDL Source Code
|
882 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\gtpa1_dual_wrapper.vhd=VHDL Source Code
|
883 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\gtpa1_dual_wrapper_tile.vhd=VHDL Source Code
|
884 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\pcie_brams_s6.vhd=VHDL Source Code
|
885 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\pcie_bram_s6.vhd=VHDL Source Code
|
886 |
|
|
.\src\pcie_src\pcie_core64_m1\source_s6\pcie_bram_top_s6.vhd=VHDL Source Code
|
887 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_rx.vhd=VHDL Source Code
|
888 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_rx_null_gen.vhd=VHDL Source Code
|
889 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_rx_pipeline.vhd=VHDL Source Code
|
890 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_top.vhd=VHDL Source Code
|
891 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_tx.vhd=VHDL Source Code
|
892 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_tx_pipeline.vhd=VHDL Source Code
|
893 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\axi_basic_tx_thrtl_ctl.vhd=VHDL Source Code
|
894 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\cl_v6pcie_m1.vhd=VHDL Source Code
|
895 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\cl_v6pcie_x4.vhd=VHDL Source Code
|
896 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\cl_v6pcie_x4.xco=External File
|
897 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_drp_chanalign_fix_3752_v6.vhd=VHDL Source Code
|
898 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_rx_valid_filter_v6.vhd=VHDL Source Code
|
899 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_tx_sync_rate_v6.vhd=VHDL Source Code
|
900 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\gtx_wrapper_v6.vhd=VHDL Source Code
|
901 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_2_0_v6.vhd=VHDL Source Code
|
902 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_brams_v6.vhd=VHDL Source Code
|
903 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_bram_top_v6.vhd=VHDL Source Code
|
904 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_bram_v6.vhd=VHDL Source Code
|
905 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_clocking_v6.vhd=VHDL Source Code
|
906 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_gtx_v6.vhd=VHDL Source Code
|
907 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_pipe_lane_v6.vhd=VHDL Source Code
|
908 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_pipe_misc_v6.vhd=VHDL Source Code
|
909 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_pipe_v6.vhd=VHDL Source Code
|
910 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_reset_delay_v6.vhd=VHDL Source Code
|
911 |
|
|
.\src\pcie_src\pcie_core64_m1\source_virtex6\pcie_upconfig_fix_3451_v6.vhd=VHDL Source Code
|
912 |
|
|
.\src\pcie_src\pcie_core64_m1\top\pcie_core64_m1.vhd=VHDL Source Code
|
913 |
|
|
.\src\pcie_src\pcie_core64_m1\top\pcie_core64_m4.vhd=VHDL Source Code
|
914 |
|
|
.\src\pcie_src\pcie_core64_m1\top\pcie_core64_m6.vhd=VHDL Source Code
|
915 |
|
|
.\src\pcie_src\pcie_sim\dsport\glbl.v=Verilog Source Code
|
916 |
|
|
.\src\pcie_src\pcie_sim\dsport\pcie_2_0_rport_v6.vhd=VHDL Source Code
|
917 |
|
|
.\src\pcie_src\pcie_sim\dsport\pcie_2_0_v6_rp.vhd=VHDL Source Code
|
918 |
|
|
.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_cfg.vhd=VHDL Source Code
|
919 |
|
|
.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_pl.vhd=VHDL Source Code
|
920 |
|
|
.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_rx_m2.vhd=VHDL Source Code
|
921 |
|
|
.\src\pcie_src\pcie_sim\dsport\pci_exp_usrapp_tx_m2.vhd=VHDL Source Code
|
922 |
|
|
.\src\pcie_src\pcie_sim\dsport\test_interface.vhd=VHDL Source Code
|
923 |
|
|
.\src\pcie_src\pcie_sim\dsport\xilinx_pcie_rport_m2.vhd=VHDL Source Code
|
924 |
|
|
.\src\pcie_src\pcie_sim\sim\block_pkg.vhd=VHDL Source Code
|
925 |
|
|
.\src\pcie_src\pcie_sim\sim\cmd_sim_pkg.vhd=VHDL Source Code
|
926 |
|
|
.\src\pcie_src\pcie_sim\sim\root_memory_pkg.vhd=VHDL Source Code
|
927 |
|
|
.\src\pcie_src\pcie_sim\sim\trd_pcie_pkg.vhd=VHDL Source Code
|
928 |
4 |
dsmv |
.\src\testbench\wb_block_pkg.vhd=VHDL Source Code
|
929 |
|
|
.\src\testbench\test_pkg.vhd=VHDL Source Code
|
930 |
2 |
dsmv |
.\src\testbench\stend_sp605_wishbone.vhd=VHDL Source Code
|
931 |
|
|
.\src\testbench\modelsim\delete.bat=External File
|
932 |
|
|
.\src\testbench\modelsim\start.bat=External File
|
933 |
|
|
.\src\testbench\modelsim\wave.do=Macro
|
934 |
|
|
.\src\testbench\modelsim\zz_do\delete.do=Macro
|
935 |
|
|
.\src\testbench\modelsim\zz_do\setup_sim.do=Macro
|
936 |
|
|
.\src\testbench\modelsim\required_tests\SciTE.session=External File
|
937 |
|
|
.\src\testbench\modelsim\required_tests\test0\block_check_wb_burst_slave_0.v=Verilog Source Code
|
938 |
|
|
.\src\testbench\modelsim\required_tests\test0\delete.bat=External File
|
939 |
|
|
.\src\testbench\modelsim\required_tests\test0\read.me=External File
|
940 |
|
|
.\src\testbench\modelsim\required_tests\test0\start.bat=External File
|
941 |
|
|
.\src\testbench\modelsim\required_tests\test0\wave.do=Macro
|
942 |
|
|
.\src\testbench\modelsim\required_tests\test0\zz_do\delete.do=Macro
|
943 |
|
|
.\src\testbench\modelsim\required_tests\test0\zz_do\setup_sim.do=Macro
|
944 |
4 |
dsmv |
.\src\testbench\ahdl\test_gen.awf=Waveform File
|
945 |
|
|
.\src\testbench\ahdl\pb_wishbone.awf=Waveform File
|
946 |
|
|
.\src\testbench\ahdl\rx.awf=Waveform File
|
947 |
|
|
.\src\testbench\ahdl\tx.awf=Waveform File
|
948 |
10 |
dsmv |
.\src\testbench\ahdl\run_ahdl.tcl=Tcl Script
|
949 |
38 |
dsmv |
.\src\testbench\log\console_test_adm_read_8kb.log=Text File
|
950 |
|
|
.\src\testbench\log\console_test_dsc_incorrect.log=Text File
|
951 |
|
|
.\src\testbench\log\console_test_read 4 kB.log=Text File
|
952 |
|
|
.\src\testbench\log\console_test_read_4kB.log=Text File
|
953 |
|
|
.\src\testbench\log\file_id_0.log=Text File
|
954 |
|
|
.\src\testbench\log\file_id_1.log=Text File
|
955 |
|
|
.\src\testbench\log\file_id_2.log=Text File
|
956 |
|
|
.\src\testbench\log\global_tc_summary.log=Text File
|
957 |
51 |
dsmv |
.\src\testbench\log\console_test_read_reg.log=Text File
|
958 |
|
|
.\src\testbench\log\file_id_3.log=Text File
|
959 |
2 |
dsmv |
.\src\top\sp605_lx45t_wishbone.ucf=External File
|
960 |
|
|
.\src\top\sp605_lx45t_wishbone_sopc_wb.vhd=VHDL Source Code
|
961 |
|
|
.\src\top\sp605_lx45t_wishbone.vhd=VHDL Source Code
|
962 |
|
|
.\src\wishbone\block_test_check\block_check_wb_pkg.vhd=VHDL Source Code
|
963 |
|
|
.\src\wishbone\block_test_check\block_check_wb_burst_slave.v=Verilog Source Code
|
964 |
|
|
.\src\wishbone\block_test_check\block_check_wb_config_slave.vhd=VHDL Source Code
|
965 |
|
|
.\src\wishbone\block_test_check\cl_test_check.vhd=VHDL Source Code
|
966 |
|
|
.\src\wishbone\block_test_check\block_test_check_wb.vhd=VHDL Source Code
|
967 |
|
|
.\src\wishbone\block_test_generate\block_generate_wb_burst_slave.v=Verilog Source Code
|
968 |
|
|
.\src\wishbone\block_test_generate\block_generate_wb_config_slave.vhd=VHDL Source Code
|
969 |
|
|
.\src\wishbone\block_test_generate\block_generate_wb_pkg.vhd=VHDL Source Code
|
970 |
|
|
.\src\wishbone\block_test_generate\cl_test_generate.vhd=VHDL Source Code
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971 |
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972 |
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.\src\wishbone\cross\read.me=External File
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973 |
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.\src\wishbone\cross\wb_conmax_arb.v=Verilog Source Code
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974 |
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.\src\wishbone\cross\wb_conmax_defines.v=Verilog Source Code
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975 |
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.\src\wishbone\cross\wb_conmax_master_if.v=Verilog Source Code
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976 |
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.\src\wishbone\cross\wb_conmax_msel.v=Verilog Source Code
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977 |
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.\src\wishbone\cross\wb_conmax_pri_dec.v=Verilog Source Code
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978 |
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.\src\wishbone\cross\wb_conmax_pri_enc.v=Verilog Source Code
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979 |
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.\src\wishbone\cross\wb_conmax_rf.v=Verilog Source Code
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980 |
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.\src\wishbone\cross\wb_conmax_slave_if.v=Verilog Source Code
|
981 |
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.\src\wishbone\cross\wb_conmax_top.v=Verilog Source Code
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982 |
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.\src\wishbone\cross\wb_conmax_top_pkg.vhd=VHDL Source Code
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983 |
53 |
dsmv |
.\src\wishbone\doc\en\block_test_check_en.htm=HTML Document
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984 |
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.\src\wishbone\doc\en\block_test_generate_en.htm=HTML Document
|
985 |
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.\src\wishbone\doc\en\style.css=External File
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986 |
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.\src\wishbone\doc\en\wishbone_test_en.htm=HTML Document
|
987 |
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.\src\wishbone\doc\ru\block_test_check.htm=HTML Document
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988 |
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.\src\wishbone\doc\ru\block_test_generate.htm=HTML Document
|
989 |
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.\src\wishbone\doc\ru\style.css=External File
|
990 |
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.\src\wishbone\doc\ru\wishbonbe_test.htm=HTML Document
|
991 |
2 |
dsmv |
.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.ngc=External File
|
992 |
|
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.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.vhd=VHDL Source Code
|
993 |
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.\src\wishbone\coregen\ctrl_fifo1024x64_st_v1.xco=External File
|
994 |
|
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.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\SciTE.session=External File
|
995 |
|
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.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\delete.bat=External File
|
996 |
|
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.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\ds_dma_pb_if.v=Verilog Source Code
|
997 |
|
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.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\start.bat=External File
|
998 |
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.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\tb.v=Verilog Source Code
|
999 |
|
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.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\wave.do=Macro
|
1000 |
|
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.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\wb_simple_ram_slave_if.v=Verilog Source Code
|
1001 |
|
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.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\wb_slave_if.v=Verilog Source Code
|
1002 |
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.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do\delete.do=Macro
|
1003 |
|
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.\src\wishbone\testbecnh\dev_pb_wishbone_ctrl\sim\zz_do\setup_sim.do=Macro
|
1004 |
|
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.\src\wishbone\testbecnh\dev_test_check\SciTE.session=External File
|
1005 |
|
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.\src\wishbone\testbecnh\dev_test_check\sim\delete.bat=External File
|
1006 |
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.\src\wishbone\testbecnh\dev_test_check\sim\ds_dma_test_check_burst_master_if.v=Verilog Source Code
|
1007 |
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.\src\wishbone\testbecnh\dev_test_check\sim\ds_dma_test_check_burst_master_if.vPreview=External File
|
1008 |
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.\src\wishbone\testbecnh\dev_test_check\sim\start.bat=External File
|
1009 |
|
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.\src\wishbone\testbecnh\dev_test_check\sim\tb.v=Verilog Source Code
|
1010 |
|
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.\src\wishbone\testbecnh\dev_test_check\sim\wave.do=Macro
|
1011 |
|
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.\src\wishbone\testbecnh\dev_test_check\sim\zz_do\delete.do=Macro
|
1012 |
|
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.\src\wishbone\testbecnh\dev_test_check\sim\zz_do\setup_sim.do=Macro
|
1013 |
|
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.\src\wishbone\testbecnh\dev_test_gen\SciTE.session=External File
|
1014 |
|
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.\src\wishbone\testbecnh\dev_test_gen\sim\delete.bat=External File
|
1015 |
|
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.\src\wishbone\testbecnh\dev_test_gen\sim\ds_dma_test_gen_burst_master_if.v=Verilog Source Code
|
1016 |
|
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.\src\wishbone\testbecnh\dev_test_gen\sim\start.bat=External File
|
1017 |
|
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.\src\wishbone\testbecnh\dev_test_gen\sim\tb.v=Verilog Source Code
|
1018 |
|
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.\src\wishbone\testbecnh\dev_test_gen\sim\wave.do=Macro
|
1019 |
|
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.\src\wishbone\testbecnh\dev_test_gen\sim\zz_do\delete.do=Macro
|
1020 |
|
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.\src\wishbone\testbecnh\dev_test_gen\sim\zz_do\setup_sim.do=Macro
|
1021 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\SciTE.session=External File
|
1022 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\delete.bat=External File
|
1023 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\start.bat=External File
|
1024 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\tb.v=Verilog Source Code
|
1025 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wave.do=Macro
|
1026 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_intf.sv=SystemVerilog Source Code
|
1027 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_master.sv=SystemVerilog Source Code
|
1028 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\wb_tb_simple_ram_slave.v=Verilog Source Code
|
1029 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\delete.do=Macro
|
1030 |
|
|
.\src\wishbone\testbecnh\dev_wb_cross\sim\zz_do\setup_sim.do=Macro
|
1031 |
38 |
dsmv |
.\synthesis\sp605_lx45t_wishbone.vhd=VHDL Source Code
|
1032 |
|
|
.\src\DESIGN_STATUS\2013_07_26_01_18\ComputerInformation.txt=Text File
|
1033 |
|
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.\src\DESIGN_STATUS\2013_07_26_01_18\DesignInformation.txt=Text File
|
1034 |
|
|
.\src\DESIGN_STATUS\2013_07_26_01_18\DesignFiles.txt=Text File
|
1035 |
|
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.\src\DESIGN_STATUS\2013_07_26_01_18\LibrariesList.txt=Text File
|
1036 |
|
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.\src\DESIGN_STATUS\2013_07_26_01_18\synthesis_synthesis.dfml=Text File
|
1037 |
|
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.\src\DESIGN_STATUS\2013_07_26_01_18\implement_ver1_rev1_implementation.dfml=Text File
|
1038 |
51 |
dsmv |
.\src\DESIGN_STATUS\2013_08_02_00_11\ComputerInformation.txt=Text File
|
1039 |
|
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.\src\DESIGN_STATUS\2013_08_02_00_11\DesignInformation.txt=Text File
|
1040 |
|
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.\src\DESIGN_STATUS\2013_08_02_00_11\DesignFiles.txt=Text File
|
1041 |
|
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.\src\DESIGN_STATUS\2013_08_02_00_11\LibrariesList.txt=Text File
|
1042 |
|
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.\src\DESIGN_STATUS\2013_08_02_00_11\synthesis_synthesis.dfml=Text File
|
1043 |
|
|
.\src\DESIGN_STATUS\2013_08_02_00_11\implement_ver1_rev1_implementation.dfml=Text File
|
1044 |
10 |
dsmv |
|
1045 |
53 |
dsmv |
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WindowVisible=0
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