Subversion Repositories pcie_ds_dma

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##-----------------------------------------------------------------------------

## Project    : Spartan-6 Integrated Block for PCI Express

## File       : xilinx_pcie_1_lane_ep_xc6slx150t-fgg676-2.ucf

## Description: Example User Constraints File

##

## Use this file only with the device listed below.  Any other

## combination is invalid.  Do not modify this file except in

## regions designated for "User" constraints.

##-----------------------------------------------------------------------------

###############################################################################

# Define Device, Package And Speed Grade

###############################################################################

#CONFIG PART = xc6slx150t-fgg676-2;

###############################################################################

# User Time Names / User Time Groups / Time Specs

###############################################################################

###############################################################################

# User Physical Constraints

###############################################################################

###############################################################################

# Pinout and Related I/O Constraints

###############################################################################

#

# SYS reset (input) signal.  The sys_reset_n signal should be

# obtained from the PCI Express interface if possible.  For

# slot based form factors, a system reset signal is usually

# present on the connector.  For cable based form factors, a

# system reset signal may not be available.  In this case, the

# system reset signal must be generated locally by some form of

# supervisory circuit.  You may change the IOSTANDARD and LOC

# to suit your requirements and VCCO voltage banking rules.

#

NET sys_reset_n      LOC = J7  | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY;

# SYS clock 100 or 125 MHz (input) signal. The sys_clk_p and sys_clk_n

# signals are the PCI Express reference clock. Spartan-6 GTP

# Transceiver architecture requires the use of dedicated clock

# resources (FPGA input pins) associated with each GTP Transceiver Tile.

# To use these pins an IBUFDS primitive (refclk_ibuf) is

# instantiated in the example design.

# Please refer to the Spartan-6 GTP Transceiver User Guide

# for guidelines regarding clock resource selection.

#

#NET  sys_clk_n       LOC = A10;

#NET  sys_clk_p       LOC = B10;

#

# Transceiver instance placement.  This constraint selects the

# transceiver to be used, which also dictates the pinout for the

# transmit and receive differential pairs.  Please refer to the

# Spartan-6 GTP Transceiver User Guide for more

# information.

#

# PCIe Lane 0

INST cl_s6pcie_m2_i/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i LOC = GTPA1_DUAL_X0Y1;

NET   pci_exp_txp<0>  LOC = B6;

NET   pci_exp_txn<0>  LOC = A6;

NET   pci_exp_rxp<0>  LOC = D7;

NET   pci_exp_rxn<0>  LOC = C7;

NET "gpio_led0" LOC = D17;

NET "gpio_led1" LOC = AB4;

NET "gpio_led2" LOC = D21;

NET "gpio_led3" LOC = W15;

###############################################################################

# Physical Constraints

###############################################################################

###############################################################################

# Timing Constraints

###############################################################################

#

# Ignore timing on asynchronous signals.

#

NET sys_reset_n TIG;

#

# Timing requirements and related constraints.

#

#NET sys_clk_c PERIOD = 8ns;

NET sys_clk_p TNM_NET = GT_REFCLK_OUT;

NET */ep/gt_refclk_out(0) TNM_NET = GT_REFCLK_OUT;

TIMESPEC TS_GT_REFCLK_OUT = PERIOD GT_REFCLK_OUT 8ns HIGH 50 % ;

NET "WB_SOPC/s_wb_clk" TNM_NET = WB_CLK;

TIMESPEC TS_WB_CLK = PERIOD WB_CLK 30 ns;

###############################################################################

# End

###############################################################################

 INST "WB_SOPC/PCIE_CORE64_WB/CORE/ep" AREA_GROUP = "pblock_ep";

AREA_GROUP "pblock_ep" RANGE=SLICE_X4Y96:SLICE_X7Y125;

AREA_GROUP "pblock_ep" RANGE=RAMB16_X0Y48:RAMB16_X0Y62;

AREA_GROUP "pblock_ep" RANGE=RAMB8_X0Y48:RAMB8_X0Y63;

INST "WB_SOPC/PCIE_CORE64_WB/CORE/rx" AREA_GROUP = "pblock_rx";

AREA_GROUP "pblock_rx" RANGE=SLICE_X8Y111:SLICE_X17Y88;

INST "WB_SOPC/PCIE_CORE64_WB/CORE/tx" AREA_GROUP = "pblock_tx";

AREA_GROUP "pblock_tx" RANGE=SLICE_X20Y88:SLICE_X29Y111;

INST "WB_SOPC/PCIE_CORE64_WB/CORE/reg" AREA_GROUP = "pblock_reg";

AREA_GROUP "pblock_reg" RANGE=SLICE_X18Y85:SLICE_X19Y95, SLICE_X12Y85:SLICE_X17Y87;

INST "WB_SOPC/PCIE_CORE64_WB/CORE/int" AREA_GROUP = "pblock_int";

AREA_GROUP "pblock_int" RANGE=SLICE_X0Y122:SLICE_X3Y125;

INST "WB_SOPC/PCIE_CORE64_WB/CORE/disp" AREA_GROUP = "pblock_disp";

AREA_GROUP "pblock_disp" RANGE=SLICE_X20Y87:SLICE_X29Y83;

INST "WB_SOPC/PCIE_CORE64_WB/CORE/fifo" AREA_GROUP = "pblock_fifo";

AREA_GROUP "pblock_fifo" RANGE=SLICE_X18Y72:SLICE_X29Y82, SLICE_X8Y72:SLICE_X17Y84, SLICE_X2Y72:SLICE_X7Y95;

AREA_GROUP "pblock_fifo" RANGE=RAMB16_X0Y36:RAMB16_X1Y46;

AREA_GROUP "pblock_fifo" RANGE=RAMB8_X0Y36:RAMB8_X1Y47;

INST "WB_SOPC/PCIE_CORE64_WB/PE_MAIN" AREA_GROUP = "pblock_PE_MAIN";

AREA_GROUP "pblock_PE_MAIN" RANGE=SLICE_X24Y119:SLICE_X29Y113;

INST "WB_SOPC/PCIE_CORE64_WB/PW_WB" AREA_GROUP = "pblock_PW_WB";

AREA_GROUP "pblock_PW_WB" RANGE=SLICE_X4Y68:SLICE_X21Y71;

INST "WB_SOPC/WB_CROSS" AREA_GROUP = "pblock_WB_CROSS";

AREA_GROUP "pblock_WB_CROSS" RANGE=SLICE_X4Y56:SLICE_X21Y67;

INST "WB_SOPC/TEST_CHECK" AREA_GROUP = "pblock_TEST_CHECK";

AREA_GROUP "pblock_TEST_CHECK" RANGE=SLICE_X4Y24:SLICE_X17Y55;

AREA_GROUP "pblock_TEST_CHECK" RANGE=RAMB16_X0Y12:RAMB16_X0Y26;

AREA_GROUP "pblock_TEST_CHECK" RANGE=RAMB8_X0Y12:RAMB8_X0Y27;

INST "WB_SOPC/TEST_GEN" AREA_GROUP = "pblock_TEST_GEN";

AREA_GROUP "pblock_TEST_GEN" RANGE=SLICE_X18Y24:SLICE_X27Y55;

AREA_GROUP "pblock_TEST_GEN" RANGE=RAMB16_X1Y12:RAMB16_X1Y26;

AREA_GROUP "pblock_TEST_GEN" RANGE=RAMB8_X1Y12:RAMB8_X1Y27;