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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MySource/] [DDR_Blinker.vhd] - Blame information for rev 13

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1 13 barabba 
----------------------------------------------------------------------------------
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-- Company:  ZITI
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-- Engineer:  wgao
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--
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-- Create Date:    16:38:03 06 Oct 2008
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-- Design Name:
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-- Module Name:    DDR_Blink - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library work;
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use work.abb64Package.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity DDR_Blink is
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    Port (
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           DDR_blinker              : OUT   std_logic;
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           DDR_Write                : IN    std_logic;
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           DDR_Read                 : IN    std_logic;
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           DDR_Both                 : IN    std_logic;
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           ddr_Clock                : IN    std_logic;
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           DDr_Rst_n                : IN    std_logic
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          );
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end entity DDR_Blink;
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architecture Behavioral of DDR_Blink is
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  -- Blinking -_-_-_-_
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  Constant  C_BLINKER_MSB       : integer      :=   15;  -- 4;  -- 15;
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  Constant  CBIT_SLOW_BLINKER   : integer      :=   11;  -- 2;  -- 11;
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  signal  DDR_blinker_i         :  std_logic;
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  signal  Fast_blinker          :  std_logic_vector(C_BLINKER_MSB downto 0);
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  signal  Fast_blinker_MSB_r1   :  std_logic;
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  signal  Blink_Pulse           :  std_logic;
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  signal  Slow_blinker          :  std_logic_vector(CBIT_SLOW_BLINKER downto 0);
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  signal  DDR_write_extension    :  std_logic;
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  signal  DDR_write_extension_Cnt:  std_logic_vector(1 downto 0);
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  signal  DDR_read_extension     :  std_logic;
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  signal  DDR_read_extension_Cnt :  std_logic_vector(1 downto 0);
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begin
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   --
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   Syn_DDR_Fast_blinker:
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   process ( ddr_Clock, DDr_Rst_n)
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   begin
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      if DDr_Rst_n = '0' then
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         Fast_blinker        <= (OTHERS=>'0');
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         Fast_blinker_MSB_r1 <= '0';
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         Blink_Pulse         <= '0';
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         Slow_blinker        <= (OTHERS=>'0');
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      elsif ddr_Clock'event and ddr_Clock = '1' then
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         Fast_blinker        <= Fast_blinker + '1';
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         Fast_blinker_MSB_r1 <= Fast_blinker(C_BLINKER_MSB);
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         Blink_Pulse         <= Fast_blinker(C_BLINKER_MSB) and not Fast_blinker_MSB_r1;
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         Slow_blinker        <= Slow_blinker + Blink_Pulse;
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      end if;
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   end process;
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   --
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   Syn_DDR_Write_Extenstion:
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   process ( ddr_Clock, DDr_Rst_n)
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   begin
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      if DDr_Rst_n = '0' then
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         DDR_write_extension_Cnt <= (OTHERS=>'0');
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         DDR_write_extension     <= '0';
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      elsif ddr_Clock'event and ddr_Clock = '1' then
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         case DDR_write_extension_Cnt is
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           when "00"   =>
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             if DDR_Write='1' then
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                DDR_write_extension_Cnt <= "01";
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                DDR_write_extension     <= '1';
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             else
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                DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
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                DDR_write_extension     <= DDR_write_extension;
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             end if;
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           when "01"   =>
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             if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
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                DDR_write_extension_Cnt <= "11";
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                DDR_write_extension     <= '1';
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             else
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                DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
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                DDR_write_extension     <= DDR_write_extension;
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             end if;
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           when "11"   =>
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             if Slow_blinker(CBIT_SLOW_BLINKER)='0' then
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                DDR_write_extension_Cnt <= "10";
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                DDR_write_extension     <= '1';
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             else
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                DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
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                DDR_write_extension     <= DDR_write_extension;
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             end if;
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           when Others          =>
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             if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
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                DDR_write_extension_Cnt <= "00";
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                DDR_write_extension     <= '0';
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             else
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                DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
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                DDR_write_extension     <= DDR_write_extension;
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             end if;
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139 
         end case;
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141 
      end if;
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   end process;
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   --
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   Syn_DDR_Read_Extenstion:
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   process ( ddr_Clock, DDr_Rst_n)
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   begin
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      if DDr_Rst_n = '0' then
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         DDR_read_extension_Cnt <= (OTHERS=>'0');
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         DDR_read_extension     <= '1';
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      elsif ddr_Clock'event and ddr_Clock = '1' then
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         case DDR_read_extension_Cnt is
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           when "00"   =>
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             if DDR_Read='1' then
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                DDR_read_extension_Cnt <= "01";
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                DDR_read_extension     <= '0';
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             else
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                DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
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                DDR_read_extension     <= DDR_read_extension;
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             end if;
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           when "01"   =>
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             if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
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                DDR_read_extension_Cnt <= "11";
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                DDR_read_extension     <= '0';
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             else
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                DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
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                DDR_read_extension     <= DDR_read_extension;
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             end if;
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175 
           when "11"   =>
176 
             if Slow_blinker(CBIT_SLOW_BLINKER)='0' then
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                DDR_read_extension_Cnt <= "10";
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                DDR_read_extension     <= '0';
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             else
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                DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
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                DDR_read_extension     <= DDR_read_extension;
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             end if;
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184 
           when Others          =>
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             if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
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                DDR_read_extension_Cnt <= "00";
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                DDR_read_extension     <= '1';
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             else
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                DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
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                DDR_read_extension     <= DDR_read_extension;
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             end if;
192 
 
193 
         end case;
194 
 
195 
      end if;
196 
   end process;
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198 
 
199 
   --
200 
   Syn_DDR_Working_blinker:
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   process ( ddr_Clock, DDr_Rst_n)
202 
   begin
203 
      if DDr_Rst_n = '0' then
204 
         DDR_Blinker_i      <= '0';
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206 
      elsif ddr_Clock'event and ddr_Clock = '1' then
207 
 
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         DDR_Blinker_i      <= (Slow_blinker(CBIT_SLOW_BLINKER-2) or DDR_write_extension) and DDR_read_extension;
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--         DDR_Blinker_i      <= Slow_blinker(CBIT_SLOW_BLINKER-2);
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211 
      end if;
212 
   end process;
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   DDR_blinker    <=  DDR_blinker_i;
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end architecture Behavioral;

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