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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MySource/] [bram_DDRs_Control.vhd] - Blame information for rev 13

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1 13 barabba 
----------------------------------------------------------------------------------
2 
-- Company:  ZITI
3 
-- Engineer:  wgao
4 
--
5 
-- Create Date:    12:29:46 04/15/2008
6 
-- Design Name:
7 
-- Module Name:    bram_DDRs_Control - Behavioral
8 
-- Project Name:
9 
-- Target Devices:
10 
-- Tool versions:
11 
-- Description:
12 
--
13 
-- Dependencies:
14 
--
15 
-- Revision:
16 
-- Revision 0.01 - File Created
17 
-- Additional Comments:
18 
--
19 
----------------------------------------------------------------------------------
20 
library IEEE;
21 
use IEEE.STD_LOGIC_1164.ALL;
22 
use IEEE.STD_LOGIC_ARITH.ALL;
23 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 
 
25 
library work;
26 
use work.abb64Package.all;
27 
 
28 
---- Uncomment the following library declaration if instantiating
29 
---- any Xilinx primitives in this code.
30 
--library UNISIM;
31 
--use UNISIM.VComponents.all;
32 
 
33 
entity bram_DDRs_Control is
34 
    Generic (
35 
             C_ASYNFIFO_WIDTH  :  integer  :=  72 ;
36 
             P_SIMULATION      :  boolean  :=  TRUE
37 
            );
38 
    Port (
39 
 
40 
--           -- Pins
41 
--           DDR_CLKn                 : OUT   std_logic;
42 
--           DDR_CLK                  : OUT   std_logic;
43 
--           DDR_CKE                  : OUT   std_logic;
44 
--           DDR_CSn                  : OUT   std_logic;
45 
--           DDR_RASn                 : OUT   std_logic;
46 
--           DDR_CASn                 : OUT   std_logic;
47 
--           DDR_WEn                  : OUT   std_logic;
48 
--           DDR_BankAddr             : OUT   std_logic_vector(C_DDR_BANK_AWIDTH-1 downto 0);
49 
--           DDR_Addr                 : OUT   std_logic_vector(C_DDR_AWIDTH-1 downto 0);
50 
--           DDR_DM                   : OUT   std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
51 
--           DDR_DQ                   : INOUT std_logic_vector(C_DDR_DWIDTH-1 downto 0);
52 
--           DDR_DQS                  : INOUT std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
53 
 
54 
                          --USER Logic Interface
55 
                          user_wr_weA              : IN    std_logic_vector(7 downto 0);
56 
                          user_wr_addrA            : IN    std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
57 
                          user_wr_dinA             : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
58 
                          user_rd_addrB            : IN    std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
59 
                          user_rd_doutB            : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
60 
                          user_rd_clk              : IN    std_logic;
61 
                          user_wr_clk              : IN    std_logic;
62 
 
63 
           -- DMA interface
64 
           DDR_wr_sof               : IN    std_logic;
65 
           DDR_wr_eof               : IN    std_logic;
66 
           DDR_wr_v                 : IN    std_logic;
67 
           DDR_wr_FA                : IN    std_logic;
68 
           DDR_wr_Shift             : IN    std_logic;
69 
           DDR_wr_Mask              : IN    std_logic_vector(2-1 downto 0);
70 
           DDR_wr_din               : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
71 
           DDR_wr_full              : OUT   std_logic;
72 
 
73 
           DDR_rdc_sof              : IN    std_logic;
74 
           DDR_rdc_eof              : IN    std_logic;
75 
           DDR_rdc_v                : IN    std_logic;
76 
           DDR_rdc_FA               : IN    std_logic;
77 
           DDR_rdc_Shift            : IN    std_logic;
78 
           DDR_rdc_din              : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
79 
           DDR_rdc_full             : OUT   std_logic;
80 
 
81 
--           DDR_rdD_sof              : OUT   std_logic;
82 
--           DDR_rdD_eof              : OUT   std_logic;
83 
--           DDR_rdDout_V             : OUT   std_logic;
84 
--           DDR_rdDout               : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
85 
 
86 
           -- DDR payload FIFO Read Port
87 
           DDR_FIFO_RdEn            : IN    std_logic;
88 
           DDR_FIFO_Empty           : OUT   std_logic;
89 
           DDR_FIFO_RdQout          : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
90 
 
91 
           -- Common interface
92 
           DDR_Ready                : OUT   std_logic;
93 
           DDR_blinker              : OUT   std_logic;
94 
           Sim_Zeichen              : OUT   std_logic;
95 
 
96 
           mem_clk                  : IN    std_logic;
97 
           trn_clk                  : IN    std_logic;
98 
           trn_reset_n              : IN    std_logic
99 
          );
100 
end entity bram_DDRs_Control;
101 
 
102 
 
103 
architecture Behavioral of bram_DDRs_Control is
104 
 
105 
  -- ----------------------------------------------------------------------------
106 
  --
107 
  -- ----------------------------------------------------------------------------
108 
  COMPONENT DDR_ClkGen
109 
    PORT(
110 
         ddr_Clock              : OUT   std_logic;
111 
         ddr_Clock_n            : OUT   std_logic;
112 
         ddr_Clock90            : OUT   std_logic;
113 
         ddr_Clock90_n          : OUT   std_logic;
114 
         Clk_ddr_rddata         : OUT   std_logic;
115 
         Clk_ddr_rddata_n       : OUT   std_logic;
116 
 
117 
         ddr_DCM_locked         : OUT   std_logic;
118 
 
119 
         clk_in                 : IN    std_logic;
120 
         trn_reset_n            : IN    std_logic
121 
        );
122 
  END COMPONENT;
123 
 
124 
 
125 
  -- ----------------------------------------------------------------------------
126 
  --
127 
  -- ----------------------------------------------------------------------------
128 
 
129 
  COMPONENT asyn_rw_FIFO72
130 
--    GENERIC (
131 
--             OUTPUT_REGISTERED  : BOOLEAN
132 
--            );
133 
    PORT(
134 
        wClk                    : IN     std_logic;
135 
        wEn                     : IN     std_logic;
136 
        Din                     : IN     std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
137 
        aFull                   : OUT    std_logic;
138 
        Full                    : OUT    std_logic;
139 
 
140 
        rClk                    : IN     std_logic;
141 
        rEn                     : IN     std_logic;
142 
        Qout                    : OUT    std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
143 
        aEmpty                  : OUT    std_logic;
144 
        Empty                   : OUT    std_logic;
145 
 
146 
        Rst                     : IN     std_logic
147 
        );
148 
  END COMPONENT;
149 
 
150 
 
151 
  component v6_prime_FIFO_plain
152 
      port (
153 
      wr_clk   : IN  std_logic;
154 
      wr_en    : IN  std_logic;
155 
      din      : IN  std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
156 
      full     : OUT std_logic;
157 
      prog_full: OUT std_logic;
158 
      rd_clk   : IN  std_logic;
159 
      rd_en    : IN  std_logic;
160 
      dout     : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
161 
      empty    : OUT std_logic;
162 
      rst      : IN  std_logic
163 
      );
164 
  end component;
165 
 
166 
--  component fifo_512x36_v4_2
167 
--    port (
168 
--    wr_clk      : IN  std_logic;
169 
--    wr_en       : IN  std_logic;
170 
--    din         : IN  std_logic_VECTOR(35 downto 0);
171 
--    prog_full   : OUT std_logic;
172 
--    full        : OUT std_logic;
173 
--
174 
--    rd_clk      : IN  std_logic;
175 
--    rd_en       : IN  std_logic;
176 
--    dout        : OUT std_logic_VECTOR(35 downto 0);
177 
--    prog_empty  : OUT std_logic;
178 
--    empty       : OUT std_logic;
179 
--
180 
--    rst         : IN  std_logic
181 
--    );
182 
--  end component;
183 
 
184 
  component fifo_512x72_v4_4
185 
    port (
186 
    wr_clk      : IN  std_logic;
187 
    wr_en       : IN  std_logic;
188 
    din         : IN  std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
189 
    prog_full   : OUT std_logic;
190 
    full        : OUT std_logic;
191 
 
192 
    rd_clk      : IN  std_logic;
193 
    rd_en       : IN  std_logic;
194 
    dout        : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
195 
--    prog_empty  : OUT std_logic;
196 
    empty       : OUT std_logic;
197 
 
198 
    rst         : IN  std_logic
199 
    );
200 
  end component;
201 
 
202 
 
203 
  ---- Dual-port block RAM for packets
204 
  ---    Core output registered
205 
  --
206 
--  component v5bram4096x32
207 
--    port (
208 
--      clka           : IN  std_logic;
209 
--      addra          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
210 
--      wea            : IN  std_logic_vector(0 downto 0);
211 
--      dina           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
212 
--      douta          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
213 
--
214 
--      clkb           : IN  std_logic;
215 
--      addrb          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
216 
--      web            : IN  std_logic_vector(0 downto 0);
217 
--      dinb           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
218 
--      doutb          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
219 
--    );
220 
--  end component;
221 
 
222 
--SIMONE DEBUG
223 
--component pcie_userlogic_02_cw
224 
--  port (
225 
--    addra: in std_logic_vector(11 downto 0);
226 
--    addrb: in std_logic_vector(11 downto 0);
227 
--    ce: in std_logic := '1';
228 
--    clk: in std_logic; -- clock period = 5.0 ns (200.0 Mhz)
229 
--    dina: in std_logic_vector(63 downto 0);
230 
--    dinb: in std_logic_vector(63 downto 0);
231 
--    douta: in std_logic_vector(63 downto 0);
232 
--    doutb: in std_logic_vector(63 downto 0);
233 
--    rst_i: in std_logic;
234 
--    wea: in std_logic_vector(7 downto 0);
235 
--    web: in std_logic_vector(7 downto 0);
236 
--    rst_o: out std_logic
237 
--  );
238 
--end component;
239 
 
240 
 
241 
  component v6_bram4096x64
242 
    port (
243 
      clka           : IN  std_logic;
244 
      addra          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
245 
      wea            : IN  std_logic_vector(7 downto 0);
246 
      dina           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
247 
      douta          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
248 
 
249 
      clkb           : IN  std_logic;
250 
      addrb          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
251 
      web            : IN  std_logic_vector(7 downto 0);
252 
      dinb           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
253 
      doutb          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
254 
    );
255 
  end component;
256 
 
257 
  -- Blinking  -_-_-_-_-_-_-_-_-_-_-_-_-_-_-
258 
  COMPONENT DDR_Blink
259 
    PORT(
260 
           DDR_Blinker              : OUT   std_logic;
261 
 
262 
           DDR_Write                : IN    std_logic;
263 
           DDR_Read                 : IN    std_logic;
264 
           DDR_Both                 : IN    std_logic;
265 
 
266 
           ddr_Clock                : IN    std_logic;
267 
           DDr_Rst_n                : IN    std_logic
268 
          );
269 
  END COMPONENT;
270 
 
271 
  -- ---------------------------------------------------------------------
272 
  signal  ddr_DCM_locked        :  std_logic;
273 
  --  -- ---------------------------------------------------------------------
274 
  signal  Rst_i                 :  std_logic;
275 
  --  -- ---------------------------------------------------------------------
276 
  signal  DDR_Ready_i           :  std_logic;
277 
  --  -- ---------------------------------------------------------------------
278 
  signal  ddr_Clock             :  std_logic;
279 
  signal  ddr_Clock_n           :  std_logic;
280 
  signal  ddr_Clock90           :  std_logic;
281 
  signal  ddr_Clock90_n         :  std_logic;
282 
 
283 
  signal  Clk_ddr_rddata        :  std_logic;
284 
  signal  Clk_ddr_rddata_n      :  std_logic;
285 
 
286 
  -- -- --  Write Pipe Channel
287 
  signal  wpipe_wEn             :  std_logic;
288 
  signal  wpipe_Din             :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
289 
  signal  wpipe_aFull           :  std_logic;
290 
  signal  wpipe_Full            :  std_logic;
291 
  --  Earlier calculate for better timing
292 
  signal  DDR_wr_Cross_Row      :  std_logic;
293 
  signal  DDR_wr_din_r1         :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
294 
  signal  DDR_write_ALC         :  std_logic_vector(11-1 downto 0);
295 
 
296 
  signal  wpipe_rEn             :  std_logic;
297 
  signal  wpipe_Qout            :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
298 
--  signal  wpipe_aEmpty          :  std_logic;
299 
  signal  wpipe_Empty           :  std_logic;
300 
  signal  wpipe_Qout_latch      :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
301 
 
302 
  -- -- --  Read Pipe Command Channel
303 
  signal  rpipec_wEn            :  std_logic;
304 
  signal  rpipec_Din            :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
305 
  signal  rpipec_aFull          :  std_logic;
306 
  signal  rpipec_Full           :  std_logic;
307 
  --  Earlier calculate for better timing
308 
  signal  DDR_rd_Cross_Row      :  std_logic;
309 
  signal  DDR_rdc_din_r1        :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
310 
  signal  DDR_read_ALC          :  std_logic_vector(11-1 downto 0);
311 
 
312 
  signal  rpipec_rEn            :  std_logic;
313 
  signal  rpipec_Qout           :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
314 
--  signal  rpipec_aEmpty         :  std_logic;
315 
  signal  rpipec_Empty          :  std_logic;
316 
 
317 
  -- -- --  Read Pipe Data Channel
318 
  signal  rpiped_wEn            :  std_logic;
319 
  signal  rpiped_Din            :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
320 
  signal  rpiped_aFull          :  std_logic;
321 
  signal  rpiped_Full           :  std_logic;
322 
 
323 
--  signal  rpiped_rEn            :  std_logic;
324 
  signal  rpiped_Qout           :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
325 
--  signal  rpiped_aEmpty         :  std_logic;
326 
--  signal  rpiped_Empty          :  std_logic;
327 
 
328 
 
329 
  --   write State machine
330 
  type bram_wrStates is          ( wrST_bram_RESET
331 
                                 , wrST_bram_IDLE
332 
--                                 , wrST_bram_Address
333 
                                 , wrST_bram_1st_Data
334 
                                 , wrST_bram_1st_Data_b2b
335 
                                 , wrST_bram_more_Data
336 
                                 , wrST_bram_last_DW
337 
                                 );
338 
 
339 
  -- State variables
340 
  signal pseudo_DDR_wr_State     : bram_wrStates;
341 
 
342 
  --       Block RAM
343 
  signal   pRAM_weA              : std_logic_vector(7 downto 0);
344 
  signal   pRAM_addrA            : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
345 
  signal   pRAM_dinA             : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
346 
  signal   pRAM_doutA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
347 
 
348 
  signal   user_wr_doutA         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
349 
  signal   user_rd_weB           : std_logic_vector(7 downto 0);
350 
  signal   user_rd_dinB          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
351 
 
352 
 
353 
  signal   pRAM_weB              : std_logic_vector(7 downto 0);
354 
  signal   pRAM_dinB             : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
355 
  signal   pRAM_addrB            : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
356 
  signal   pRAM_doutB            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
357 
  signal   pRAM_doutB_r1         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
358 
  signal   pRAM_doutB_shifted    : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
359 
 
360 
  signal   wpipe_qout_lo32b      : std_logic_vector(33-1 downto 0);
361 
  signal   wpipe_QW_Aligned      : std_logic;
362 
  signal   pRAM_AddrA_Inc        : std_logic;
363 
  signal   wpipe_read_valid      : std_logic;
364 
 
365 
 
366 
  --   read State machine
367 
  type bram_rdStates is          ( rdST_bram_RESET
368 
                                 , rdST_bram_IDLE
369 
                                 , rdST_bram_b4_LA
370 
                                 , rdST_bram_LA
371 
--                                 , rdST_bram_b4_Length
372 
--                                 , rdST_bram_Length
373 
--                                 , rdST_bram_b4_Address
374 
--                                 , rdST_bram_Address
375 
                                 , rdST_bram_Data
376 
--                                 , rdST_bram_Data_shift
377 
                                 );
378 
 
379 
  -- State variables
380 
  signal pseudo_DDR_rd_State     : bram_rdStates;
381 
 
382 
  signal rpiped_rd_counter       : std_logic_vector(10-1 downto 0);
383 
  signal rpiped_wEn_b3           : std_logic;
384 
  signal rpiped_wEn_b2           : std_logic;
385 
  signal rpiped_wEn_b1           : std_logic;
386 
  signal rpiped_wr_EOF           : std_logic;
387 
  signal rpipec_read_valid       : std_logic;
388 
  signal rpiped_wr_skew          : std_logic;
389 
  signal rpiped_wr_postpone      : std_logic;
390 
 
391 
  signal simone_debug : std_logic;
392 
 
393 
begin
394 
 
395 
 
396 
  Rst_i              <=  not trn_reset_n;
397 
  DDR_Ready          <=  DDR_Ready_i;
398 
 
399 
  pRAM_doutB_shifted  <= pRAM_doutB_r1(32-1 downto 0) & pRAM_doutB(64-1 downto 32);
400 
 
401 
  --  Delay
402 
  Syn_Shifting_pRAM_doutB:
403 
  process ( trn_clk)
404 
  begin
405 
     if trn_clk'event and trn_clk = '1' then
406 
        pRAM_doutB_r1 <= pRAM_doutB;
407 
     end if;
408 
  end process;
409 
 
410 
  -- -----------------------------------------------
411 
  --
412 
  Syn_DDR_CKE:
413 
  process (trn_clk, Rst_i)
414 
  begin
415 
    if Rst_i = '1' then
416 
       DDR_Ready_i       <=  '0';
417 
    elsif trn_clk'event and trn_clk = '1' then
418 
       DDR_Ready_i       <=  '1';   -- ddr_DCM_locked;
419 
    end if;
420 
  end process;
421 
 
422 
  -- ----------------------------------------------------------------------------
423 
  --
424 
  -- ----------------------------------------------------------------------------
425 
--  DDR_Clock_Generator:
426 
--  DDR_ClkGen
427 
--  PORT MAP(
428 
--           ddr_Clock            =>  ddr_Clock             , -- OUT   std_logic;
429 
--           ddr_Clock_n          =>  ddr_Clock_n           , -- OUT   std_logic;
430 
--           ddr_Clock90          =>  ddr_Clock90           , -- OUT   std_logic;
431 
--           ddr_Clock90_n        =>  ddr_Clock90_n         , -- OUT   std_logic;
432 
--           Clk_ddr_rddata       =>  Clk_ddr_rddata        , -- OUT   std_logic;
433 
--           Clk_ddr_rddata_n     =>  Clk_ddr_rddata_n      , -- OUT   std_logic;
434 
--           ddr_DCM_locked       =>  ddr_DCM_locked        , -- OUT   std_logic;
435 
--
436 
--           clk_in               =>  mem_clk               , -- IN    std_logic;
437 
--           trn_reset_n          =>  trn_reset_n             -- IN    std_logic
438 
--          );
439 
 
440 
 
441 
  -- ----------------------------------------------------------------------------
442 
  --
443 
  -- ----------------------------------------------------------------------------
444 
--  DDR_pipe_write_fifo:
445 
--  asyn_rw_FIFO
446 
--  GENERIC MAP (
447 
--               OUTPUT_REGISTERED    => TRUE
448 
--              )
449 
--  PORT MAP(
450 
--           wClk          =>  trn_clk         ,
451 
--           wEn           =>  wpipe_wEn       ,
452 
--           Din           =>  wpipe_Din       ,
453 
--           aFull         =>  wpipe_aFull     ,
454 
--           Full          =>  wpipe_Full      ,
455 
--
456 
--           rClk          =>  ddr_Clock       ,  -- ddr_Clock_n     ,
457 
--           rEn           =>  wpipe_rEn       ,
458 
--           Qout          =>  wpipe_Qout      ,
459 
--           aEmpty        =>  wpipe_aEmpty    ,
460 
--           Empty         =>  wpipe_Empty     ,
461 
--
462 
--           Rst           =>  Rst_i
463 
--          );
464 
 
465 
--  DDR_pipe_write_fifo:
466 
--  asyn_rw_FIFO72
467 
--  PORT MAP(
468 
--           wClk          =>  trn_clk       ,
469 
--           wEn           =>  wpipe_wEn     ,
470 
--           Din           =>  wpipe_Din     ,
471 
--           aFull         =>  wpipe_aFull   ,
472 
--           Full          =>  open          ,
473 
--
474 
--           rClk          =>  ddr_Clock     ,
475 
--           rEn           =>  wpipe_rEn     ,
476 
--           Qout          =>  wpipe_Qout    ,
477 
--           aEmpty        =>  open          ,
478 
--           Empty         =>  wpipe_Empty   ,
479 
--
480 
--           Rst           =>  Rst_i
481 
--          );
482 
 
483 
  DDR_pipe_write_fifo:
484 
  v6_prime_FIFO_plain
485 
  PORT MAP(
486 
    wr_clk       =>  trn_clk      , -- IN  std_logic;
487 
    wr_en        =>  wpipe_wEn    , -- IN  std_logic;
488 
    din          =>  wpipe_Din    , -- IN  std_logic_VECTOR(35 downto 0);
489 
    prog_full    =>  wpipe_aFull  , -- OUT std_logic;
490 
    full         =>  wpipe_Full   , -- OUT std_logic;
491 
 
492 
    rd_clk       =>  trn_clk    , -- IN  std_logic;
493 
    rd_en        =>  wpipe_rEn    , -- IN  std_logic;
494 
    dout         =>  wpipe_Qout   , -- OUT std_logic_VECTOR(35 downto 0);
495 
    empty        =>  wpipe_Empty  , -- OUT std_logic;
496 
 
497 
    rst          =>  Rst_i          -- IN  std_logic
498 
    );
499 
 
500 
 
501 
  wpipe_wEn              <=  DDR_wr_v;
502 
  wpipe_Din              <=  DDR_wr_Mask & DDR_wr_Shift & '0' & DDR_wr_sof & DDR_wr_eof & DDR_wr_Cross_Row & DDR_wr_FA & DDR_wr_din;
503 
  DDR_wr_full            <=  wpipe_aFull;
504 
  Sim_Zeichen            <=  simone_debug; --S wpipe_Empty;
505 
 
506 
 
507 
  Syn_DDR_wrD_Cross_Row:
508 
  process (trn_clk)
509 
  begin
510 
    if trn_clk'event and trn_clk = '1' then
511 
       DDR_wr_din_r1(64-1 downto 10)     <= (OTHERS=>'0');
512 
       DDR_wr_din_r1( 9 downto  0)     <= DDR_wr_din(9 downto  0) - "100";
513 
    end if;
514 
  end process;
515 
 
516 
  DDR_write_ALC      <= (DDR_wr_din_r1(10 downto 2) &"00") + ('0' & DDR_wr_din(9 downto 2) &"00");
517 
  DDR_wr_Cross_Row   <= '0';   -- DDR_write_ALC(10);
518 
 
519 
  -- ----------------------------------------------------------------------------
520 
  --
521 
  -- ----------------------------------------------------------------------------
522 
 
523 
--  DDR_pipe_read_C_fifo:
524 
--  asyn_rw_FIFO
525 
--  GENERIC MAP (
526 
--               OUTPUT_REGISTERED    => TRUE
527 
--              )
528 
--  PORT MAP(
529 
--           wClk          =>  trn_clk         ,
530 
--           wEn           =>  rpipec_wEn      ,
531 
--           Din           =>  rpipec_Din      ,
532 
--           aFull         =>  rpipec_aFull    ,
533 
--           Full          =>  rpipec_Full     ,
534 
--
535 
--           rClk          =>  ddr_Clock       ,  -- ddr_Clock_n     ,
536 
--           rEn           =>  rpipec_rEn      ,
537 
--           Qout          =>  rpipec_Qout     ,
538 
--           aEmpty        =>  rpipec_aEmpty   ,
539 
--           Empty         =>  rpipec_Empty    ,
540 
--
541 
--           Rst           =>  Rst_i
542 
--          );
543 
--
544 
 
545 
--  DDR_pipe_read_C_fifo:
546 
--  asyn_rw_FIFO72
547 
--  PORT MAP(
548 
--           wClk          =>  trn_clk       ,
549 
--           wEn           =>  rpipec_wEn     ,
550 
--           Din           =>  rpipec_Din     ,
551 
--           aFull         =>  rpipec_aFull   ,
552 
--           Full          =>  open          ,
553 
--
554 
--           rClk          =>  ddr_Clock     ,
555 
--           rEn           =>  rpipec_rEn     ,
556 
--           Qout          =>  rpipec_Qout    ,
557 
--           aEmpty        =>  open          ,
558 
--           Empty         =>  rpipec_Empty   ,
559 
--
560 
--           Rst           =>  Rst_i
561 
--          );
562 
 
563 
  DDR_pipe_read_C_fifo:
564 
  v6_prime_FIFO_plain
565 
  PORT MAP(
566 
    wr_clk       =>  trn_clk        , -- IN  std_logic;
567 
    wr_en        =>  rpipec_wEn     , -- IN  std_logic;
568 
    din          =>  rpipec_Din     , -- IN  std_logic_VECTOR(35 downto 0);
569 
    prog_full    =>  rpipec_aFull   , -- OUT std_logic;
570 
    full         =>  open,   --rpipec_Full    , -- OUT std_logic;
571 
 
572 
    rd_clk       =>  trn_clk      , -- IN  std_logic;
573 
    rd_en        =>  rpipec_rEn     , -- IN  std_logic;
574 
    dout         =>  rpipec_Qout    , -- OUT std_logic_VECTOR(35 downto 0);
575 
    empty        =>  rpipec_Empty   , -- OUT std_logic;
576 
 
577 
    rst          =>  Rst_i            -- IN  std_logic
578 
    );
579 
 
580 
 
581 
  rpipec_wEn             <=  DDR_rdc_v;
582 
  rpipec_Din             <=  "00" & DDR_rdc_Shift & '0' & DDR_rdc_sof & DDR_rdc_eof & DDR_rd_Cross_Row & DDR_rdc_FA & DDR_rdc_din;
583 
  DDR_rdc_full           <=  rpipec_aFull;
584 
 
585 
 
586 
  Syn_DDR_rdC_Cross_Row:
587 
  process (trn_clk)
588 
  begin
589 
    if trn_clk'event and trn_clk = '1' then
590 
       DDR_rdc_din_r1(64-1 downto 10)   <= (OTHERS=>'0');
591 
       DDR_rdc_din_r1( 9 downto  0)     <= DDR_rdc_din(9 downto  0) - "100";
592 
    end if;
593 
  end process;
594 
 
595 
  DDR_read_ALC       <= (DDR_rdc_din_r1(10 downto 2) &"00") + ('0' & DDR_rdc_din(9 downto 2) &"00");
596 
  DDR_rd_Cross_Row   <= '0';   -- DDR_read_ALC(10);
597 
 
598 
  -- ----------------------------------------------------------------------------
599 
  --
600 
  -- ----------------------------------------------------------------------------
601 
--  DDR_pipe_read_D_fifo:
602 
--  asyn_rw_FIFO
603 
--  GENERIC MAP (
604 
--               OUTPUT_REGISTERED    => TRUE
605 
--              )
606 
--  PORT MAP(
607 
--           wClk          =>  ddr_Clock,       -- Clk_ddr_rddata  ,  -- ddr_Clock       ,  -- ddr_Clock_n     ,
608 
--           wEn           =>  rpiped_wEn      ,
609 
--           Din           =>  rpiped_Din      ,
610 
--           aFull         =>  rpiped_aFull    ,
611 
--           Full          =>  rpiped_Full     ,
612 
--
613 
--           rClk          =>  trn_clk         ,
614 
--           rEn           =>  DDR_FIFO_RdEn   ,  -- rpiped_rEn      ,
615 
--           Qout          =>  rpiped_Qout     ,
616 
--           aEmpty        =>  open            ,  -- rpiped_aEmpty   ,
617 
--           Empty         =>  DDR_FIFO_Empty  ,  -- rpiped_Empty    ,
618 
--
619 
--           Rst           =>  Rst_i
620 
--          );
621 
 
622 
--  DDR_pipe_read_D_fifo:
623 
--  asyn_rw_FIFO72
624 
--  PORT MAP(
625 
--           wClk          =>  ddr_Clock       ,
626 
--           wEn           =>  rpiped_wEn     ,
627 
--           Din           =>  rpiped_Din     ,
628 
--           aFull         =>  rpiped_aFull   ,
629 
--           Full          =>  open          ,
630 
--
631 
--           rClk          =>  trn_clk     ,
632 
--           rEn           =>  DDR_FIFO_RdEn     ,
633 
--           Qout          =>  rpiped_Qout    ,
634 
--           aEmpty        =>  open          ,
635 
--           Empty         =>  DDR_FIFO_Empty   ,
636 
--
637 
--           Rst           =>  Rst_i
638 
--          );
639 
 
640 
  DDR_pipe_read_D_fifo:
641 
  v6_prime_FIFO_plain
642 
  PORT MAP(
643 
    wr_clk       =>  trn_clk      , -- IN  std_logic;
644 
    wr_en        =>  rpiped_wEn      , -- IN  std_logic;
645 
    din          =>  rpiped_Din      , -- IN  std_logic_VECTOR(35 downto 0);
646 
    prog_full    =>  rpiped_aFull    , -- OUT std_logic;
647 
    full         =>  open,    -- rpiped_Full     , -- OUT std_logic;
648 
 
649 
    rd_clk       =>  trn_clk         , -- IN  std_logic;
650 
    rd_en        =>  DDR_FIFO_RdEn   , -- IN  std_logic;
651 
    dout         =>  rpiped_Qout     , -- OUT std_logic_VECTOR(35 downto 0);
652 
    empty        =>  DDR_FIFO_Empty  , -- OUT std_logic;
653 
 
654 
    rst          =>  Rst_i             -- IN  std_logic
655 
    );
656 
 
657 
 
658 
    DDR_FIFO_RdQout      <=  rpiped_Qout(C_DBUS_WIDTH-1 downto 0);
659 
 
660 
 
661 
 
662 
    -- -------------------------------------------------
663 
    -- pkt_RAM instantiate
664 
    --
665 
    pkt_RAM_IN:
666 
    v6_bram4096x64
667 
      port map (
668 
         clka      =>    trn_clk  ,
669 
         addra     =>    pRAM_addrA ,
670 
         wea       =>    pRAM_weA   ,
671 
         dina      =>    pRAM_dinA  ,
672 
         douta     =>    pRAM_doutA ,
673 
 
674 
         clkb      =>    user_rd_clk  ,
675 
         addrb     =>    user_rd_addrB ,
676 
         web       =>    user_rd_weB   ,  --'0'
677 
         dinb      =>    user_rd_dinB  ,  --'0'
678 
         doutb     =>    user_rd_doutB
679 
       );
680 
 
681 
    user_rd_weB       <= X"00";
682 
    user_rd_dinB      <= (Others =>'0');
683 
 
684 
    pkt_RAM_OUT:
685 
    v6_bram4096x64
686 
      port map (
687 
         clka      =>    user_wr_clk  ,
688 
         addra     =>    user_wr_addrA ,
689 
         wea       =>    user_wr_weA   ,
690 
         dina      =>    user_wr_dinA  ,
691 
         douta     =>    user_wr_doutA , --'open'
692 
 
693 
         clkb      =>    trn_clk  ,
694 
         addrb     =>    pRAM_addrB ,
695 
         web       =>    pRAM_weB   ,
696 
         dinb      =>    pRAM_dinB  ,
697 
         doutb     =>    pRAM_doutB
698 
       );
699 
 
700 
    pRAM_weB       <= X"00";
701 
    pRAM_dinB      <= (Others =>'0');
702 
 
703 
 
704 
 
705 
--my_pcie_userlogic_02_cw : pcie_userlogic_02_cw
706 
--  port map (
707 
--
708 
--    addra => pRAM_addrA,
709 
--    addrb => pRAM_addrB,
710 
--    ce    => '1',
711 
--    clk   => trn_clk,
712 
--    dina  => pRAM_dinA,
713 
--    dinb  => pRAM_dinB,
714 
--    douta => pRAM_doutA,
715 
--    doutb => pRAM_doutB,
716 
--    rst_i => Rst_i,
717 
--    wea   => pRAM_weA,
718 
--    web   => pRAM_weB,
719 
--    rst_o => simone_debug
720 
--  );
721 
 
722 
 simone_debug <= '0';
723 
 
724 
 
725 
 
726 
-- ------------------------------------------------
727 
-- write States synchronous
728 
--
729 
   Syn_Pseudo_DDR_wr_States:
730 
   process ( trn_clk, trn_reset_n)
731 
   begin
732 
      if trn_reset_n = '0' then
733 
         pseudo_DDR_wr_State   <= wrST_bram_RESET;
734 
         pRAM_addrA            <= (OTHERS=>'1');
735 
         pRAM_weA              <= (OTHERS=>'0');
736 
         pRAM_dinA             <= (OTHERS=>'0');
737 
         wpipe_qout_lo32b      <= (OTHERS=>'0');
738 
         wpipe_QW_Aligned      <= '1';
739 
         pRAM_AddrA_Inc        <= '1';
740 
 
741 
      elsif trn_clk'event and trn_clk = '1' then
742 
 
743 
        case pseudo_DDR_wr_State  is
744 
 
745 
          when wrST_bram_RESET =>
746 
             pseudo_DDR_wr_State   <= wrST_bram_IDLE;
747 
             pRAM_addrA            <= (OTHERS=>'1');
748 
             wpipe_QW_Aligned      <= '1';
749 
             wpipe_qout_lo32b      <= (OTHERS=>'0');
750 
             pRAM_weA              <= (OTHERS=>'0');
751 
             pRAM_dinA             <= (OTHERS=>'0');
752 
             pRAM_AddrA_Inc        <= '1';
753 
 
754 
          when wrST_bram_IDLE =>
755 
             pRAM_addrA            <= wpipe_Qout(14 downto 3);
756 
             pRAM_AddrA_Inc        <= wpipe_Qout(2);
757 
             wpipe_QW_Aligned      <= not wpipe_Qout(69);
758 
             wpipe_qout_lo32b      <= (32=>'1', OTHERS=>'0');
759 
             pRAM_weA              <= (OTHERS=>'0');
760 
             pRAM_dinA             <= pRAM_dinA;
761 
             if wpipe_read_valid = '1' then
762 
               pseudo_DDR_wr_State   <= wrST_bram_1st_Data;  -- wrST_bram_Address;
763 
             else
764 
               pseudo_DDR_wr_State   <= wrST_bram_IDLE;
765 
             end if;
766 
 
767 
 
768 
          when wrST_bram_1st_Data =>
769 
             pRAM_addrA          <= pRAM_addrA;
770 
             if wpipe_read_valid = '0' then
771 
               pseudo_DDR_wr_State <= wrST_bram_1st_Data;
772 
               pRAM_weA            <= (OTHERS=>'0'); --pRAM_weA;
773 
               pRAM_dinA           <= pRAM_dinA;
774 
             elsif wpipe_Qout(66)='1' then   -- eof
775 
                if wpipe_QW_Aligned='1' then
776 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
777 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
778 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
779 
                                             );
780 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
781 
                elsif wpipe_Qout(70)='1' then     -- mask(0)
782 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
783 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
784 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
785 
                                             );
786 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
787 
                elsif wpipe_Qout(71)='1' then     -- mask(1)
788 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
789 
                  pRAM_weA            <= X"F0";
790 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
791 
                else
792 
                  pseudo_DDR_wr_State <= wrST_bram_last_DW;
793 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
794 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
795 
                                             );
796 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
797 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
798 
                end if;
799 
             else
800 
                if wpipe_QW_Aligned='1' then
801 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
802 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
803 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
804 
                                             );
805 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
806 
                elsif pRAM_AddrA_Inc='1' then
807 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
808 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
809 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
810 
                                             );
811 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
812 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
813 
                else
814 
                  pseudo_DDR_wr_State <= wrST_bram_1st_Data;
815 
                  pRAM_AddrA_Inc      <= '1';
816 
                  pRAM_weA            <= X"00";
817 
                  pRAM_dinA           <= pRAM_dinA;
818 
                  wpipe_qout_lo32b    <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
819 
                end if;
820 
             end if;
821 
 
822 
          when wrST_bram_more_Data =>
823 
             if wpipe_read_valid = '0' then
824 
               pseudo_DDR_wr_State <= wrST_bram_more_Data;  -- wrST_bram_1st_Data;
825 
               pRAM_weA            <= (OTHERS=>'0'); --pRAM_weA;
826 
               pRAM_addrA          <= pRAM_addrA;
827 
               pRAM_dinA           <= pRAM_dinA;
828 
             elsif wpipe_Qout(66)='1' then   -- eof
829 
                if wpipe_QW_Aligned='1' then
830 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
831 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
832 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
833 
                                             );
834 
                  pRAM_addrA          <= pRAM_addrA + '1';
835 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
836 
                elsif wpipe_Qout(70)='1' then  -- mask(0)
837 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
838 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
839 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
840 
                                             );
841 
                  pRAM_addrA          <= pRAM_addrA + '1';
842 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
843 
                else
844 
                  pseudo_DDR_wr_State <= wrST_bram_last_DW;
845 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
846 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
847 
                                             );
848 
                  pRAM_addrA          <= pRAM_addrA + '1';
849 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
850 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
851 
                end if;
852 
             else
853 
                if wpipe_QW_Aligned='1' then
854 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
855 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
856 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
857 
                                             );
858 
                  pRAM_addrA          <= pRAM_addrA + '1';
859 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
860 
                else
861 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
862 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
863 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
864 
                                             );
865 
                  pRAM_addrA          <= pRAM_addrA + '1';
866 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
867 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
868 
                end if;
869 
             end if;
870 
 
871 
 
872 
          when wrST_bram_last_DW =>
873 
--             pseudo_DDR_wr_State   <= wrST_bram_IDLE;
874 
             pRAM_weA              <= X"F0";
875 
             pRAM_addrA            <= pRAM_addrA + '1';
876 
             pRAM_dinA             <= wpipe_qout_lo32b(32-1 downto 0) & X"00000000";
877 
             if wpipe_read_valid = '1' then
878 
               pseudo_DDR_wr_State         <= wrST_bram_1st_Data_b2b;  -- wrST_bram_Address;
879 
               wpipe_Qout_latch            <= wpipe_Qout;
880 
             else
881 
               pseudo_DDR_wr_State         <= wrST_bram_IDLE;
882 
               wpipe_Qout_latch            <= wpipe_Qout;
883 
             end if;
884 
 
885 
 
886 
          when wrST_bram_1st_Data_b2b =>
887 
             pRAM_addrA            <= wpipe_Qout_latch(14 downto 3);
888 
             wpipe_QW_Aligned      <= not wpipe_Qout_latch(69);
889 
             if wpipe_read_valid = '0' then
890 
               pseudo_DDR_wr_State <= wrST_bram_1st_Data;
891 
               pRAM_weA            <= (OTHERS=>'0'); --pRAM_weA;
892 
               pRAM_dinA           <= pRAM_dinA;
893 
               pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
894 
               wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
895 
             elsif wpipe_Qout(66)='1' then   -- eof
896 
                if wpipe_Qout_latch(69)='0' then   -- wpipe_QW_Aligned
897 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
898 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
899 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
900 
                                             );
901 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
902 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
903 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
904 
                elsif wpipe_Qout(70)='1' then     -- mask(0)
905 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
906 
                  pRAM_weA            <= not ( X"f"
907 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
908 
                                             );
909 
                  pRAM_dinA           <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
910 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
911 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
912 
                elsif wpipe_Qout(71)='1' then     -- mask(1)
913 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
914 
                  pRAM_weA            <= X"F0";
915 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
916 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
917 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
918 
                else
919 
                  pseudo_DDR_wr_State <= wrST_bram_last_DW;
920 
                  pRAM_weA            <= not ( X"f"
921 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
922 
                                             );
923 
                  pRAM_dinA           <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
924 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
925 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
926 
                end if;
927 
             else
928 
                if wpipe_Qout_latch(69)='0' then    -- wpipe_QW_Aligned
929 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
930 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
931 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
932 
                                             );
933 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
934 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
935 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
936 
                elsif wpipe_Qout_latch(2)='1' then   -- pRAM_AddrA_Inc
937 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
938 
                  pRAM_weA            <= not ( X"f"
939 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
940 
                                             );
941 
                  pRAM_dinA           <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
942 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
943 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
944 
                else
945 
                  pseudo_DDR_wr_State <= wrST_bram_1st_Data;
946 
                  pRAM_AddrA_Inc      <= '1';
947 
                  pRAM_weA            <= X"00";
948 
                  pRAM_dinA           <= pRAM_dinA;
949 
                  wpipe_qout_lo32b    <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
950 
                end if;
951 
             end if;
952 
 
953 
 
954 
          when OTHERS =>
955 
             pseudo_DDR_wr_State   <= wrST_bram_RESET;
956 
             pRAM_addrA            <= (OTHERS=>'1');
957 
             pRAM_weA              <= (OTHERS=>'0');
958 
             pRAM_dinA             <= (OTHERS=>'0');
959 
             wpipe_qout_lo32b      <= (OTHERS=>'0');
960 
             wpipe_QW_Aligned      <= '1';
961 
             pRAM_AddrA_Inc        <= '1';
962 
 
963 
        end case;
964 
 
965 
      end if;
966 
   end process;
967 
 
968 
 
969 
   --
970 
   Syn_wPipe_read:
971 
   process ( trn_clk, DDR_Ready_i)
972 
   begin
973 
      if DDR_Ready_i = '0' then
974 
         wpipe_rEn         <= '0';
975 
         wpipe_read_valid  <= '0';
976 
 
977 
      elsif trn_clk'event and trn_clk = '1' then
978 
 
979 
         wpipe_rEn         <= '1';
980 
         wpipe_read_valid  <= wpipe_rEn and not wpipe_Empty;
981 
 
982 
      end if;
983 
   end process;
984 
 
985 
 
986 
 
987 
   --
988 
   Syn_rPipeC_read:
989 
   process ( trn_clk, DDR_Ready_i)
990 
   begin
991 
      if DDR_Ready_i = '0' then
992 
         rpipec_read_valid    <= '0';
993 
         rpiped_wr_postpone   <= '0';
994 
         rpiped_wr_skew       <= '0';
995 
 
996 
      elsif trn_clk'event and trn_clk = '1' then
997 
 
998 
         rpipec_read_valid  <= rpipec_rEn and not rpipec_Empty;
999 
         if rpipec_read_valid='1' then
1000 
            rpiped_wr_postpone  <= rpipec_Qout(2) and not rpipec_Qout(69);
1001 
            rpiped_wr_skew      <= rpipec_Qout(69) xor rpipec_Qout(2);
1002 
         else
1003 
            rpiped_wr_postpone  <= rpiped_wr_postpone;
1004 
            rpiped_wr_skew      <= rpiped_wr_skew;
1005 
         end if;
1006 
 
1007 
      end if;
1008 
   end process;
1009 
 
1010 
-- ------------------------------------------------
1011 
-- Read States synchronous
1012 
--
1013 
   Syn_Pseudo_DDR_rd_States:
1014 
   process ( trn_clk, DDR_Ready_i)
1015 
   begin
1016 
      if DDR_Ready_i = '0' then
1017 
         pseudo_DDR_rd_State   <= rdST_bram_RESET;
1018 
         rpipec_rEn            <= '0';
1019 
         pRAM_addrB            <= (OTHERS=>'1');
1020 
         rpiped_rd_counter     <= (OTHERS=>'0');
1021 
         rpiped_wEn_b3         <= '0';
1022 
         rpiped_wr_EOF         <= '0';
1023 
 
1024 
      elsif trn_clk'event and trn_clk = '1' then
1025 
 
1026 
        case pseudo_DDR_rd_State  is
1027 
 
1028 
          when rdST_bram_RESET =>
1029 
             pseudo_DDR_rd_State   <= rdST_bram_IDLE;
1030 
             rpipec_rEn            <= '0';
1031 
             pRAM_addrB            <= (OTHERS=>'1');
1032 
             rpiped_rd_counter     <= (OTHERS=>'0');
1033 
             rpiped_wEn_b3         <= '0';
1034 
             rpiped_wr_EOF         <= '0';
1035 
 
1036 
          when rdST_bram_IDLE =>
1037 
             pRAM_addrB            <= pRAM_addrB;
1038 
             rpiped_rd_counter     <= (OTHERS=>'0');
1039 
             rpiped_wEn_b3         <= '0';
1040 
             rpiped_wr_EOF         <= '0';
1041 
             if rpipec_Empty = '0' then
1042 
               rpipec_rEn          <= '1';
1043 
               pseudo_DDR_rd_State <= rdST_bram_b4_LA;  --rdST_bram_b4_Length;
1044 
             else
1045 
               rpipec_rEn          <= '0';
1046 
               pseudo_DDR_rd_State <= rdST_bram_IDLE;
1047 
             end if;
1048 
 
1049 
          when rdST_bram_b4_LA =>
1050 
             pRAM_addrB            <= pRAM_addrB;
1051 
             rpiped_rd_counter     <= (OTHERS=>'0');
1052 
             rpiped_wEn_b3         <= '0';
1053 
             rpiped_wr_EOF         <= '0';
1054 
             rpipec_rEn            <= '0';
1055 
             pseudo_DDR_rd_State   <= rdST_bram_LA;
1056 
 
1057 
          when rdST_bram_LA =>
1058 
             rpipec_rEn            <= '0';
1059 
             pRAM_addrB            <= rpipec_Qout(14 downto 3);
1060 
             rpiped_wr_EOF         <= '0';
1061 
             rpiped_wEn_b3         <= '0';
1062 
             if rpipec_Qout(2+32)='1' then
1063 
               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + '1';
1064 
             elsif rpipec_Qout(2)='1' and rpipec_Qout(69)='1' then
1065 
               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + "10";
1066 
             elsif rpipec_Qout(2)='0' and rpipec_Qout(69)='1' then
1067 
               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + "10";
1068 
             elsif rpipec_Qout(2)='1' and rpipec_Qout(69)='0' then
1069 
               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32);
1070 
             else
1071 
               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32);
1072 
             end if;
1073 
 
1074 
--             elsif rpipec_Qout(2)='1' then
1075 
--               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + "10";
1076 
--             elsif rpipec_Qout(69)='1' then
1077 
--               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + "10";
1078 
--             else
1079 
--               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32);
1080 
--             end if;
1081 
             pseudo_DDR_rd_State   <= rdST_bram_Data;
1082 
 
1083 
 
1084 
          when rdST_bram_Data =>
1085 
             rpipec_rEn            <= '0';
1086 
             if rpiped_rd_counter = CONV_STD_LOGIC_VECTOR(2, 10) then
1087 
               pRAM_addrB            <= pRAM_addrB + '1';
1088 
               rpiped_rd_counter     <= rpiped_rd_counter;
1089 
               rpiped_wEn_b3         <= '1';
1090 
               rpiped_wr_EOF         <= '1';
1091 
               pseudo_DDR_rd_State   <= rdST_bram_IDLE;
1092 
             elsif rpiped_aFull = '1' then
1093 
               pRAM_addrB            <= pRAM_addrB;
1094 
               rpiped_rd_counter     <= rpiped_rd_counter;
1095 
               rpiped_wEn_b3         <= '0';
1096 
               rpiped_wr_EOF         <= '0';
1097 
               pseudo_DDR_rd_State   <= rdST_bram_Data;
1098 
             else
1099 
               pRAM_addrB            <= pRAM_addrB + '1';
1100 
               rpiped_rd_counter     <= rpiped_rd_counter - "10";
1101 
               rpiped_wEn_b3         <= '1';
1102 
               rpiped_wr_EOF         <= '0';
1103 
               pseudo_DDR_rd_State   <= rdST_bram_Data;
1104 
             end if;
1105 
 
1106 
 
1107 
          when OTHERS =>
1108 
               rpipec_rEn            <= '0';
1109 
               pRAM_addrB            <= pRAM_addrB;
1110 
               rpiped_rd_counter     <= rpiped_rd_counter;
1111 
               rpiped_wEn_b3         <= '0';
1112 
               rpiped_wr_EOF         <= '0';
1113 
               pseudo_DDR_rd_State   <= rdST_bram_RESET;
1114 
 
1115 
        end case;
1116 
 
1117 
      end if;
1118 
   end process;
1119 
 
1120 
 
1121 
 
1122 
   Syn_Pseudo_DDR_rdd_write:
1123 
   process ( trn_clk, DDR_Ready_i)
1124 
   begin
1125 
      if DDR_Ready_i = '0' then
1126 
         rpiped_wEn_b1      <= '0';
1127 
         rpiped_wEn_b2      <= '0';
1128 
         rpiped_wEn         <= '0';
1129 
         rpiped_Din         <= (OTHERS=>'0');
1130 
 
1131 
      elsif trn_clk'event and trn_clk = '1' then
1132 
 
1133 
         rpiped_wEn_b2      <= rpiped_wEn_b3;
1134 
         rpiped_wEn_b1      <= rpiped_wEn_b2;
1135 
         if rpiped_wr_skew='1' then
1136 
--           rpiped_wEn         <= rpiped_wEn_b2;
1137 
           rpiped_wEn         <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
1138 
                              or (rpiped_wEn_b1 and rpiped_wr_postpone);
1139 
           rpiped_Din         <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB_shifted;
1140 
         else
1141 
--           rpiped_wEn         <= rpiped_wEn_b2;
1142 
           rpiped_wEn         <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
1143 
                              or (rpiped_wEn_b1 and rpiped_wr_postpone);
1144 
           rpiped_Din         <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB;
1145 
         end if;
1146 
 
1147 
      end if;
1148 
   end process;
1149 
 
1150 
 
1151 
  --
1152 
  DDR_Blinker_Module:
1153 
  DDR_Blink
1154 
  PORT MAP(
1155 
           DDR_Blinker          =>  DDR_Blinker    ,
1156 
 
1157 
           DDR_Write            =>  wpipe_rEn      ,
1158 
           DDR_Read             =>  rpiped_wEn     ,
1159 
           DDR_Both             =>  '0'            ,
1160 
 
1161 
           ddr_Clock            =>  trn_clk      ,
1162 
           DDr_Rst_n            =>  DDR_Ready_i      -- DDR_CKE_i
1163 
          );
1164 
 
1165 
 
1166 
end architecture Behavioral;

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