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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MySource/] [bram_DDRs_Control_Loopback.vhd] - Blame information for rev 13

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1 13 barabba 
----------------------------------------------------------------------------------
2 
-- Company:  ZITI
3 
-- Engineer:  wgao
4 
--
5 
-- Create Date:    12:29:46 04/15/2008
6 
-- Design Name:
7 
-- Module Name:    bram_DDRs_Control - Behavioral
8 
-- Project Name:
9 
-- Target Devices:
10 
-- Tool versions:
11 
-- Description:
12 
--
13 
-- Dependencies:
14 
--
15 
-- Revision:
16 
-- Revision 0.01 - File Created
17 
-- Additional Comments:
18 
--
19 
----------------------------------------------------------------------------------
20 
library IEEE;
21 
use IEEE.STD_LOGIC_1164.ALL;
22 
use IEEE.STD_LOGIC_ARITH.ALL;
23 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 
 
25 
library work;
26 
use work.abb64Package.all;
27 
 
28 
---- Uncomment the following library declaration if instantiating
29 
---- any Xilinx primitives in this code.
30 
--library UNISIM;
31 
--use UNISIM.VComponents.all;
32 
 
33 
entity bram_DDRs_Control_loopback is
34 
    Generic (
35 
             C_ASYNFIFO_WIDTH  :  integer  :=  72 ;
36 
             P_SIMULATION      :  boolean  :=  TRUE
37 
            );
38 
    Port (
39 
 
40 
--           -- Pins
41 
--           DDR_CLKn                 : OUT   std_logic;
42 
--           DDR_CLK                  : OUT   std_logic;
43 
--           DDR_CKE                  : OUT   std_logic;
44 
--           DDR_CSn                  : OUT   std_logic;
45 
--           DDR_RASn                 : OUT   std_logic;
46 
--           DDR_CASn                 : OUT   std_logic;
47 
--           DDR_WEn                  : OUT   std_logic;
48 
--           DDR_BankAddr             : OUT   std_logic_vector(C_DDR_BANK_AWIDTH-1 downto 0);
49 
--           DDR_Addr                 : OUT   std_logic_vector(C_DDR_AWIDTH-1 downto 0);
50 
--           DDR_DM                   : OUT   std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
51 
--           DDR_DQ                   : INOUT std_logic_vector(C_DDR_DWIDTH-1 downto 0);
52 
--           DDR_DQS                  : INOUT std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
53 
 
54 
           -- DMA interface
55 
           DDR_wr_sof               : IN    std_logic;
56 
           DDR_wr_eof               : IN    std_logic;
57 
           DDR_wr_v                 : IN    std_logic;
58 
           DDR_wr_FA                : IN    std_logic;
59 
           DDR_wr_Shift             : IN    std_logic;
60 
           DDR_wr_Mask              : IN    std_logic_vector(2-1 downto 0);
61 
           DDR_wr_din               : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
62 
           DDR_wr_full              : OUT   std_logic;
63 
 
64 
           DDR_rdc_sof              : IN    std_logic;
65 
           DDR_rdc_eof              : IN    std_logic;
66 
           DDR_rdc_v                : IN    std_logic;
67 
           DDR_rdc_FA               : IN    std_logic;
68 
           DDR_rdc_Shift            : IN    std_logic;
69 
           DDR_rdc_din              : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
70 
           DDR_rdc_full             : OUT   std_logic;
71 
 
72 
--           DDR_rdD_sof              : OUT   std_logic;
73 
--           DDR_rdD_eof              : OUT   std_logic;
74 
--           DDR_rdDout_V             : OUT   std_logic;
75 
--           DDR_rdDout               : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
76 
 
77 
           -- DDR payload FIFO Read Port
78 
           DDR_FIFO_RdEn            : IN    std_logic;
79 
           DDR_FIFO_Empty           : OUT   std_logic;
80 
           DDR_FIFO_RdQout          : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
81 
 
82 
           -- Common interface
83 
           DDR_Ready                : OUT   std_logic;
84 
           DDR_blinker              : OUT   std_logic;
85 
           Sim_Zeichen              : OUT   std_logic;
86 
 
87 
           mem_clk                  : IN    std_logic;
88 
           trn_clk                  : IN    std_logic;
89 
           trn_reset_n              : IN    std_logic
90 
          );
91 
end entity bram_DDRs_Control_loopback;
92 
 
93 
 
94 
architecture Behavioral of bram_DDRs_Control_loopback is
95 
 
96 
  -- ----------------------------------------------------------------------------
97 
  --
98 
  -- ----------------------------------------------------------------------------
99 
  COMPONENT DDR_ClkGen
100 
    PORT(
101 
         ddr_Clock              : OUT   std_logic;
102 
         ddr_Clock_n            : OUT   std_logic;
103 
         ddr_Clock90            : OUT   std_logic;
104 
         ddr_Clock90_n          : OUT   std_logic;
105 
         Clk_ddr_rddata         : OUT   std_logic;
106 
         Clk_ddr_rddata_n       : OUT   std_logic;
107 
 
108 
         ddr_DCM_locked         : OUT   std_logic;
109 
 
110 
         clk_in                 : IN    std_logic;
111 
         trn_reset_n            : IN    std_logic
112 
        );
113 
  END COMPONENT;
114 
 
115 
 
116 
  -- ----------------------------------------------------------------------------
117 
  --
118 
  -- ----------------------------------------------------------------------------
119 
 
120 
  COMPONENT asyn_rw_FIFO72
121 
--    GENERIC (
122 
--             OUTPUT_REGISTERED  : BOOLEAN
123 
--            );
124 
    PORT(
125 
        wClk                    : IN     std_logic;
126 
        wEn                     : IN     std_logic;
127 
        Din                     : IN     std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
128 
        aFull                   : OUT    std_logic;
129 
        Full                    : OUT    std_logic;
130 
 
131 
        rClk                    : IN     std_logic;
132 
        rEn                     : IN     std_logic;
133 
        Qout                    : OUT    std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
134 
        aEmpty                  : OUT    std_logic;
135 
        Empty                   : OUT    std_logic;
136 
 
137 
        Rst                     : IN     std_logic
138 
        );
139 
  END COMPONENT;
140 
 
141 
 
142 
  component v6_prime_FIFO_plain
143 
      port (
144 
      wr_clk   : IN  std_logic;
145 
      wr_en    : IN  std_logic;
146 
      din      : IN  std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
147 
      full     : OUT std_logic;
148 
      prog_full: OUT std_logic;
149 
      rd_clk   : IN  std_logic;
150 
      rd_en    : IN  std_logic;
151 
      dout     : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
152 
      empty    : OUT std_logic;
153 
      rst      : IN  std_logic
154 
      );
155 
  end component;
156 
 
157 
--  component fifo_512x36_v4_2
158 
--    port (
159 
--    wr_clk      : IN  std_logic;
160 
--    wr_en       : IN  std_logic;
161 
--    din         : IN  std_logic_VECTOR(35 downto 0);
162 
--    prog_full   : OUT std_logic;
163 
--    full        : OUT std_logic;
164 
--
165 
--    rd_clk      : IN  std_logic;
166 
--    rd_en       : IN  std_logic;
167 
--    dout        : OUT std_logic_VECTOR(35 downto 0);
168 
--    prog_empty  : OUT std_logic;
169 
--    empty       : OUT std_logic;
170 
--
171 
--    rst         : IN  std_logic
172 
--    );
173 
--  end component;
174 
 
175 
  component fifo_512x72_v4_4
176 
    port (
177 
    wr_clk      : IN  std_logic;
178 
    wr_en       : IN  std_logic;
179 
    din         : IN  std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
180 
    prog_full   : OUT std_logic;
181 
    full        : OUT std_logic;
182 
 
183 
    rd_clk      : IN  std_logic;
184 
    rd_en       : IN  std_logic;
185 
    dout        : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
186 
--    prog_empty  : OUT std_logic;
187 
    empty       : OUT std_logic;
188 
 
189 
    rst         : IN  std_logic
190 
    );
191 
  end component;
192 
 
193 
 
194 
  ---- Dual-port block RAM for packets
195 
  ---    Core output registered
196 
  --
197 
--  component v5bram4096x32
198 
--    port (
199 
--      clka           : IN  std_logic;
200 
--      addra          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
201 
--      wea            : IN  std_logic_vector(0 downto 0);
202 
--      dina           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
203 
--      douta          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
204 
--
205 
--      clkb           : IN  std_logic;
206 
--      addrb          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
207 
--      web            : IN  std_logic_vector(0 downto 0);
208 
--      dinb           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
209 
--      doutb          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
210 
--    );
211 
--  end component;
212 
 
213 
 
214 
 
215 
  component v6_bram4096x64
216 
    port (
217 
      clka           : IN  std_logic;
218 
      addra          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
219 
      wea            : IN  std_logic_vector(7 downto 0);
220 
      dina           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
221 
      douta          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
222 
 
223 
      clkb           : IN  std_logic;
224 
      addrb          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
225 
      web            : IN  std_logic_vector(7 downto 0);
226 
      dinb           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
227 
      doutb          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
228 
    );
229 
  end component;
230 
 
231 
  -- Blinking  -_-_-_-_-_-_-_-_-_-_-_-_-_-_-
232 
  COMPONENT DDR_Blink
233 
    PORT(
234 
           DDR_Blinker              : OUT   std_logic;
235 
 
236 
           DDR_Write                : IN    std_logic;
237 
           DDR_Read                 : IN    std_logic;
238 
           DDR_Both                 : IN    std_logic;
239 
 
240 
           ddr_Clock                : IN    std_logic;
241 
           DDr_Rst_n                : IN    std_logic
242 
          );
243 
  END COMPONENT;
244 
 
245 
  -- ---------------------------------------------------------------------
246 
  signal  ddr_DCM_locked        :  std_logic;
247 
  --  -- ---------------------------------------------------------------------
248 
  signal  Rst_i                 :  std_logic;
249 
  --  -- ---------------------------------------------------------------------
250 
  signal  DDR_Ready_i           :  std_logic;
251 
  --  -- ---------------------------------------------------------------------
252 
  signal  ddr_Clock             :  std_logic;
253 
  signal  ddr_Clock_n           :  std_logic;
254 
  signal  ddr_Clock90           :  std_logic;
255 
  signal  ddr_Clock90_n         :  std_logic;
256 
 
257 
  signal  Clk_ddr_rddata        :  std_logic;
258 
  signal  Clk_ddr_rddata_n      :  std_logic;
259 
 
260 
  -- -- --  Write Pipe Channel
261 
  signal  wpipe_wEn             :  std_logic;
262 
  signal  wpipe_Din             :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
263 
  signal  wpipe_aFull           :  std_logic;
264 
  signal  wpipe_Full            :  std_logic;
265 
  --  Earlier calculate for better timing
266 
  signal  DDR_wr_Cross_Row      :  std_logic;
267 
  signal  DDR_wr_din_r1         :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
268 
  signal  DDR_write_ALC         :  std_logic_vector(11-1 downto 0);
269 
 
270 
  signal  wpipe_rEn             :  std_logic;
271 
  signal  wpipe_Qout            :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
272 
--  signal  wpipe_aEmpty          :  std_logic;
273 
  signal  wpipe_Empty           :  std_logic;
274 
  signal  wpipe_Qout_latch      :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
275 
 
276 
  -- -- --  Read Pipe Command Channel
277 
  signal  rpipec_wEn            :  std_logic;
278 
  signal  rpipec_Din            :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
279 
  signal  rpipec_aFull          :  std_logic;
280 
  signal  rpipec_Full           :  std_logic;
281 
  --  Earlier calculate for better timing
282 
  signal  DDR_rd_Cross_Row      :  std_logic;
283 
  signal  DDR_rdc_din_r1        :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
284 
  signal  DDR_read_ALC          :  std_logic_vector(11-1 downto 0);
285 
 
286 
  signal  rpipec_rEn            :  std_logic;
287 
  signal  rpipec_Qout           :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
288 
--  signal  rpipec_aEmpty         :  std_logic;
289 
  signal  rpipec_Empty          :  std_logic;
290 
 
291 
  -- -- --  Read Pipe Data Channel
292 
  signal  rpiped_wEn            :  std_logic;
293 
  signal  rpiped_Din            :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
294 
  signal  rpiped_aFull          :  std_logic;
295 
  signal  rpiped_Full           :  std_logic;
296 
 
297 
--  signal  rpiped_rEn            :  std_logic;
298 
  signal  rpiped_Qout           :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
299 
--  signal  rpiped_aEmpty         :  std_logic;
300 
--  signal  rpiped_Empty          :  std_logic;
301 
 
302 
 
303 
  --   write State machine
304 
  type bram_wrStates is          ( wrST_bram_RESET
305 
                                 , wrST_bram_IDLE
306 
--                                 , wrST_bram_Address
307 
                                 , wrST_bram_1st_Data
308 
                                 , wrST_bram_1st_Data_b2b
309 
                                 , wrST_bram_more_Data
310 
                                 , wrST_bram_last_DW
311 
                                 );
312 
 
313 
  -- State variables
314 
  signal pseudo_DDR_wr_State     : bram_wrStates;
315 
 
316 
  --       Block RAM
317 
  signal   pRAM_weA              : std_logic_vector(7 downto 0);
318 
  signal   pRAM_addrA            : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
319 
  signal   pRAM_dinA             : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
320 
  signal   pRAM_doutA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
321 
 
322 
  signal   pRAM_weB              : std_logic_vector(7 downto 0);
323 
  signal   pRAM_addrB            : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
324 
  signal   pRAM_dinB             : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
325 
  signal   pRAM_doutB            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
326 
  signal   pRAM_doutB_r1         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
327 
  signal   pRAM_doutB_shifted    : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
328 
 
329 
  signal   wpipe_qout_lo32b      : std_logic_vector(33-1 downto 0);
330 
  signal   wpipe_QW_Aligned      : std_logic;
331 
  signal   pRAM_AddrA_Inc        : std_logic;
332 
  signal   wpipe_read_valid      : std_logic;
333 
 
334 
 
335 
  --   read State machine
336 
  type bram_rdStates is          ( rdST_bram_RESET
337 
                                 , rdST_bram_IDLE
338 
                                 , rdST_bram_b4_LA
339 
                                 , rdST_bram_LA
340 
--                                 , rdST_bram_b4_Length
341 
--                                 , rdST_bram_Length
342 
--                                 , rdST_bram_b4_Address
343 
--                                 , rdST_bram_Address
344 
                                 , rdST_bram_Data
345 
--                                 , rdST_bram_Data_shift
346 
                                 );
347 
 
348 
  -- State variables
349 
  signal pseudo_DDR_rd_State     : bram_rdStates;
350 
 
351 
  signal rpiped_rd_counter       : std_logic_vector(10-1 downto 0);
352 
  signal rpiped_wEn_b3           : std_logic;
353 
  signal rpiped_wEn_b2           : std_logic;
354 
  signal rpiped_wEn_b1           : std_logic;
355 
  signal rpiped_wr_EOF           : std_logic;
356 
  signal rpipec_read_valid       : std_logic;
357 
  signal rpiped_wr_skew          : std_logic;
358 
  signal rpiped_wr_postpone      : std_logic;
359 
 
360 
  signal simone_debug : std_logic;
361 
 
362 
begin
363 
 
364 
 
365 
  Rst_i              <=  not trn_reset_n;
366 
  DDR_Ready          <=  DDR_Ready_i;
367 
 
368 
  pRAM_doutB_shifted  <= pRAM_doutB_r1(32-1 downto 0) & pRAM_doutB(64-1 downto 32);
369 
 
370 
  --  Delay
371 
  Syn_Shifting_pRAM_doutB:
372 
  process ( trn_clk)
373 
  begin
374 
     if trn_clk'event and trn_clk = '1' then
375 
        pRAM_doutB_r1 <= pRAM_doutB;
376 
     end if;
377 
  end process;
378 
 
379 
  -- -----------------------------------------------
380 
  --
381 
  Syn_DDR_CKE:
382 
  process (trn_clk, Rst_i)
383 
  begin
384 
    if Rst_i = '1' then
385 
       DDR_Ready_i       <=  '0';
386 
    elsif trn_clk'event and trn_clk = '1' then
387 
       DDR_Ready_i       <=  '1';   -- ddr_DCM_locked;
388 
    end if;
389 
  end process;
390 
 
391 
  -- ----------------------------------------------------------------------------
392 
  --
393 
  -- ----------------------------------------------------------------------------
394 
--  DDR_Clock_Generator:
395 
--  DDR_ClkGen
396 
--  PORT MAP(
397 
--           ddr_Clock            =>  ddr_Clock             , -- OUT   std_logic;
398 
--           ddr_Clock_n          =>  ddr_Clock_n           , -- OUT   std_logic;
399 
--           ddr_Clock90          =>  ddr_Clock90           , -- OUT   std_logic;
400 
--           ddr_Clock90_n        =>  ddr_Clock90_n         , -- OUT   std_logic;
401 
--           Clk_ddr_rddata       =>  Clk_ddr_rddata        , -- OUT   std_logic;
402 
--           Clk_ddr_rddata_n     =>  Clk_ddr_rddata_n      , -- OUT   std_logic;
403 
--           ddr_DCM_locked       =>  ddr_DCM_locked        , -- OUT   std_logic;
404 
--
405 
--           clk_in               =>  mem_clk               , -- IN    std_logic;
406 
--           trn_reset_n          =>  trn_reset_n             -- IN    std_logic
407 
--          );
408 
 
409 
 
410 
  -- ----------------------------------------------------------------------------
411 
  --
412 
  -- ----------------------------------------------------------------------------
413 
--  DDR_pipe_write_fifo:
414 
--  asyn_rw_FIFO
415 
--  GENERIC MAP (
416 
--               OUTPUT_REGISTERED    => TRUE
417 
--              )
418 
--  PORT MAP(
419 
--           wClk          =>  trn_clk         ,
420 
--           wEn           =>  wpipe_wEn       ,
421 
--           Din           =>  wpipe_Din       ,
422 
--           aFull         =>  wpipe_aFull     ,
423 
--           Full          =>  wpipe_Full      ,
424 
--
425 
--           rClk          =>  ddr_Clock       ,  -- ddr_Clock_n     ,
426 
--           rEn           =>  wpipe_rEn       ,
427 
--           Qout          =>  wpipe_Qout      ,
428 
--           aEmpty        =>  wpipe_aEmpty    ,
429 
--           Empty         =>  wpipe_Empty     ,
430 
--
431 
--           Rst           =>  Rst_i
432 
--          );
433 
 
434 
--  DDR_pipe_write_fifo:
435 
--  asyn_rw_FIFO72
436 
--  PORT MAP(
437 
--           wClk          =>  trn_clk       ,
438 
--           wEn           =>  wpipe_wEn     ,
439 
--           Din           =>  wpipe_Din     ,
440 
--           aFull         =>  wpipe_aFull   ,
441 
--           Full          =>  open          ,
442 
--
443 
--           rClk          =>  ddr_Clock     ,
444 
--           rEn           =>  wpipe_rEn     ,
445 
--           Qout          =>  wpipe_Qout    ,
446 
--           aEmpty        =>  open          ,
447 
--           Empty         =>  wpipe_Empty   ,
448 
--
449 
--           Rst           =>  Rst_i
450 
--          );
451 
 
452 
  DDR_pipe_write_fifo:
453 
  v6_prime_fifo_plain
454 
  PORT MAP(
455 
    wr_clk       =>  trn_clk      , -- IN  std_logic;
456 
    wr_en        =>  wpipe_wEn    , -- IN  std_logic;
457 
    din          =>  wpipe_Din    , -- IN  std_logic_VECTOR(35 downto 0);
458 
    prog_full    =>  wpipe_aFull  , -- OUT std_logic;
459 
    full         =>  wpipe_Full   , -- OUT std_logic;
460 
 
461 
    rd_clk       =>  trn_clk    , -- IN  std_logic;
462 
    rd_en        =>  wpipe_rEn    , -- IN  std_logic;
463 
    dout         =>  wpipe_Qout   , -- OUT std_logic_VECTOR(35 downto 0);
464 
    empty        =>  wpipe_Empty  , -- OUT std_logic;
465 
 
466 
    rst          =>  Rst_i          -- IN  std_logic
467 
    );
468 
 
469 
 
470 
  wpipe_wEn              <=  DDR_wr_v;
471 
  wpipe_Din              <=  DDR_wr_Mask & DDR_wr_Shift & '0' & DDR_wr_sof & DDR_wr_eof & DDR_wr_Cross_Row & DDR_wr_FA & DDR_wr_din;
472 
  DDR_wr_full            <=  wpipe_aFull;
473 
  Sim_Zeichen            <=  simone_debug; --S wpipe_Empty;
474 
 
475 
 
476 
  Syn_DDR_wrD_Cross_Row:
477 
  process (trn_clk)
478 
  begin
479 
    if trn_clk'event and trn_clk = '1' then
480 
       DDR_wr_din_r1(64-1 downto 10)     <= (OTHERS=>'0');
481 
       DDR_wr_din_r1( 9 downto  0)     <= DDR_wr_din(9 downto  0) - "100";
482 
    end if;
483 
  end process;
484 
 
485 
  DDR_write_ALC      <= (DDR_wr_din_r1(10 downto 2) &"00") + ('0' & DDR_wr_din(9 downto 2) &"00");
486 
  DDR_wr_Cross_Row   <= '0';   -- DDR_write_ALC(10);
487 
 
488 
  -- ----------------------------------------------------------------------------
489 
  --
490 
  -- ----------------------------------------------------------------------------
491 
 
492 
--  DDR_pipe_read_C_fifo:
493 
--  asyn_rw_FIFO
494 
--  GENERIC MAP (
495 
--               OUTPUT_REGISTERED    => TRUE
496 
--              )
497 
--  PORT MAP(
498 
--           wClk          =>  trn_clk         ,
499 
--           wEn           =>  rpipec_wEn      ,
500 
--           Din           =>  rpipec_Din      ,
501 
--           aFull         =>  rpipec_aFull    ,
502 
--           Full          =>  rpipec_Full     ,
503 
--
504 
--           rClk          =>  ddr_Clock       ,  -- ddr_Clock_n     ,
505 
--           rEn           =>  rpipec_rEn      ,
506 
--           Qout          =>  rpipec_Qout     ,
507 
--           aEmpty        =>  rpipec_aEmpty   ,
508 
--           Empty         =>  rpipec_Empty    ,
509 
--
510 
--           Rst           =>  Rst_i
511 
--          );
512 
--
513 
 
514 
--  DDR_pipe_read_C_fifo:
515 
--  asyn_rw_FIFO72
516 
--  PORT MAP(
517 
--           wClk          =>  trn_clk       ,
518 
--           wEn           =>  rpipec_wEn     ,
519 
--           Din           =>  rpipec_Din     ,
520 
--           aFull         =>  rpipec_aFull   ,
521 
--           Full          =>  open          ,
522 
--
523 
--           rClk          =>  ddr_Clock     ,
524 
--           rEn           =>  rpipec_rEn     ,
525 
--           Qout          =>  rpipec_Qout    ,
526 
--           aEmpty        =>  open          ,
527 
--           Empty         =>  rpipec_Empty   ,
528 
--
529 
--           Rst           =>  Rst_i
530 
--          );
531 
 
532 
  DDR_pipe_read_C_fifo:
533 
  v6_prime_fifo_plain
534 
  PORT MAP(
535 
    wr_clk       =>  trn_clk        , -- IN  std_logic;
536 
    wr_en        =>  rpipec_wEn     , -- IN  std_logic;
537 
    din          =>  rpipec_Din     , -- IN  std_logic_VECTOR(35 downto 0);
538 
    prog_full    =>  rpipec_aFull   , -- OUT std_logic;
539 
    full         =>  open,   --rpipec_Full    , -- OUT std_logic;
540 
 
541 
    rd_clk       =>  trn_clk      , -- IN  std_logic;
542 
    rd_en        =>  rpipec_rEn     , -- IN  std_logic;
543 
    dout         =>  rpipec_Qout    , -- OUT std_logic_VECTOR(35 downto 0);
544 
    empty        =>  rpipec_Empty   , -- OUT std_logic;
545 
 
546 
    rst          =>  Rst_i            -- IN  std_logic
547 
    );
548 
 
549 
 
550 
  rpipec_wEn             <=  DDR_rdc_v;
551 
  rpipec_Din             <=  "00" & DDR_rdc_Shift & '0' & DDR_rdc_sof & DDR_rdc_eof & DDR_rd_Cross_Row & DDR_rdc_FA & DDR_rdc_din;
552 
  DDR_rdc_full           <=  rpipec_aFull;
553 
 
554 
 
555 
  Syn_DDR_rdC_Cross_Row:
556 
  process (trn_clk)
557 
  begin
558 
    if trn_clk'event and trn_clk = '1' then
559 
       DDR_rdc_din_r1(64-1 downto 10)   <= (OTHERS=>'0');
560 
       DDR_rdc_din_r1( 9 downto  0)     <= DDR_rdc_din(9 downto  0) - "100";
561 
    end if;
562 
  end process;
563 
 
564 
  DDR_read_ALC       <= (DDR_rdc_din_r1(10 downto 2) &"00") + ('0' & DDR_rdc_din(9 downto 2) &"00");
565 
  DDR_rd_Cross_Row   <= '0';   -- DDR_read_ALC(10);
566 
 
567 
  -- ----------------------------------------------------------------------------
568 
  --
569 
  -- ----------------------------------------------------------------------------
570 
--  DDR_pipe_read_D_fifo:
571 
--  asyn_rw_FIFO
572 
--  GENERIC MAP (
573 
--               OUTPUT_REGISTERED    => TRUE
574 
--              )
575 
--  PORT MAP(
576 
--           wClk          =>  ddr_Clock,       -- Clk_ddr_rddata  ,  -- ddr_Clock       ,  -- ddr_Clock_n     ,
577 
--           wEn           =>  rpiped_wEn      ,
578 
--           Din           =>  rpiped_Din      ,
579 
--           aFull         =>  rpiped_aFull    ,
580 
--           Full          =>  rpiped_Full     ,
581 
--
582 
--           rClk          =>  trn_clk         ,
583 
--           rEn           =>  DDR_FIFO_RdEn   ,  -- rpiped_rEn      ,
584 
--           Qout          =>  rpiped_Qout     ,
585 
--           aEmpty        =>  open            ,  -- rpiped_aEmpty   ,
586 
--           Empty         =>  DDR_FIFO_Empty  ,  -- rpiped_Empty    ,
587 
--
588 
--           Rst           =>  Rst_i
589 
--          );
590 
 
591 
--  DDR_pipe_read_D_fifo:
592 
--  asyn_rw_FIFO72
593 
--  PORT MAP(
594 
--           wClk          =>  ddr_Clock       ,
595 
--           wEn           =>  rpiped_wEn     ,
596 
--           Din           =>  rpiped_Din     ,
597 
--           aFull         =>  rpiped_aFull   ,
598 
--           Full          =>  open          ,
599 
--
600 
--           rClk          =>  trn_clk     ,
601 
--           rEn           =>  DDR_FIFO_RdEn     ,
602 
--           Qout          =>  rpiped_Qout    ,
603 
--           aEmpty        =>  open          ,
604 
--           Empty         =>  DDR_FIFO_Empty   ,
605 
--
606 
--           Rst           =>  Rst_i
607 
--          );
608 
 
609 
  DDR_pipe_read_D_fifo:
610 
  v6_prime_fifo_plain
611 
  PORT MAP(
612 
    wr_clk       =>  trn_clk      , -- IN  std_logic;
613 
    wr_en        =>  rpiped_wEn      , -- IN  std_logic;
614 
    din          =>  rpiped_Din      , -- IN  std_logic_VECTOR(35 downto 0);
615 
    prog_full    =>  rpiped_aFull    , -- OUT std_logic;
616 
    full         =>  open,    -- rpiped_Full     , -- OUT std_logic;
617 
 
618 
    rd_clk       =>  trn_clk         , -- IN  std_logic;
619 
    rd_en        =>  DDR_FIFO_RdEn   , -- IN  std_logic;
620 
    dout         =>  rpiped_Qout     , -- OUT std_logic_VECTOR(35 downto 0);
621 
    empty        =>  DDR_FIFO_Empty  , -- OUT std_logic;
622 
 
623 
    rst          =>  Rst_i             -- IN  std_logic
624 
    );
625 
 
626 
 
627 
    DDR_FIFO_RdQout      <=  rpiped_Qout(C_DBUS_WIDTH-1 downto 0);
628 
 
629 
 
630 
 
631 
    -- -------------------------------------------------
632 
    -- pkt_RAM instantiate
633 
    --
634 
    pkt_RAM:
635 
    v6_bram4096x64
636 
      port map (
637 
         clka      =>    trn_clk  ,
638 
         addra     =>    pRAM_addrA ,
639 
         wea       =>    pRAM_weA   ,
640 
         dina      =>    pRAM_dinA  ,
641 
         douta     =>    pRAM_doutA ,
642 
 
643 
         clkb      =>    trn_clk  ,
644 
         addrb     =>    pRAM_addrB ,
645 
         web       =>    pRAM_weB   ,
646 
         dinb      =>    pRAM_dinB  ,
647 
         doutb     =>    pRAM_doutB
648 
       );
649 
 
650 
    pRAM_weB       <= X"00";
651 
    pRAM_dinB      <= (Others =>'0');
652 
 
653 
 
654 
 
655 
 
656 
 
657 
 
658 
-- ------------------------------------------------
659 
-- write States synchronous
660 
--
661 
   Syn_Pseudo_DDR_wr_States:
662 
   process ( trn_clk, trn_reset_n)
663 
   begin
664 
      if trn_reset_n = '0' then
665 
         pseudo_DDR_wr_State   <= wrST_bram_RESET;
666 
         pRAM_addrA            <= (OTHERS=>'1');
667 
         pRAM_weA              <= (OTHERS=>'0');
668 
         pRAM_dinA             <= (OTHERS=>'0');
669 
         wpipe_qout_lo32b      <= (OTHERS=>'0');
670 
         wpipe_QW_Aligned      <= '1';
671 
         pRAM_AddrA_Inc        <= '1';
672 
 
673 
      elsif trn_clk'event and trn_clk = '1' then
674 
 
675 
        case pseudo_DDR_wr_State  is
676 
 
677 
          when wrST_bram_RESET =>
678 
             pseudo_DDR_wr_State   <= wrST_bram_IDLE;
679 
             pRAM_addrA            <= (OTHERS=>'1');
680 
             wpipe_QW_Aligned      <= '1';
681 
             wpipe_qout_lo32b      <= (OTHERS=>'0');
682 
             pRAM_weA              <= (OTHERS=>'0');
683 
             pRAM_dinA             <= (OTHERS=>'0');
684 
             pRAM_AddrA_Inc        <= '1';
685 
 
686 
          when wrST_bram_IDLE =>
687 
             pRAM_addrA            <= wpipe_Qout(14 downto 3);
688 
             pRAM_AddrA_Inc        <= wpipe_Qout(2);
689 
             wpipe_QW_Aligned      <= not wpipe_Qout(69);
690 
             wpipe_qout_lo32b      <= (32=>'1', OTHERS=>'0');
691 
             pRAM_weA              <= (OTHERS=>'0');
692 
             pRAM_dinA             <= pRAM_dinA;
693 
             if wpipe_read_valid = '1' then
694 
               pseudo_DDR_wr_State   <= wrST_bram_1st_Data;  -- wrST_bram_Address;
695 
             else
696 
               pseudo_DDR_wr_State   <= wrST_bram_IDLE;
697 
             end if;
698 
 
699 
 
700 
          when wrST_bram_1st_Data =>
701 
             pRAM_addrA          <= pRAM_addrA;
702 
             if wpipe_read_valid = '0' then
703 
               pseudo_DDR_wr_State <= wrST_bram_1st_Data;
704 
               pRAM_weA            <= (OTHERS=>'0'); --pRAM_weA;
705 
               pRAM_dinA           <= pRAM_dinA;
706 
             elsif wpipe_Qout(66)='1' then   -- eof
707 
                if wpipe_QW_Aligned='1' then
708 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
709 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
710 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
711 
                                             );
712 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
713 
                elsif wpipe_Qout(70)='1' then     -- mask(0)
714 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
715 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
716 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
717 
                                             );
718 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
719 
                elsif wpipe_Qout(71)='1' then     -- mask(1)
720 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
721 
                  pRAM_weA            <= X"F0";
722 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
723 
                else
724 
                  pseudo_DDR_wr_State <= wrST_bram_last_DW;
725 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
726 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
727 
                                             );
728 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
729 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
730 
                end if;
731 
             else
732 
                if wpipe_QW_Aligned='1' then
733 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
734 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
735 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
736 
                                             );
737 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
738 
                elsif pRAM_AddrA_Inc='1' then
739 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
740 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
741 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
742 
                                             );
743 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
744 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
745 
                else
746 
                  pseudo_DDR_wr_State <= wrST_bram_1st_Data;
747 
                  pRAM_AddrA_Inc      <= '1';
748 
                  pRAM_weA            <= X"00";
749 
                  pRAM_dinA           <= pRAM_dinA;
750 
                  wpipe_qout_lo32b    <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
751 
                end if;
752 
             end if;
753 
 
754 
          when wrST_bram_more_Data =>
755 
             if wpipe_read_valid = '0' then
756 
               pseudo_DDR_wr_State <= wrST_bram_more_Data;  -- wrST_bram_1st_Data;
757 
               pRAM_weA            <= (OTHERS=>'0'); --pRAM_weA;
758 
               pRAM_addrA          <= pRAM_addrA;
759 
               pRAM_dinA           <= pRAM_dinA;
760 
             elsif wpipe_Qout(66)='1' then   -- eof
761 
                if wpipe_QW_Aligned='1' then
762 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
763 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
764 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
765 
                                             );
766 
                  pRAM_addrA          <= pRAM_addrA + '1';
767 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
768 
                elsif wpipe_Qout(70)='1' then  -- mask(0)
769 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
770 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
771 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
772 
                                             );
773 
                  pRAM_addrA          <= pRAM_addrA + '1';
774 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
775 
                else
776 
                  pseudo_DDR_wr_State <= wrST_bram_last_DW;
777 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
778 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
779 
                                             );
780 
                  pRAM_addrA          <= pRAM_addrA + '1';
781 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
782 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
783 
                end if;
784 
             else
785 
                if wpipe_QW_Aligned='1' then
786 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
787 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
788 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
789 
                                             );
790 
                  pRAM_addrA          <= pRAM_addrA + '1';
791 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
792 
                else
793 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
794 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
795 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
796 
                                             );
797 
                  pRAM_addrA          <= pRAM_addrA + '1';
798 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
799 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
800 
                end if;
801 
             end if;
802 
 
803 
 
804 
          when wrST_bram_last_DW =>
805 
--             pseudo_DDR_wr_State   <= wrST_bram_IDLE;
806 
             pRAM_weA              <= X"F0";
807 
             pRAM_addrA            <= pRAM_addrA + '1';
808 
             pRAM_dinA             <= wpipe_qout_lo32b(32-1 downto 0) & X"00000000";
809 
             if wpipe_read_valid = '1' then
810 
               pseudo_DDR_wr_State         <= wrST_bram_1st_Data_b2b;  -- wrST_bram_Address;
811 
               wpipe_Qout_latch            <= wpipe_Qout;
812 
             else
813 
               pseudo_DDR_wr_State         <= wrST_bram_IDLE;
814 
               wpipe_Qout_latch            <= wpipe_Qout;
815 
             end if;
816 
 
817 
 
818 
          when wrST_bram_1st_Data_b2b =>
819 
             pRAM_addrA            <= wpipe_Qout_latch(14 downto 3);
820 
             wpipe_QW_Aligned      <= not wpipe_Qout_latch(69);
821 
             if wpipe_read_valid = '0' then
822 
               pseudo_DDR_wr_State <= wrST_bram_1st_Data;
823 
               pRAM_weA            <= (OTHERS=>'0'); --pRAM_weA;
824 
               pRAM_dinA           <= pRAM_dinA;
825 
               pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
826 
               wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
827 
             elsif wpipe_Qout(66)='1' then   -- eof
828 
                if wpipe_Qout_latch(69)='0' then   -- wpipe_QW_Aligned
829 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
830 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
831 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
832 
                                             );
833 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
834 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
835 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
836 
                elsif wpipe_Qout(70)='1' then     -- mask(0)
837 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
838 
                  pRAM_weA            <= not ( X"f"
839 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
840 
                                             );
841 
                  pRAM_dinA           <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
842 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
843 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
844 
                elsif wpipe_Qout(71)='1' then     -- mask(1)
845 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
846 
                  pRAM_weA            <= X"F0";
847 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
848 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
849 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
850 
                else
851 
                  pseudo_DDR_wr_State <= wrST_bram_last_DW;
852 
                  pRAM_weA            <= not ( X"f"
853 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
854 
                                             );
855 
                  pRAM_dinA           <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
856 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
857 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
858 
                end if;
859 
             else
860 
                if wpipe_Qout_latch(69)='0' then    -- wpipe_QW_Aligned
861 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
862 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
863 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
864 
                                             );
865 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
866 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
867 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
868 
                elsif wpipe_Qout_latch(2)='1' then   -- pRAM_AddrA_Inc
869 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
870 
                  pRAM_weA            <= not ( X"f"
871 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
872 
                                             );
873 
                  pRAM_dinA           <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
874 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
875 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
876 
                else
877 
                  pseudo_DDR_wr_State <= wrST_bram_1st_Data;
878 
                  pRAM_AddrA_Inc      <= '1';
879 
                  pRAM_weA            <= X"00";
880 
                  pRAM_dinA           <= pRAM_dinA;
881 
                  wpipe_qout_lo32b    <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
882 
                end if;
883 
             end if;
884 
 
885 
 
886 
          when OTHERS =>
887 
             pseudo_DDR_wr_State   <= wrST_bram_RESET;
888 
             pRAM_addrA            <= (OTHERS=>'1');
889 
             pRAM_weA              <= (OTHERS=>'0');
890 
             pRAM_dinA             <= (OTHERS=>'0');
891 
             wpipe_qout_lo32b      <= (OTHERS=>'0');
892 
             wpipe_QW_Aligned      <= '1';
893 
             pRAM_AddrA_Inc        <= '1';
894 
 
895 
        end case;
896 
 
897 
      end if;
898 
   end process;
899 
 
900 
 
901 
   --
902 
   Syn_wPipe_read:
903 
   process ( trn_clk, DDR_Ready_i)
904 
   begin
905 
      if DDR_Ready_i = '0' then
906 
         wpipe_rEn         <= '0';
907 
         wpipe_read_valid  <= '0';
908 
 
909 
      elsif trn_clk'event and trn_clk = '1' then
910 
 
911 
         wpipe_rEn         <= '1';
912 
         wpipe_read_valid  <= wpipe_rEn and not wpipe_Empty;
913 
 
914 
      end if;
915 
   end process;
916 
 
917 
 
918 
 
919 
   --
920 
   Syn_rPipeC_read:
921 
   process ( trn_clk, DDR_Ready_i)
922 
   begin
923 
      if DDR_Ready_i = '0' then
924 
         rpipec_read_valid    <= '0';
925 
         rpiped_wr_postpone   <= '0';
926 
         rpiped_wr_skew       <= '0';
927 
 
928 
      elsif trn_clk'event and trn_clk = '1' then
929 
 
930 
         rpipec_read_valid  <= rpipec_rEn and not rpipec_Empty;
931 
         if rpipec_read_valid='1' then
932 
            rpiped_wr_postpone  <= rpipec_Qout(2) and not rpipec_Qout(69);
933 
            rpiped_wr_skew      <= rpipec_Qout(69) xor rpipec_Qout(2);
934 
         else
935 
            rpiped_wr_postpone  <= rpiped_wr_postpone;
936 
            rpiped_wr_skew      <= rpiped_wr_skew;
937 
         end if;
938 
 
939 
      end if;
940 
   end process;
941 
 
942 
-- ------------------------------------------------
943 
-- Read States synchronous
944 
--
945 
   Syn_Pseudo_DDR_rd_States:
946 
   process ( trn_clk, DDR_Ready_i)
947 
   begin
948 
      if DDR_Ready_i = '0' then
949 
         pseudo_DDR_rd_State   <= rdST_bram_RESET;
950 
         rpipec_rEn            <= '0';
951 
         pRAM_addrB            <= (OTHERS=>'1');
952 
         rpiped_rd_counter     <= (OTHERS=>'0');
953 
         rpiped_wEn_b3         <= '0';
954 
         rpiped_wr_EOF         <= '0';
955 
 
956 
      elsif trn_clk'event and trn_clk = '1' then
957 
 
958 
        case pseudo_DDR_rd_State  is
959 
 
960 
          when rdST_bram_RESET =>
961 
             pseudo_DDR_rd_State   <= rdST_bram_IDLE;
962 
             rpipec_rEn            <= '0';
963 
             pRAM_addrB            <= (OTHERS=>'1');
964 
             rpiped_rd_counter     <= (OTHERS=>'0');
965 
             rpiped_wEn_b3         <= '0';
966 
             rpiped_wr_EOF         <= '0';
967 
 
968 
          when rdST_bram_IDLE =>
969 
             pRAM_addrB            <= pRAM_addrB;
970 
             rpiped_rd_counter     <= (OTHERS=>'0');
971 
             rpiped_wEn_b3         <= '0';
972 
             rpiped_wr_EOF         <= '0';
973 
             if rpipec_Empty = '0' then
974 
               rpipec_rEn          <= '1';
975 
               pseudo_DDR_rd_State <= rdST_bram_b4_LA;  --rdST_bram_b4_Length;
976 
             else
977 
               rpipec_rEn          <= '0';
978 
               pseudo_DDR_rd_State <= rdST_bram_IDLE;
979 
             end if;
980 
 
981 
          when rdST_bram_b4_LA =>
982 
             pRAM_addrB            <= pRAM_addrB;
983 
             rpiped_rd_counter     <= (OTHERS=>'0');
984 
             rpiped_wEn_b3         <= '0';
985 
             rpiped_wr_EOF         <= '0';
986 
             rpipec_rEn            <= '0';
987 
             pseudo_DDR_rd_State   <= rdST_bram_LA;
988 
 
989 
          when rdST_bram_LA =>
990 
             rpipec_rEn            <= '0';
991 
             pRAM_addrB            <= rpipec_Qout(14 downto 3);
992 
             rpiped_wr_EOF         <= '0';
993 
             rpiped_wEn_b3         <= '0';
994 
             if rpipec_Qout(2+32)='1' then
995 
               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + '1';
996 
             elsif rpipec_Qout(2)='1' and rpipec_Qout(69)='1' then
997 
               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + "10";
998 
             elsif rpipec_Qout(2)='0' and rpipec_Qout(69)='1' then
999 
               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + "10";
1000 
             elsif rpipec_Qout(2)='1' and rpipec_Qout(69)='0' then
1001 
               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32);
1002 
             else
1003 
               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32);
1004 
             end if;
1005 
 
1006 
--             elsif rpipec_Qout(2)='1' then
1007 
--               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + "10";
1008 
--             elsif rpipec_Qout(69)='1' then
1009 
--               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + "10";
1010 
--             else
1011 
--               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32);
1012 
--             end if;
1013 
             pseudo_DDR_rd_State   <= rdST_bram_Data;
1014 
 
1015 
 
1016 
          when rdST_bram_Data =>
1017 
             rpipec_rEn            <= '0';
1018 
             if rpiped_rd_counter = CONV_STD_LOGIC_VECTOR(2, 10) then
1019 
               pRAM_addrB            <= pRAM_addrB + '1';
1020 
               rpiped_rd_counter     <= rpiped_rd_counter;
1021 
               rpiped_wEn_b3         <= '1';
1022 
               rpiped_wr_EOF         <= '1';
1023 
               pseudo_DDR_rd_State   <= rdST_bram_IDLE;
1024 
             elsif rpiped_aFull = '1' then
1025 
               pRAM_addrB            <= pRAM_addrB;
1026 
               rpiped_rd_counter     <= rpiped_rd_counter;
1027 
               rpiped_wEn_b3         <= '0';
1028 
               rpiped_wr_EOF         <= '0';
1029 
               pseudo_DDR_rd_State   <= rdST_bram_Data;
1030 
             else
1031 
               pRAM_addrB            <= pRAM_addrB + '1';
1032 
               rpiped_rd_counter     <= rpiped_rd_counter - "10";
1033 
               rpiped_wEn_b3         <= '1';
1034 
               rpiped_wr_EOF         <= '0';
1035 
               pseudo_DDR_rd_State   <= rdST_bram_Data;
1036 
             end if;
1037 
 
1038 
 
1039 
          when OTHERS =>
1040 
               rpipec_rEn            <= '0';
1041 
               pRAM_addrB            <= pRAM_addrB;
1042 
               rpiped_rd_counter     <= rpiped_rd_counter;
1043 
               rpiped_wEn_b3         <= '0';
1044 
               rpiped_wr_EOF         <= '0';
1045 
               pseudo_DDR_rd_State   <= rdST_bram_RESET;
1046 
 
1047 
        end case;
1048 
 
1049 
      end if;
1050 
   end process;
1051 
 
1052 
 
1053 
 
1054 
   Syn_Pseudo_DDR_rdd_write:
1055 
   process ( trn_clk, DDR_Ready_i)
1056 
   begin
1057 
      if DDR_Ready_i = '0' then
1058 
         rpiped_wEn_b1      <= '0';
1059 
         rpiped_wEn_b2      <= '0';
1060 
         rpiped_wEn         <= '0';
1061 
         rpiped_Din         <= (OTHERS=>'0');
1062 
 
1063 
      elsif trn_clk'event and trn_clk = '1' then
1064 
 
1065 
         rpiped_wEn_b2      <= rpiped_wEn_b3;
1066 
         rpiped_wEn_b1      <= rpiped_wEn_b2;
1067 
         if rpiped_wr_skew='1' then
1068 
--           rpiped_wEn         <= rpiped_wEn_b2;
1069 
           rpiped_wEn         <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
1070 
                              or (rpiped_wEn_b1 and rpiped_wr_postpone);
1071 
           rpiped_Din         <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB_shifted;
1072 
         else
1073 
--           rpiped_wEn         <= rpiped_wEn_b2;
1074 
           rpiped_wEn         <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
1075 
                              or (rpiped_wEn_b1 and rpiped_wr_postpone);
1076 
           rpiped_Din         <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB;
1077 
         end if;
1078 
 
1079 
      end if;
1080 
   end process;
1081 
 
1082 
 
1083 
  --
1084 
  DDR_Blinker_Module:
1085 
  DDR_Blink
1086 
  PORT MAP(
1087 
           DDR_Blinker          =>  DDR_Blinker    ,
1088 
 
1089 
           DDR_Write            =>  wpipe_rEn      ,
1090 
           DDR_Read             =>  rpiped_wEn     ,
1091 
           DDR_Both             =>  '0'            ,
1092 
 
1093 
           ddr_Clock            =>  trn_clk      ,
1094 
           DDr_Rst_n            =>  DDR_Ready_i      -- DDR_CKE_i
1095 
          );
1096 
 
1097 
 
1098 
end architecture Behavioral;

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