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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MySource/] [rx_Transact.vhd] - Blame information for rev 13

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Line No. Rev Author Line
1 13 barabba 
----------------------------------------------------------------------------------
2 
-- Company:
3 
-- Engineer:
4 
--
5 
-- Design Name:
6 
-- Module Name:    rx_Transact - Behavioral
7 
-- Project Name:
8 
-- Target Devices:
9 
-- Tool versions:
10 
-- Description:
11 
--
12 
-- Dependencies:
13 
--
14 
-- Revision 1.20 - Memory space repartitioned.   13.07.2007
15 
--
16 
-- Revision 1.10 - x4 timing constraints met.   02.02.2007
17 
--
18 
-- Revision 1.04 - Timing improved.     17.01.2007
19 
--
20 
-- Revision 1.02 - FIFO added.    20.12.2006
21 
--
22 
-- Revision 1.00 - first release. 14.12.2006
23 
--
24 
-- Additional Comments:
25 
--
26 
----------------------------------------------------------------------------------
27 
 
28 
library IEEE;
29 
use IEEE.STD_LOGIC_1164.ALL;
30 
use IEEE.STD_LOGIC_ARITH.ALL;
31 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
32 
 
33 
library work;
34 
use work.abb64Package.all;
35 
 
36 
 
37 
-- Uncomment the following library declaration if instantiating
38 
-- any Xilinx primitives in this code.
39 
--library UNISIM;
40 
--use UNISIM.VComponents.all;
41 
 
42 
entity rx_Transact is
43 
    port (
44 
      -- Common ports
45 
      trn_clk                   : IN  std_logic;
46 
      trn_reset_n               : IN  std_logic;
47 
      trn_lnk_up_n              : IN  std_logic;
48 
 
49 
      -- Transaction receive interface
50 
      trn_rsof_n                : IN  std_logic;
51 
      trn_reof_n                : IN  std_logic;
52 
      trn_rd                    : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
53 
      trn_rrem_n                : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
54 
      trn_rerrfwd_n             : IN  std_logic;
55 
      trn_rsrc_rdy_n            : IN  std_logic;
56 
      trn_rdst_rdy_n            : OUT std_logic;
57 
      trn_rnp_ok_n              : OUT std_logic;
58 
      trn_rsrc_dsc_n            : IN  std_logic;
59 
      trn_rbar_hit_n            : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
60 
--      trn_rfc_ph_av             : IN  std_logic_vector(7 downto 0);
61 
--      trn_rfc_pd_av             : IN  std_logic_vector(11 downto 0);
62 
--      trn_rfc_nph_av            : IN  std_logic_vector(7 downto 0);
63 
--      trn_rfc_npd_av            : IN  std_logic_vector(11 downto 0);
64 
--      trn_rfc_cplh_av           : IN  std_logic_vector(7 downto 0);
65 
--      trn_rfc_cpld_av           : IN  std_logic_vector(11 downto 0);
66 
 
67 
      -- PIO MRd Channel
68 
      pioCplD_Req               : OUT std_logic;
69 
      pioCplD_RE                : IN  std_logic;
70 
      pioCplD_Qout              : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
71 
      pio_FC_stop               : IN  std_logic;
72 
 
73 
      -- downstream MRd Channel
74 
      dsMRd_Req                 : OUT std_logic;
75 
      dsMRd_RE                  : IN  std_logic;
76 
      dsMRd_Qout                : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
77 
 
78 
      -- upstream MWr/MRd Channel
79 
      usTlp_Req                 : OUT std_logic;
80 
      usTlp_RE                  : IN  std_logic;
81 
      usTlp_Qout                : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
82 
      us_FC_stop                : IN  std_logic;
83 
      us_Last_sof               : IN  std_logic;
84 
      us_Last_eof               : IN  std_logic;
85 
 
86 
      -- Irpt Channel
87 
      Irpt_Req                  : OUT std_logic;
88 
      Irpt_RE                   : IN  std_logic;
89 
      Irpt_Qout                 : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
90 
 
91 
      -- Interrupt Interface
92 
                cfg_interrupt_n           : OUT std_logic;
93 
                cfg_interrupt_rdy_n       : IN  std_logic;
94 
                cfg_interrupt_mmenable    : IN  std_logic_VECTOR(2 downto 0);
95 
                cfg_interrupt_msienable   : IN  std_logic;
96 
                cfg_interrupt_di          : OUT std_logic_VECTOR(7 downto 0);
97 
                cfg_interrupt_do          : IN  std_logic_VECTOR(7 downto 0);
98 
                cfg_interrupt_assert_n    : OUT std_logic;
99 
 
100 
      -- Downstream DMA transferred bytes count up
101 
      ds_DMA_Bytes_Add          : OUT std_logic;
102 
      ds_DMA_Bytes              : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
103 
 
104 
      -- --------------------------
105 
      -- Registers
106 
      DMA_ds_PA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
107 
      DMA_ds_HA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
108 
      DMA_ds_BDA                : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
109 
      DMA_ds_Length             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
110 
      DMA_ds_Control            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
111 
      dsDMA_BDA_eq_Null         : IN  std_logic;
112 
      DMA_ds_Status             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
113 
      DMA_ds_Done               : OUT std_logic;
114 
      DMA_ds_Busy               : OUT std_logic;
115 
      DMA_ds_Tout               : OUT std_logic;
116 
 
117 
      -- Calculation in advance, for better timing
118 
      dsHA_is_64b               : IN  std_logic;
119 
      dsBDA_is_64b              : IN  std_logic;
120 
 
121 
      -- Calculation in advance, for better timing
122 
      dsLeng_Hi19b_True         : IN  std_logic;
123 
      dsLeng_Lo7b_True          : IN  std_logic;
124 
 
125 
      --
126 
      dsDMA_Start               : IN  std_logic;
127 
      dsDMA_Stop                : IN  std_logic;
128 
      dsDMA_Start2              : IN  std_logic;
129 
      dsDMA_Stop2               : IN  std_logic;
130 
      dsDMA_Channel_Rst         : IN  std_logic;
131 
      dsDMA_Cmd_Ack             : OUT std_logic;
132 
 
133 
      --
134 
      DMA_us_PA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
135 
      DMA_us_HA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
136 
      DMA_us_BDA                : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
137 
      DMA_us_Length             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
138 
      DMA_us_Control            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
139 
      usDMA_BDA_eq_Null         : IN  std_logic;
140 
      us_MWr_Param_Vec          : IN  std_logic_vector(6-1   downto 0);
141 
      DMA_us_Status             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
142 
      DMA_us_Done               : OUT std_logic;
143 
      DMA_us_Busy               : OUT std_logic;
144 
      DMA_us_Tout               : OUT std_logic;
145 
 
146 
      -- Calculation in advance, for better timing
147 
      usHA_is_64b               : IN  std_logic;
148 
      usBDA_is_64b              : IN  std_logic;
149 
 
150 
      -- Calculation in advance, for better timing
151 
      usLeng_Hi19b_True         : IN  std_logic;
152 
      usLeng_Lo7b_True          : IN  std_logic;
153 
 
154 
      --
155 
      usDMA_Start               : IN  std_logic;
156 
      usDMA_Stop                : IN  std_logic;
157 
      usDMA_Start2              : IN  std_logic;
158 
      usDMA_Stop2               : IN  std_logic;
159 
      usDMA_Channel_Rst         : IN  std_logic;
160 
      usDMA_Cmd_Ack             : OUT std_logic;
161 
 
162 
      MRd_Channel_Rst           : IN  std_logic;
163 
 
164 
      -- to Interrupt module
165 
      Sys_IRQ                   : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
166 
 
167 
 
168 
      -- Event Buffer write port
169 
      eb_FIFO_we                : OUT std_logic;
170 
      eb_FIFO_wsof              : OUT std_logic;
171 
      eb_FIFO_weof              : OUT std_logic;
172 
      eb_FIFO_din               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
173 
 
174 
      eb_FIFO_data_count        : IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
175 
      eb_FIFO_Empty             : IN  std_logic;
176 
      eb_FIFO_Reading           : IN  std_logic;
177 
      pio_reading_status        : OUT std_logic;
178 
 
179 
      Link_Buf_full             : IN  std_logic;
180 
 
181 
      -- Registers Write Port
182 
      Regs_WrEn0                : OUT std_logic;
183 
      Regs_WrMask0              : OUT std_logic_vector(2-1 downto 0);
184 
      Regs_WrAddr0              : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
185 
      Regs_WrDin0               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
186 
 
187 
      Regs_WrEn1                : OUT std_logic;
188 
      Regs_WrMask1              : OUT std_logic_vector(2-1 downto 0);
189 
      Regs_WrAddr1              : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
190 
      Regs_WrDin1               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
191 
 
192 
      -- DDR write port
193 
      DDR_wr_sof_A              : OUT std_logic;
194 
      DDR_wr_eof_A              : OUT std_logic;
195 
      DDR_wr_v_A                : OUT std_logic;
196 
      DDR_wr_FA_A               : OUT std_logic;
197 
      DDR_wr_Shift_A            : OUT std_logic;
198 
      DDR_wr_Mask_A             : OUT std_logic_vector(2-1 downto 0);
199 
      DDR_wr_din_A              : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
200 
 
201 
      DDR_wr_sof_B              : OUT std_logic;
202 
      DDR_wr_eof_B              : OUT std_logic;
203 
      DDR_wr_v_B                : OUT std_logic;
204 
      DDR_wr_FA_B               : OUT std_logic;
205 
      DDR_wr_Shift_B            : OUT std_logic;
206 
      DDR_wr_Mask_B             : OUT std_logic_vector(2-1 downto 0);
207 
      DDR_wr_din_B              : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
208 
 
209 
      DDR_wr_full               : IN  std_logic;
210 
 
211 
      -- Data generator table write
212 
      tab_we                    : OUT std_logic_vector(2-1 downto 0);
213 
      tab_wa                    : OUT std_logic_vector(12-1 downto 0);
214 
      tab_wd                    : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
215 
 
216 
      -- Interrupt generator signals
217 
      IG_Reset                  : IN  std_logic;
218 
      IG_Host_Clear             : IN  std_logic;
219 
      IG_Latency                : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
220 
      IG_Num_Assert             : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
221 
      IG_Num_Deassert           : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
222 
      IG_Asserting              : OUT std_logic;
223 
 
224 
      -- Additional
225 
      cfg_dcommand              : IN  std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
226 
      localID                   : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
227 
    );
228 
 
229 
end entity rx_Transact;
230 
 
231 
 
232 
architecture Behavioral of rx_Transact is
233 
 
234 
   signal  eb_FIFO_we_i         : std_logic;
235 
   signal  eb_FIFO_wsof_i       : std_logic;
236 
   signal  eb_FIFO_weof_i       : std_logic;
237 
   signal  eb_FIFO_din_i        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
238 
 
239 
    ------------------------------------------------------------------
240 
    --  Rx input delay
241 
    --  some calculation in advance, to achieve better timing
242 
    --
243 
    COMPONENT
244 
    RxIn_Delay
245 
    PORT (
246 
      -- Common ports
247 
      trn_clk                   : IN  std_logic;
248 
      trn_reset_n               : IN  std_logic;
249 
      trn_lnk_up_n              : IN  std_logic;
250 
 
251 
      -- Transaction receive interface
252 
      trn_rsof_n                : IN  std_logic;
253 
      trn_reof_n                : IN  std_logic;
254 
      trn_rd                    : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
255 
      trn_rrem_n                : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
256 
      trn_rerrfwd_n             : IN  std_logic;
257 
      trn_rsrc_rdy_n            : IN  std_logic;
258 
      trn_rsrc_dsc_n            : IN  std_logic;
259 
      trn_rbar_hit_n            : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
260 
      trn_rdst_rdy_n            : OUT std_logic;
261 
      Pool_wrBuf_full           : IN  std_logic;
262 
      Link_Buf_full             : IN  std_logic;
263 
 
264 
      -- Delayed
265 
      trn_rsof_n_dly            : OUT std_logic;
266 
      trn_reof_n_dly            : OUT std_logic;
267 
      trn_rd_dly                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
268 
      trn_rrem_n_dly            : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
269 
      trn_rerrfwd_n_dly         : OUT std_logic;
270 
      trn_rsrc_rdy_n_dly        : OUT std_logic;
271 
      trn_rdst_rdy_n_dly        : OUT std_logic;
272 
      trn_rsrc_dsc_n_dly        : OUT std_logic;
273 
      trn_rbar_hit_n_dly        : OUT std_logic_vector(C_BAR_NUMBER-1 downto 0);
274 
 
275 
      -- TLP resolution
276 
      IORd_Type                 : OUT std_logic;
277 
      IOWr_Type                 : OUT std_logic;
278 
      MRd_Type                  : OUT std_logic_vector(3 downto 0);
279 
      MWr_Type                  : OUT std_logic_vector(1 downto 0);
280 
      CplD_Type                 : OUT std_logic_vector(3 downto 0);
281 
 
282 
      -- From Cpl/D channel
283 
      usDMA_dex_Tag             : IN  std_logic_vector(C_TAG_WIDTH-1 downto 0);
284 
      dsDMA_dex_Tag             : IN  std_logic_vector(C_TAG_WIDTH-1 downto 0);
285 
 
286 
      -- To Memory request process modules
287 
      Tlp_straddles_4KB         : OUT std_logic;
288 
 
289 
      -- To Cpl/D channel
290 
      Tlp_has_4KB               : OUT std_logic;
291 
      Tlp_has_1DW               : OUT std_logic;
292 
      CplD_is_the_Last          : OUT std_logic;
293 
      CplD_on_Pool              : OUT std_logic;
294 
      CplD_on_EB                : OUT std_logic;
295 
      Req_ID_Match              : OUT std_logic;
296 
      usDex_Tag_Matched         : OUT std_logic;
297 
      dsDex_Tag_Matched         : OUT std_logic;
298 
      CplD_Tag                  : OUT std_logic_vector(C_TAG_WIDTH-1 downto  0);
299 
 
300 
      -- Additional
301 
      cfg_dcommand              : IN  std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
302 
      localID                   : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
303 
    );
304 
    END COMPONENT;
305 
 
306 
   -- One clock delayed
307 
   signal   trn_rsof_n_dly      :  std_logic;
308 
   signal   trn_reof_n_dly      :  std_logic;
309 
   signal   trn_rd_dly          :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
310 
   signal   trn_rrem_n_dly      :  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
311 
   signal   trn_rerrfwd_n_dly   :  std_logic;
312 
   signal   trn_rsrc_rdy_n_dly  :  std_logic;
313 
   signal   trn_rdst_rdy_n_dly  :  std_logic;
314 
   signal   trn_rsrc_dsc_n_dly  :  std_logic;
315 
   signal   trn_rbar_hit_n_dly  :  std_logic_vector(C_BAR_NUMBER-1 downto 0);
316 
 
317 
   -- TLP types
318 
   signal   IORd_Type           :  std_logic;
319 
   signal   IOWr_Type           :  std_logic;
320 
   signal   MRd_Type            :  std_logic_vector(3 downto 0);
321 
   signal   MWr_Type            :  std_logic_vector(1 downto 0);
322 
   signal   CplD_Type           :  std_logic_vector(3 downto 0);
323 
 
324 
   signal   Tlp_straddles_4KB   :  std_logic;
325 
 
326 
   -- To Cpl/D channel
327 
   signal   Tlp_has_4KB         :  std_logic;
328 
   signal   Tlp_has_1DW         :  std_logic;
329 
   signal   CplD_is_the_Last    :  std_logic;
330 
   signal   CplD_on_Pool        :  std_logic;
331 
   signal   CplD_on_EB          :  std_logic;
332 
   signal   Req_ID_Match        :  std_logic;
333 
   signal   usDex_Tag_Matched   :  std_logic;
334 
   signal   dsDex_Tag_Matched   :  std_logic;
335 
   signal   CplD_Tag            :  std_logic_vector(C_TAG_WIDTH-1 downto  0);
336 
 
337 
 
338 
   ------------------------------------------------------------------
339 
   --  MRd TLP processing
340 
   --   contains channel buffer for PIO Completions
341 
   --
342 
        COMPONENT
343 
   rx_MRd_Transact
344 
        PORT(
345 
                trn_rsof_n                : IN  std_logic;
346 
                trn_reof_n                : IN  std_logic;
347 
                trn_rd                    : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
348 
      trn_rrem_n                : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
349 
--              trn_rdst_rdy_n            : OUT std_logic;
350 
                trn_rnp_ok_n              : OUT std_logic;  -----------------
351 
                trn_rerrfwd_n             : IN  std_logic;
352 
                trn_rsrc_rdy_n            : IN  std_logic;
353 
                trn_rsrc_dsc_n            : IN  std_logic;
354 
                trn_rbar_hit_n            : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
355 
 
356 
      IORd_Type                 : IN  std_logic;
357 
      MRd_Type                  : IN  std_logic_vector(3 downto 0);
358 
      Tlp_straddles_4KB         : IN  std_logic;
359 
 
360 
                pioCplD_RE                : IN  std_logic;
361 
                pioCplD_Req               : OUT std_logic;
362 
                pioCplD_Qout              : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
363 
      FIFO_Empty                : IN  std_logic;
364 
      FIFO_Reading              : IN  std_logic;
365 
      pio_FC_stop               : IN  std_logic;
366 
      pio_reading_status        : OUT std_logic;
367 
 
368 
      Channel_Rst               : IN  std_logic;
369 
 
370 
                trn_clk                   : IN  std_logic;
371 
                trn_reset_n               : IN  std_logic;
372 
                trn_lnk_up_n              : IN  std_logic
373 
                );
374 
        END COMPONENT;
375 
 
376 
 
377 
   ------------------------------------------------------------------
378 
   --  MWr TLP processing
379 
   --
380 
        COMPONENT
381 
   rx_MWr_Transact
382 
        PORT(
383 
      --
384 
                trn_rsof_n                : IN  std_logic;
385 
                trn_reof_n                : IN  std_logic;
386 
                trn_rd                    : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
387 
      trn_rrem_n                : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
388 
                trn_rdst_rdy_n            : IN  std_logic;  -- !!
389 
                trn_rerrfwd_n             : IN  std_logic;
390 
                trn_rsrc_rdy_n            : IN  std_logic;
391 
                trn_rsrc_dsc_n            : IN  std_logic;
392 
                trn_rbar_hit_n            : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
393 
 
394 
      IOWr_Type                 : IN  std_logic;
395 
      MWr_Type                  : IN  std_logic_vector(1 downto 0);
396 
      Tlp_straddles_4KB         : IN  std_logic;
397 
      Tlp_has_4KB               : IN  std_logic;
398 
 
399 
 
400 
      -- Event Buffer write port
401 
      eb_FIFO_we                : OUT std_logic;
402 
      eb_FIFO_wsof              : OUT std_logic;
403 
      eb_FIFO_weof              : OUT std_logic;
404 
      eb_FIFO_din               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
405 
 
406 
      -- Registers Write Port
407 
      Regs_WrEn                 : OUT std_logic;
408 
      Regs_WrMask               : OUT std_logic_vector(2-1 downto 0);
409 
      Regs_WrAddr               : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
410 
      Regs_WrDin                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
411 
 
412 
      -- DDR write port
413 
      DDR_wr_sof                : OUT std_logic;
414 
      DDR_wr_eof                : OUT std_logic;
415 
      DDR_wr_v                  : OUT std_logic;
416 
      DDR_wr_FA                 : OUT std_logic;
417 
      DDR_wr_Shift              : OUT std_logic;
418 
      DDR_wr_Mask               : OUT std_logic_vector(2-1 downto 0);
419 
      DDR_wr_din                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
420 
      DDR_wr_full               : IN  std_logic;
421 
 
422 
      -- Data generator table write
423 
      tab_we             : OUT std_logic_vector(2-1 downto 0);
424 
      tab_wa             : OUT std_logic_vector(12-1 downto 0);
425 
      tab_wd             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
426 
 
427 
      -- Common
428 
                trn_clk                   : IN  std_logic;
429 
                trn_reset_n               : IN  std_logic;
430 
                trn_lnk_up_n              : IN  std_logic
431 
 
432 
                );
433 
        END COMPONENT;
434 
 
435 
   signal  eb_FIFO_we_MWr       : std_logic;
436 
   signal  eb_FIFO_wsof_MWr     : std_logic;
437 
   signal  eb_FIFO_weof_MWr     : std_logic;
438 
   signal  eb_FIFO_din_MWr      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
439 
 
440 
 
441 
   ------------------------------------------------------------------
442 
   --  Cpl/D TLP processing
443 
   --
444 
        COMPONENT
445 
   rx_CplD_Transact
446 
        PORT(
447 
                trn_rsof_n                : IN  std_logic;
448 
                trn_reof_n                : IN  std_logic;
449 
                trn_rd                    : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
450 
      trn_rrem_n                : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
451 
                trn_rdst_rdy_n            : IN  std_logic;
452 
                trn_rerrfwd_n             : IN  std_logic;
453 
                trn_rsrc_rdy_n            : IN  std_logic;
454 
                trn_rsrc_dsc_n            : IN  std_logic;
455 
                trn_rbar_hit_n            : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
456 
 
457 
      CplD_Type                 : IN  std_logic_vector(3 downto 0);
458 
 
459 
      Req_ID_Match              : IN  std_logic;
460 
      usDex_Tag_Matched         : IN  std_logic;
461 
      dsDex_Tag_Matched         : IN  std_logic;
462 
 
463 
      Tlp_has_4KB               : IN  std_logic;
464 
      Tlp_has_1DW               : IN  std_logic;
465 
      CplD_is_the_Last          : IN  std_logic;
466 
      CplD_on_Pool              : IN  std_logic;
467 
      CplD_on_EB                : IN  std_logic;
468 
      CplD_Tag                  : IN  std_logic_vector(C_TAG_WIDTH-1 downto  0);
469 
      FC_pop                    : OUT std_logic;
470 
 
471 
      -- Downstream DMA transferred bytes count up
472 
      ds_DMA_Bytes_Add          : OUT std_logic;
473 
      ds_DMA_Bytes              : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
474 
 
475 
      -- for descriptor of the downstream DMA
476 
      dsDMA_Dex_Tag             : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
477 
 
478 
      -- Downstream Handshake Signals with ds Channel for Busy/Done
479 
      Tag_Map_Clear             : OUT std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
480 
 
481 
      -- Downstream tRAM port A write request
482 
      tRAM_weB                  : IN  std_logic;
483 
      tRAM_addrB                : IN  std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
484 
      tRAM_dinB                 : IN  std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
485 
 
486 
      -- for descriptor of the upstream DMA
487 
      usDMA_dex_Tag             : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
488 
 
489 
 
490 
      -- Event Buffer write port
491 
      eb_FIFO_we                : OUT std_logic;
492 
      eb_FIFO_wsof              : OUT std_logic;
493 
      eb_FIFO_weof              : OUT std_logic;
494 
      eb_FIFO_din               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
495 
 
496 
      -- Registers Write Port
497 
      Regs_WrEn                 : OUT std_logic;
498 
      Regs_WrMask               : OUT std_logic_vector(2-1 downto 0);
499 
      Regs_WrAddr               : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
500 
      Regs_WrDin                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
501 
 
502 
      -- DDR write port
503 
      DDR_wr_sof                : OUT std_logic;
504 
      DDR_wr_eof                : OUT std_logic;
505 
      DDR_wr_v                  : OUT std_logic;
506 
      DDR_wr_FA                 : OUT std_logic;
507 
      DDR_wr_Shift              : OUT std_logic;
508 
      DDR_wr_Mask               : OUT std_logic_vector(2-1 downto 0);
509 
      DDR_wr_din                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
510 
      DDR_wr_full               : IN  std_logic;
511 
 
512 
      -- Common signals
513 
                trn_clk                   : IN  std_logic;
514 
                trn_reset_n               : IN  std_logic;
515 
                trn_lnk_up_n              : IN  std_logic
516 
                );
517 
        END COMPONENT;
518 
 
519 
   signal  eb_FIFO_we_CplD      : std_logic;
520 
   signal  eb_FIFO_wsof_CplD    : std_logic;
521 
   signal  eb_FIFO_weof_CplD    : std_logic;
522 
   signal  eb_FIFO_din_CplD     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
523 
 
524 
   signal  usDMA_dex_Tag        : std_logic_vector(C_TAG_WIDTH-1 downto 0);
525 
   signal  dsDMA_dex_Tag        : std_logic_vector(C_TAG_WIDTH-1 downto 0);
526 
 
527 
   signal  Tag_Map_Clear        : std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
528 
   signal  FC_pop               : std_logic;
529 
 
530 
 
531 
   ------------------------------------------------------------------
532 
   --  Interrupts generation
533 
   --
534 
   COMPONENT
535 
   Interrupts
536 
   PORT(
537 
      Sys_IRQ                   : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
538 
 
539 
      -- Interrupt generator signals
540 
      IG_Reset                  : IN  std_logic;
541 
      IG_Host_Clear             : IN  std_logic;
542 
      IG_Latency                : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
543 
      IG_Num_Assert             : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
544 
      IG_Num_Deassert           : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
545 
      IG_Asserting              : OUT std_logic;
546 
 
547 
      -- cfg interface
548 
      cfg_interrupt_n           : OUT std_logic;
549 
      cfg_interrupt_rdy_n       : IN  std_logic;
550 
      cfg_interrupt_mmenable    : IN  std_logic_vector(2 downto 0);
551 
      cfg_interrupt_msienable   : IN  std_logic;
552 
      cfg_interrupt_di          : OUT std_logic_vector(7 downto 0);
553 
      cfg_interrupt_do          : IN  std_logic_vector(7 downto 0);
554 
      cfg_interrupt_assert_n    : OUT std_logic;
555 
 
556 
      -- Irpt Channel
557 
      Irpt_Req                  : OUT std_logic;
558 
      Irpt_RE                   : IN  std_logic;
559 
      Irpt_Qout                 : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
560 
 
561 
      trn_clk                   : IN  std_logic;
562 
      trn_reset_n               : IN  std_logic
563 
      );
564 
   END COMPONENT;
565 
 
566 
 
567 
   ------------------------------------------------------------------
568 
   --  Upstream DMA Channel
569 
   --   contains channel buffer for upstream DMA
570 
   --
571 
        COMPONENT
572 
   usDMA_Transact
573 
        PORT(
574 
 
575 
      -- command buffer
576 
      usTlp_Req                 : OUT std_logic;
577 
      usTlp_RE                  : IN  std_logic;
578 
      usTlp_Qout                : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
579 
 
580 
      FIFO_Data_Count           : IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
581 
      FIFO_Reading              : IN  std_logic;
582 
 
583 
      -- Upstream DMA Control Signals from MWr Channel
584 
      usDMA_Start               : IN  std_logic;
585 
      usDMA_Stop                : IN  std_logic;
586 
      usDMA_Channel_Rst         : IN  std_logic;
587 
      us_FC_stop                : IN  std_logic;
588 
      us_Last_sof               : IN  std_logic;
589 
      us_Last_eof               : IN  std_logic;
590 
 
591 
      --- Upstream registers from CplD channel
592 
      DMA_us_PA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
593 
      DMA_us_HA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
594 
      DMA_us_BDA                : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
595 
      DMA_us_Length             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
596 
      DMA_us_Control            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
597 
      usDMA_BDA_eq_Null         : IN  std_logic;
598 
      us_MWr_Param_Vec          : IN  std_logic_vector(6-1   downto 0);
599 
 
600 
      -- Calculation in advance, for better timing
601 
      usHA_is_64b               : IN  std_logic;
602 
      usBDA_is_64b              : IN  std_logic;
603 
 
604 
      -- Calculation in advance, for better timing
605 
      usLeng_Hi19b_True         : IN  std_logic;
606 
      usLeng_Lo7b_True          : IN  std_logic;
607 
 
608 
      --- Upstream commands from CplD channel
609 
      usDMA_Start2              : IN  std_logic;
610 
      usDMA_Stop2               : IN  std_logic;
611 
 
612 
      -- DMA Acknowledge to the start command
613 
      DMA_Cmd_Ack               : OUT std_logic;
614 
 
615 
      --- Tag for descriptor
616 
      usDMA_dex_Tag             : IN  std_logic_vector(C_TAG_WIDTH-1 downto 0);
617 
 
618 
      -- To Interrupt module
619 
      DMA_Done                  : OUT std_logic;
620 
      DMA_TimeOut               : OUT std_logic;
621 
      DMA_Busy                  : OUT std_logic;
622 
 
623 
      -- To Tx channel
624 
      DMA_us_Status             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
625 
 
626 
      -- Additional
627 
      cfg_dcommand              : IN  std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
628 
 
629 
      -- common
630 
                trn_clk                   : IN  std_logic
631 
                );
632 
        END COMPONENT;
633 
 
634 
 
635 
   ------------------------------------------------------------------
636 
   --  Downstream DMA Channel
637 
   --   contains channel buffer for downstream DMA
638 
   --
639 
        COMPONENT
640 
   dsDMA_Transact
641 
        PORT(
642 
      -- command buffer
643 
                MRd_dsp_RE                : IN std_logic;
644 
                MRd_dsp_Req               : OUT std_logic;
645 
                MRd_dsp_Qout              : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
646 
 
647 
      -- Downstream tRAM port A write request, to CplD channel
648 
      tRAM_weB                  : OUT std_logic;
649 
      tRAM_addrB                : OUT std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
650 
      tRAM_dinB                 : OUT std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
651 
 
652 
      -- Downstream Registers from MWr Channel
653 
      DMA_ds_PA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
654 
      DMA_ds_HA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
655 
      DMA_ds_BDA                : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
656 
      DMA_ds_Length             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
657 
      DMA_ds_Control            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
658 
      dsDMA_BDA_eq_Null         : IN  std_logic;
659 
 
660 
      -- Calculation in advance, for better timing
661 
      dsHA_is_64b               : IN  std_logic;
662 
      dsBDA_is_64b              : IN  std_logic;
663 
 
664 
      -- Calculation in advance, for better timing
665 
      dsLeng_Hi19b_True         : IN  std_logic;
666 
      dsLeng_Lo7b_True          : IN  std_logic;
667 
 
668 
      -- Downstream Control Signals from MWr Channel
669 
      dsDMA_Start               : IN  std_logic;
670 
      dsDMA_Stop                : IN  std_logic;
671 
 
672 
      -- DMA Acknowledge to the start command
673 
      DMA_Cmd_Ack               : OUT std_logic;
674 
 
675 
      dsDMA_Channel_Rst         : IN  std_logic;
676 
 
677 
      -- Downstream Control Signals from CplD Channel, out of consecutive dex
678 
      dsDMA_Start2              : IN  std_logic;
679 
      dsDMA_Stop2               : IN  std_logic;
680 
 
681 
      -- Downstream Handshake Signals with CplD Channel for Busy/Done
682 
      Tag_Map_Clear             : IN  std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
683 
      FC_pop                    : IN  std_logic;
684 
 
685 
 
686 
      -- Tag for descriptor
687 
      dsDMA_dex_Tag             : IN  std_logic_vector(C_TAG_WIDTH-1 downto 0);
688 
 
689 
      -- To Interrupt module
690 
      DMA_Done                  : OUT std_logic;
691 
      DMA_TimeOut               : OUT std_logic;
692 
      DMA_Busy                  : OUT std_logic;
693 
 
694 
      -- To Cpl/D channel
695 
      DMA_ds_Status             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
696 
 
697 
      -- Additional
698 
      cfg_dcommand              : IN  std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
699 
 
700 
      -- common
701 
                trn_clk                   : IN  std_logic
702 
                );
703 
        END COMPONENT;
704 
 
705 
   -- tag RAM port A write request
706 
   signal  tRAM_weB             : std_logic;
707 
   signal  tRAM_addrB           : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
708 
   signal  tRAM_dinB            : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
709 
 
710 
 
711 
begin
712 
 
713 
   eb_FIFO_we       <= eb_FIFO_we_i     ;
714 
   eb_FIFO_wsof     <= eb_FIFO_wsof_i   ;
715 
   eb_FIFO_weof     <= eb_FIFO_weof_i   ;
716 
   eb_FIFO_din      <= eb_FIFO_din_i    ;
717 
 
718 
 
719 
   eb_FIFO_we_i     <= eb_FIFO_we_MWr or eb_FIFO_we_CplD;
720 
   eb_FIFO_wsof_i   <= eb_FIFO_wsof_CplD when eb_FIFO_we_CplD='1' else eb_FIFO_wsof_MWr;
721 
   eb_FIFO_weof_i   <= eb_FIFO_weof_CplD when eb_FIFO_we_CplD='1' else eb_FIFO_weof_MWr;
722 
   eb_FIFO_din_i    <= eb_FIFO_din_CplD  when eb_FIFO_we_CplD='1' else eb_FIFO_din_MWr;
723 
 
724 
   -- ------------------------------------------------
725 
   -- Delay of Rx inputs
726 
   -- ------------------------------------------------
727 
    Rx_Input_Delays:
728 
    RxIn_Delay
729 
    PORT MAP(
730 
      -- Common ports
731 
      trn_clk             =>  trn_clk           ,        -- IN  std_logic;
732 
      trn_reset_n         =>  trn_reset_n       ,        -- IN  std_logic;
733 
      trn_lnk_up_n        =>  trn_lnk_up_n      ,        -- IN  std_logic;
734 
 
735 
      -- Transaction receive interface
736 
      trn_rsof_n          =>  trn_rsof_n        ,        -- IN  std_logic;
737 
      trn_reof_n          =>  trn_reof_n        ,        -- IN  std_logic;
738 
      trn_rd              =>  trn_rd            ,        -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
739 
      trn_rrem_n          =>  trn_rrem_n        ,        -- IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
740 
      trn_rerrfwd_n       =>  trn_rerrfwd_n     ,        -- IN  std_logic;
741 
      trn_rsrc_rdy_n      =>  trn_rsrc_rdy_n    ,        -- IN  std_logic;
742 
      trn_rsrc_dsc_n      =>  trn_rsrc_dsc_n    ,        -- IN  std_logic;
743 
      trn_rbar_hit_n      =>  trn_rbar_hit_n    ,        -- IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
744 
      trn_rdst_rdy_n      =>  trn_rdst_rdy_n    ,        -- OUT std_logic;
745 
      Pool_wrBuf_full     =>  DDR_wr_full       ,        -- IN  std_logic;
746 
      Link_Buf_full       =>  Link_Buf_full     ,        -- IN  std_logic;
747 
 
748 
      -- Delayed
749 
      trn_rsof_n_dly      =>  trn_rsof_n_dly    ,        -- OUT std_logic;
750 
      trn_reof_n_dly      =>  trn_reof_n_dly    ,        -- OUT std_logic;
751 
      trn_rd_dly          =>  trn_rd_dly        ,        -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
752 
      trn_rrem_n_dly      =>  trn_rrem_n_dly    ,        -- OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
753 
      trn_rerrfwd_n_dly   =>  trn_rerrfwd_n_dly ,        -- OUT std_logic;
754 
      trn_rsrc_rdy_n_dly  =>  trn_rsrc_rdy_n_dly,        -- OUT std_logic;
755 
      trn_rdst_rdy_n_dly  =>  trn_rdst_rdy_n_dly,        -- OUT std_logic;
756 
      trn_rsrc_dsc_n_dly  =>  trn_rsrc_dsc_n_dly,        -- OUT std_logic;
757 
      trn_rbar_hit_n_dly  =>  trn_rbar_hit_n_dly,        -- OUT std_logic_vector(C_BAR_NUMBER-1 downto 0);
758 
 
759 
      -- TLP resolution
760 
      IORd_Type           =>  IORd_Type         ,        -- OUT std_logic;
761 
      IOWr_Type           =>  IOWr_Type         ,        -- OUT std_logic;
762 
      MRd_Type            =>  MRd_Type          ,        -- OUT std_logic_vector(3 downto 0);
763 
      MWr_Type            =>  MWr_Type          ,        -- OUT std_logic_vector(1 downto 0);
764 
      CplD_Type           =>  CplD_Type         ,        -- OUT std_logic_vector(3 downto 0);
765 
 
766 
      -- From Cpl/D channel
767 
      usDMA_dex_Tag       =>  usDMA_dex_Tag     ,        -- IN  std_logic_vector(7 downto 0);
768 
      dsDMA_dex_Tag       =>  dsDMA_dex_Tag     ,        -- IN  std_logic_vector(7 downto 0);
769 
 
770 
      -- To Memory request process modules
771 
      Tlp_straddles_4KB   =>  Tlp_straddles_4KB ,        -- OUT std_logic;
772 
 
773 
      -- To Cpl/D channel
774 
      Tlp_has_4KB         =>  Tlp_has_4KB       ,        -- OUT std_logic;
775 
      Tlp_has_1DW         =>  Tlp_has_1DW       ,        -- OUT std_logic;
776 
      CplD_is_the_Last    =>  CplD_is_the_Last  ,        -- OUT std_logic;
777 
      CplD_on_Pool        =>  CplD_on_Pool      ,        -- OUT std_logic;
778 
      CplD_on_EB          =>  CplD_on_EB        ,        -- OUT std_logic;
779 
      Req_ID_Match        =>  Req_ID_Match      ,        -- OUT std_logic;
780 
      usDex_Tag_Matched   =>  usDex_Tag_Matched ,        -- OUT std_logic;
781 
      dsDex_Tag_Matched   =>  dsDex_Tag_Matched ,        -- OUT std_logic;
782 
      CplD_Tag            =>  CplD_Tag          ,        -- OUT std_logic_vector(7 downto  0);
783 
 
784 
      -- Additional
785 
      cfg_dcommand        =>  cfg_dcommand      ,        -- IN  std_logic_vector(16-1 downto 0)
786 
      localID             =>  localID                    -- IN  std_logic_vector(15 downto 0)
787 
    );
788 
 
789 
 
790 
  -- ------------------------------------------------
791 
  -- Processing MRd Requests
792 
  -- ------------------------------------------------
793 
   MRd_Channel:
794 
   rx_MRd_Transact
795 
   PORT MAP(
796 
      --
797 
      trn_rsof_n          =>  trn_rsof_n_dly,            -- IN  std_logic;
798 
      trn_reof_n          =>  trn_reof_n_dly,            -- IN  std_logic;
799 
      trn_rd              =>  trn_rd_dly,                -- IN  std_logic_vector(31 downto 0);
800 
      trn_rrem_n          =>  trn_rrem_n_dly,            -- IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
801 
      trn_rerrfwd_n       =>  trn_rerrfwd_n_dly,         -- IN  std_logic;
802 
      trn_rsrc_rdy_n      =>  trn_rsrc_rdy_n_dly,        -- IN  std_logic;
803 
      trn_rsrc_dsc_n      =>  trn_rsrc_dsc_n_dly,        -- IN  std_logic;
804 
      trn_rbar_hit_n      =>  trn_rbar_hit_n_dly,        -- IN  std_logic_vector(6 downto 0);
805 
--      trn_rdst_rdy_n      =>  open,  -- trn_rdst_rdy_n_MRd,            -- OUT std_logic;
806 
                trn_rnp_ok_n        =>  trn_rnp_ok_n,              -- OUT std_logic;
807 
 
808 
      IORd_Type           =>  IORd_Type         ,        -- IN  std_logic;
809 
      MRd_Type            =>  MRd_Type          ,        -- IN  std_logic_vector(3 downto 0);
810 
      Tlp_straddles_4KB   =>  Tlp_straddles_4KB ,        -- IN  std_logic;
811 
 
812 
      pioCplD_RE          =>  pioCplD_RE,                -- IN  std_logic;
813 
      pioCplD_Req         =>  pioCplD_Req,               -- OUT std_logic;
814 
      pioCplD_Qout        =>  pioCplD_Qout,              -- OUT std_logic_vector(127 downto 0);
815 
      pio_FC_stop         =>  pio_FC_stop,               -- IN  std_logic;
816 
 
817 
      FIFO_Empty          =>  eb_FIFO_Empty,                -- IN  std_logic;
818 
      FIFO_Reading        =>  eb_FIFO_Reading,              -- IN  std_logic;
819 
      pio_reading_status  =>  pio_reading_status,           -- OUT std_logic;
820 
 
821 
      Channel_Rst         =>  MRd_Channel_Rst,           -- IN  std_logic;
822 
 
823 
      trn_clk             =>  trn_clk,                   -- IN  std_logic;
824 
      trn_reset_n         =>  trn_reset_n,               -- IN  std_logic;
825 
      trn_lnk_up_n        =>  trn_lnk_up_n               -- IN  std_logic;
826 
        );
827 
 
828 
 
829 
  -- ------------------------------------------------
830 
  -- Processing MWr Requests
831 
  -- ------------------------------------------------
832 
   MWr_Channel:
833 
   rx_MWr_Transact
834 
   PORT MAP(
835 
      --
836 
      trn_rsof_n          =>  trn_rsof_n_dly,            -- IN  std_logic;
837 
      trn_reof_n          =>  trn_reof_n_dly,            -- IN  std_logic;
838 
      trn_rd              =>  trn_rd_dly,                -- IN  std_logic_vector(31 downto 0);
839 
      trn_rrem_n          =>  trn_rrem_n_dly,            -- IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
840 
      trn_rerrfwd_n       =>  trn_rerrfwd_n_dly ,        -- IN  std_logic;
841 
      trn_rsrc_rdy_n      =>  trn_rsrc_rdy_n_dly,        -- IN  std_logic;
842 
      trn_rdst_rdy_n      =>  trn_rdst_rdy_n_dly,        -- IN  std_logic;
843 
      trn_rsrc_dsc_n      =>  trn_rsrc_dsc_n_dly,        -- IN  std_logic;
844 
      trn_rbar_hit_n      =>  trn_rbar_hit_n_dly,        -- IN  std_logic_vector(6 downto 0);
845 
 
846 
      IOWr_Type           =>  IOWr_Type         ,        -- OUT std_logic;
847 
      MWr_Type            =>  MWr_Type          ,        -- IN  std_logic_vector(1 downto 0);
848 
      Tlp_straddles_4KB   =>  Tlp_straddles_4KB ,        -- IN  std_logic;
849 
      Tlp_has_4KB         =>  Tlp_has_4KB       ,        -- IN  std_logic;
850 
 
851 
 
852 
      -- Event Buffer write port
853 
      eb_FIFO_we          =>  eb_FIFO_we_MWr    ,        -- OUT std_logic;
854 
      eb_FIFO_wsof        =>  eb_FIFO_wsof_MWr  ,        -- OUT std_logic;
855 
      eb_FIFO_weof        =>  eb_FIFO_weof_MWr  ,        -- OUT std_logic;
856 
      eb_FIFO_din         =>  eb_FIFO_din_MWr   ,        -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
857 
 
858 
      -- To registers module
859 
      Regs_WrEn           =>  Regs_WrEn0     ,           -- OUT std_logic;
860 
      Regs_WrMask         =>  Regs_WrMask0   ,           -- OUT std_logic_vector(2-1 downto 0);
861 
      Regs_WrAddr         =>  Regs_WrAddr0   ,           -- OUT std_logic_vector(16-1 downto 0);
862 
      Regs_WrDin          =>  Regs_WrDin0    ,           -- OUT std_logic_vector(32-1 downto 0);
863 
 
864 
      -- DDR write port
865 
      DDR_wr_sof          =>  DDR_wr_sof_A   ,  --        OUT   std_logic;
866 
      DDR_wr_eof          =>  DDR_wr_eof_A   ,  --        OUT   std_logic;
867 
      DDR_wr_v            =>  DDR_wr_v_A     ,  --        OUT   std_logic;
868 
      DDR_wr_FA           =>  DDR_wr_FA_A    ,  --        OUT   std_logic;
869 
      DDR_wr_Shift        =>  DDR_wr_Shift_A ,  --        OUT   std_logic;
870 
      DDR_wr_din          =>  DDR_wr_din_A   ,  --        OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
871 
      DDR_wr_Mask         =>  DDR_wr_Mask_A  ,  --        OUT   std_logic_vector(2-1 downto 0);
872 
      DDR_wr_full         =>  DDR_wr_full    ,  --        IN    std_logic;
873 
 
874 
      -- Data generator table write
875 
      tab_we              =>  tab_we ,  -- OUT std_logic_vector(2-1 downto 0);
876 
      tab_wa              =>  tab_wa ,  -- OUT std_logic_vector(12-1 downto 0);
877 
      tab_wd              =>  tab_wd ,  -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
878 
 
879 
      -- Common
880 
      trn_clk             =>  trn_clk        ,  --        IN  std_logic;
881 
      trn_reset_n         =>  trn_reset_n    ,  --        IN  std_logic;
882 
      trn_lnk_up_n        =>  trn_lnk_up_n      --        IN  std_logic;
883 
        );
884 
 
885 
 
886 
  -- ---------------------------------------------------
887 
  -- Processing Completions
888 
  -- ---------------------------------------------------
889 
   CplD_Channel:
890 
   rx_CplD_Transact
891 
   PORT MAP(
892 
      --
893 
      trn_rsof_n          =>  trn_rsof_n_dly,            -- IN  std_logic;
894 
      trn_reof_n          =>  trn_reof_n_dly,            -- IN  std_logic;
895 
      trn_rd              =>  trn_rd_dly,                -- IN  std_logic_vector(31 downto 0);
896 
      trn_rrem_n          =>  trn_rrem_n_dly,            -- IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
897 
      trn_rerrfwd_n       =>  trn_rerrfwd_n_dly,         -- IN  std_logic;
898 
      trn_rsrc_rdy_n      =>  trn_rsrc_rdy_n_dly,        -- IN  std_logic;
899 
      trn_rdst_rdy_n      =>  trn_rdst_rdy_n_dly,        -- IN  std_logic;
900 
      trn_rsrc_dsc_n      =>  trn_rsrc_dsc_n_dly,        -- IN  std_logic;
901 
      trn_rbar_hit_n      =>  trn_rbar_hit_n_dly,        -- IN  std_logic_vector(6 downto 0);
902 
 
903 
      CplD_Type           =>  CplD_Type,                 -- IN  std_logic_vector(3 downto 0);
904 
 
905 
      Req_ID_Match        =>  Req_ID_Match,              -- IN  std_logic;
906 
      usDex_Tag_Matched   =>  usDex_Tag_Matched,         -- IN  std_logic;
907 
      dsDex_Tag_Matched   =>  dsDex_Tag_Matched,         -- IN  std_logic;
908 
 
909 
      Tlp_has_4KB         =>  Tlp_has_4KB     ,          -- IN  std_logic;
910 
      Tlp_has_1DW         =>  Tlp_has_1DW     ,          -- IN  std_logic;
911 
      CplD_is_the_Last    =>  CplD_is_the_Last,          -- IN  std_logic;
912 
      CplD_on_Pool        =>  CplD_on_Pool    ,          -- IN  std_logic;
913 
      CplD_on_EB          =>  CplD_on_EB      ,          -- IN  std_logic;
914 
      CplD_Tag            =>  CplD_Tag,                  -- IN  std_logic_vector( 7 downto  0);
915 
      FC_pop              =>  FC_pop,                    -- OUT std_logic;
916 
 
917 
 
918 
      -- Downstream DMA transferred bytes count up
919 
      ds_DMA_Bytes_Add    =>  ds_DMA_Bytes_Add,          -- OUT std_logic;
920 
      ds_DMA_Bytes        =>  ds_DMA_Bytes    ,          -- OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
921 
 
922 
      -- Downstream tRAM port A write request
923 
      tRAM_weB            =>  tRAM_weB,                  -- IN  std_logic;
924 
      tRAM_addrB          =>  tRAM_addrB,                -- IN  std_logic_vector( 6 downto 0);
925 
      tRAM_dinB           =>  tRAM_dinB,                 -- IN  std_logic_vector(47 downto 0);
926 
 
927 
      -- Downstream channel descriptor tag
928 
      dsDMA_dex_Tag       =>  dsDMA_dex_Tag,             -- OUT std_logic_vector( 7 downto 0);
929 
 
930 
      -- Downstream Tag Map Signal for Busy/Done
931 
      Tag_Map_Clear       =>  Tag_Map_Clear,             -- OUT std_logic_vector(127 downto 0);
932 
 
933 
      -- Upstream channel descriptor tag
934 
      usDMA_dex_Tag       =>  usDMA_dex_Tag,             -- OUT std_logic_vector( 7 downto 0);
935 
 
936 
 
937 
      -- Event Buffer write port
938 
      eb_FIFO_we          =>  eb_FIFO_we_CplD   ,        -- OUT std_logic;
939 
      eb_FIFO_wsof        =>  eb_FIFO_wsof_CplD ,        -- OUT std_logic;
940 
      eb_FIFO_weof        =>  eb_FIFO_weof_CplD ,        -- OUT std_logic;
941 
      eb_FIFO_din         =>  eb_FIFO_din_CplD  ,        -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
942 
 
943 
      -- To registers module
944 
      Regs_WrEn           =>  Regs_WrEn1,                -- OUT std_logic;
945 
      Regs_WrMask         =>  Regs_WrMask1,              -- OUT std_logic_vector(2-1 downto 0);
946 
      Regs_WrAddr         =>  Regs_WrAddr1,              -- OUT std_logic_vector(16-1 downto 0);
947 
      Regs_WrDin          =>  Regs_WrDin1,               -- OUT std_logic_vector(32-1 downto 0);
948 
 
949 
      -- DDR write port
950 
      DDR_wr_sof          =>  DDR_wr_sof_B   ,  --        OUT   std_logic;
951 
      DDR_wr_eof          =>  DDR_wr_eof_B   ,  --        OUT   std_logic;
952 
      DDR_wr_v            =>  DDR_wr_v_B     ,  --        OUT   std_logic;
953 
      DDR_wr_FA           =>  DDR_wr_FA_B    ,  --        OUT   std_logic;
954 
      DDR_wr_Shift        =>  DDR_wr_Shift_B ,  --        OUT   std_logic;
955 
      DDR_wr_Mask         =>  DDR_wr_Mask_B  ,  --        OUT   std_logic_vector(2-1 downto 0);
956 
      DDR_wr_din          =>  DDR_wr_din_B   ,  --        OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
957 
      DDR_wr_full         =>  DDR_wr_full    ,  --        IN    std_logic;
958 
 
959 
 
960 
      -- Common
961 
      trn_clk             =>  trn_clk,                   -- IN std_logic;
962 
      trn_reset_n         =>  trn_reset_n,               -- IN std_logic;
963 
      trn_lnk_up_n        =>  trn_lnk_up_n               -- IN std_logic;
964 
        );
965 
 
966 
 
967 
  -- ------------------------------------------------
968 
  -- Processing upstream DMA Requests
969 
  -- ------------------------------------------------
970 
   Upstream_DMA_Engine:
971 
   usDMA_Transact
972 
   PORT MAP(
973 
      -- TLP buffer
974 
      usTlp_RE            =>  usTlp_RE,                 -- IN std_logic;
975 
      usTlp_Req           =>  usTlp_Req,                -- OUT std_logic;
976 
      usTlp_Qout          =>  usTlp_Qout,               -- OUT std_logic_vector(127 downto 0)
977 
 
978 
      FIFO_Data_Count     =>  eb_FIFO_data_count,          -- IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
979 
      FIFO_Reading        =>  eb_FIFO_Reading,             -- IN  std_logic;
980 
 
981 
      -- upstream Control Signals from MWr Channel
982 
      usDMA_Start         =>  usDMA_Start,              -- IN  std_logic;
983 
      usDMA_Stop          =>  usDMA_Stop,               -- IN  std_logic;
984 
 
985 
      -- Upstream Control Signals from CplD Channel
986 
      usDMA_Start2        =>  usDMA_Start2,             -- IN  std_logic;
987 
      usDMA_Stop2         =>  usDMA_Stop2,              -- IN  std_logic;
988 
 
989 
      DMA_Cmd_Ack         =>  usDMA_Cmd_Ack,            -- OUT std_logic;
990 
      usDMA_Channel_Rst   =>  usDMA_Channel_Rst,        -- IN  std_logic;
991 
      us_FC_stop          =>  us_FC_stop,               -- IN  std_logic;
992 
      us_Last_sof         =>  us_Last_sof,              -- IN  std_logic;
993 
      us_Last_eof         =>  us_Last_eof,              -- IN  std_logic;
994 
 
995 
      -- To Interrupt module
996 
      DMA_Done            =>  DMA_us_Done,              -- OUT std_logic;
997 
      DMA_TimeOut         =>  DMA_us_Tout,              -- OUT std_logic;
998 
      DMA_Busy            =>  DMA_us_Busy,              -- OUT std_logic;
999 
 
1000 
      -- To Tx channel
1001 
      DMA_us_Status       =>  DMA_us_Status,            -- OUT std_logic_vector(31 downto 0);
1002 
 
1003 
      -- upstream Registers
1004 
      DMA_us_PA           =>  DMA_us_PA,                -- IN  std_logic_vector(63 downto 0);
1005 
      DMA_us_HA           =>  DMA_us_HA,                -- IN  std_logic_vector(63 downto 0);
1006 
      DMA_us_BDA          =>  DMA_us_BDA,               -- IN  std_logic_vector(63 downto 0);
1007 
      DMA_us_Length       =>  DMA_us_Length,            -- IN  std_logic_vector(31 downto 0);
1008 
      DMA_us_Control      =>  DMA_us_Control,           -- IN  std_logic_vector(31 downto 0);
1009 
      usDMA_BDA_eq_Null   =>  usDMA_BDA_eq_Null,        -- IN  std_logic;
1010 
      us_MWr_Param_Vec    =>  us_MWr_Param_Vec,         -- IN  std_logic_vector(5 downto 0);
1011 
 
1012 
      -- Calculation in advance, for better timing
1013 
      usHA_is_64b         =>  usHA_is_64b          ,    -- IN  std_logic;
1014 
      usBDA_is_64b        =>  usBDA_is_64b         ,    -- IN  std_logic;
1015 
 
1016 
      usLeng_Hi19b_True   =>  usLeng_Hi19b_True    ,    --  IN  std_logic;
1017 
      usLeng_Lo7b_True    =>  usLeng_Lo7b_True     ,    --  IN  std_logic;
1018 
 
1019 
      usDMA_dex_Tag       =>  usDMA_dex_Tag        ,    -- OUT std_logic_vector( 7 downto 0);
1020 
 
1021 
      cfg_dcommand        =>  cfg_dcommand         ,    -- IN  std_logic_vector(16-1 downto 0)
1022 
 
1023 
      trn_clk             =>  trn_clk                   -- IN std_logic;
1024 
        );
1025 
 
1026 
 
1027 
  -- ------------------------------------------------
1028 
  -- Processing downstream DMA Requests
1029 
  -- ------------------------------------------------
1030 
   Downstream_DMA_Engine:
1031 
   dsDMA_Transact
1032 
   PORT MAP(
1033 
      -- Downstream tRAM port A write request
1034 
      tRAM_weB            =>  tRAM_weB,                 -- OUT std_logic;
1035 
      tRAM_addrB          =>  tRAM_addrB,               -- OUT std_logic_vector( 6 downto 0);
1036 
      tRAM_dinB           =>  tRAM_dinB,                -- OUT std_logic_vector(47 downto 0);
1037 
 
1038 
      -- TLP buffer
1039 
      MRd_dsp_RE          =>  dsMRd_RE,                 -- IN std_logic;
1040 
      MRd_dsp_Req         =>  dsMRd_Req,                -- OUT std_logic;
1041 
      MRd_dsp_Qout        =>  dsMRd_Qout,               -- OUT std_logic_vector(127 downto 0);
1042 
 
1043 
      -- Downstream Registers
1044 
      DMA_ds_PA           =>  DMA_ds_PA,                -- IN  std_logic_vector(63 downto 0);
1045 
      DMA_ds_HA           =>  DMA_ds_HA,                -- IN  std_logic_vector(63 downto 0);
1046 
      DMA_ds_BDA          =>  DMA_ds_BDA,               -- IN  std_logic_vector(63 downto 0);
1047 
      DMA_ds_Length       =>  DMA_ds_Length,            -- IN  std_logic_vector(31 downto 0);
1048 
      DMA_ds_Control      =>  DMA_ds_Control,           -- IN  std_logic_vector(31 downto 0);
1049 
      dsDMA_BDA_eq_Null   =>  dsDMA_BDA_eq_Null,        -- IN  std_logic;
1050 
 
1051 
      -- Calculation in advance, for better timing
1052 
      dsHA_is_64b         =>  dsHA_is_64b          ,    -- IN  std_logic;
1053 
      dsBDA_is_64b        =>  dsBDA_is_64b         ,    -- IN  std_logic;
1054 
 
1055 
      dsLeng_Hi19b_True   =>  dsLeng_Hi19b_True    ,    -- IN  std_logic;
1056 
      dsLeng_Lo7b_True    =>  dsLeng_Lo7b_True     ,    -- IN  std_logic;
1057 
 
1058 
      -- Downstream Control Signals from MWr Channel
1059 
      dsDMA_Start         =>  dsDMA_Start,              -- IN  std_logic;
1060 
      dsDMA_Stop          =>  dsDMA_Stop,               -- IN  std_logic;
1061 
 
1062 
      -- Downstream Control Signals from CplD Channel
1063 
      dsDMA_Start2        =>  dsDMA_Start2,             -- IN  std_logic;
1064 
      dsDMA_Stop2         =>  dsDMA_Stop2,              -- IN  std_logic;
1065 
 
1066 
      DMA_Cmd_Ack         =>  dsDMA_Cmd_Ack,            -- OUT std_logic;
1067 
      dsDMA_Channel_Rst   =>  dsDMA_Channel_Rst,        -- IN  std_logic;
1068 
 
1069 
      -- Downstream Handshake Signals with CplD Channel for Busy/Done
1070 
      Tag_Map_Clear       =>  Tag_Map_Clear,            -- IN  std_logic_vector(127 downto 0);
1071 
 
1072 
      FC_pop              =>  FC_pop,                   -- IN  std_logic;
1073 
 
1074 
      -- To Interrupt module
1075 
      DMA_Done            =>  DMA_ds_Done,              -- OUT std_logic;
1076 
      DMA_TimeOut         =>  DMA_ds_Tout,              -- OUT std_logic;
1077 
      DMA_Busy            =>  DMA_ds_Busy,              -- OUT std_logic;
1078 
 
1079 
      -- To Tx channel
1080 
      DMA_ds_Status       =>  DMA_ds_Status,            -- OUT std_logic_vector(31 downto 0);
1081 
 
1082 
      -- tag for descriptor
1083 
      dsDMA_dex_Tag       =>  dsDMA_dex_Tag,            -- IN  std_logic_vector( 7 downto 0);
1084 
 
1085 
      -- Additional
1086 
      cfg_dcommand        =>  cfg_dcommand ,            -- IN  std_logic_vector(16-1 downto 0)
1087 
 
1088 
      -- common
1089 
      trn_clk             =>  trn_clk                   -- IN std_logic;
1090 
        );
1091 
 
1092 
 
1093 
  -- ------------------------------------------------
1094 
  --   Interrupts generation
1095 
  -- ------------------------------------------------
1096 
   Intrpt_Handle:
1097 
   Interrupts
1098 
   PORT MAP(
1099 
      Sys_IRQ                 => Sys_IRQ                 ,  -- IN  std_logic_vector(31 downto 0);
1100 
 
1101 
      -- Interrupt generator signals
1102 
      IG_Reset                => IG_Reset                ,  -- IN  std_logic;
1103 
      IG_Host_Clear           => IG_Host_Clear           ,  -- IN  std_logic;
1104 
      IG_Latency              => IG_Latency              ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
1105 
      IG_Num_Assert           => IG_Num_Assert           ,  -- OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
1106 
      IG_Num_Deassert         => IG_Num_Deassert         ,  -- OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
1107 
      IG_Asserting            => IG_Asserting            ,  -- OUT std_logic;
1108 
 
1109 
      -- cfg interface
1110 
      cfg_interrupt_n         => cfg_interrupt_n         ,  -- OUT std_logic;
1111 
      cfg_interrupt_rdy_n     => cfg_interrupt_rdy_n     ,  -- IN  std_logic;
1112 
      cfg_interrupt_mmenable  => cfg_interrupt_mmenable  ,  -- IN  std_logic_vector(2 downto 0);
1113 
      cfg_interrupt_msienable => cfg_interrupt_msienable ,  -- IN  std_logic;
1114 
      cfg_interrupt_di        => cfg_interrupt_di        ,  -- OUT std_logic_vector(7 downto 0);
1115 
      cfg_interrupt_do        => cfg_interrupt_do        ,  -- IN  std_logic_vector(7 downto 0);
1116 
      cfg_interrupt_assert_n  => cfg_interrupt_assert_n  ,  -- OUT std_logic;
1117 
 
1118 
      -- Irpt Channel
1119 
      Irpt_Req                => Irpt_Req                ,  -- OUT std_logic;
1120 
      Irpt_RE                 => Irpt_RE                 ,  -- IN  std_logic;
1121 
      Irpt_Qout               => Irpt_Qout               ,  -- OUT std_logic_vector(127 downto 0);
1122 
 
1123 
      trn_clk                 => trn_clk                 ,  -- IN  std_logic;
1124 
      trn_reset_n             => trn_reset_n                -- IN  std_logic
1125 
      );
1126 
 
1127 
 
1128 
end architecture Behavioral;

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