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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MySource/] [v6eb_pcie.vhd] - Blame information for rev 13

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1 13 barabba 
----------------------------------------------------------------------------------
2 
-- Company:
3 
-- Engineer:
4 
--
5 
-- Create Date:    09:12:51 01 Feb 2010
6 
-- Design Name:
7 
-- Module Name:    v6pcieDMA - Behavioral
8 
-- Project Name:
9 
-- Target Devices:
10 
-- Tool versions:
11 
-- Description:
12 
--
13 
-- Dependencies:
14 
--
15 
-- Revision:
16 
--
17 
-- Revision 1.00 - File Released
18 
--
19 
-- Additional Comments:
20 
--
21 
----------------------------------------------------------------------------------
22 
library IEEE;
23 
use IEEE.STD_LOGIC_1164.ALL;
24 
use IEEE.STD_LOGIC_ARITH.ALL;
25 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
26 
 
27 
library work;
28 
use work.abb64Package.all;
29 
 
30 
---- Uncomment the following library declaration if instantiating
31 
---- any Xilinx primitives in this code.
32 
library UNISIM;
33 
use UNISIM.VComponents.all;
34 
 
35 
entity v6pcieDMA is
36 
    generic (
37 
          constant pcieLanes            : integer     := C_NUM_PCIE_LANES
38 
          );
39 
    Port (
40 
 
41 
                         userclk_66MHz                                   : IN std_logic;    --66  MHz USER Socket SingleEnded
42 
                         userclk_200MHz_n              : IN std_logic;    --200 MHz USER Socket LVDS N
43 
                         userclk_200MHz_p              : IN std_logic;    --200 MHz USER Socket LVDS P
44 
 
45 
          -- DPR blinker
46 
          LEDs_IO_pin                   : OUT   std_logic_vector(7 downto 0);
47 
 
48 
 
49 
          -- PCIe transceivers
50 
          pci_exp_rxp                   : IN    std_logic_vector(pcieLanes - 1 downto 0);
51 
          pci_exp_rxn                   : IN    std_logic_vector(pcieLanes - 1 downto 0);
52 
          pci_exp_txp                   : OUT   std_logic_vector(pcieLanes - 1 downto 0);
53 
          pci_exp_txn                   : OUT   std_logic_vector(pcieLanes - 1 downto 0);
54 
 
55 
          -- Necessity signals
56 
          sys_clk_p                     : IN    std_logic; --125 MHz PCIe Clock
57 
          sys_clk_n                     : IN    std_logic; --125 MHz PCIe Clock
58 
          sys_reset_n                   : IN    std_logic  --Reset
59 
          );
60 
 
61 
end entity v6pcieDMA;
62 
 
63 
 
64 
architecture Behavioral of v6pcieDMA is
65 
 
66 
 
67 
 component PCIe_UserLogic_00
68 
  port (
69 
    bram_rd_dout: in std_logic_vector(63 downto 0);
70 
    debug_in_1i: in std_logic_vector(31 downto 0);
71 
    debug_in_2i: in std_logic_vector(31 downto 0);
72 
    debug_in_3i: in std_logic_vector(31 downto 0);
73 
    debug_in_4i: in std_logic_vector(31 downto 0);
74 
    dma_host2board_busy: in std_logic;
75 
    dma_host2board_done: in std_logic;
76 
    fifo_rd_count: in std_logic_vector(14 downto 0);
77 
    fifo_wr_count: in std_logic_vector(14 downto 0);
78 
    fifo_rd_dout: in std_logic_vector(71 downto 0);
79 
    fifo_rd_empty: in std_logic;
80 
    fifo_rd_pempty: in std_logic;
81 
    fifo_wr_full: in std_logic;
82 
    fifo_wr_pfull: in std_logic;
83 
    fifo_rd_valid: in std_logic;
84 
    inout_logic_cw_ce: in std_logic := '1';
85 
    inout_logic_cw_clk: in std_logic;
86 
    reg01_td: in std_logic_vector(31 downto 0);
87 
    reg01_tv: in std_logic;
88 
    reg02_td: in std_logic_vector(31 downto 0);
89 
    reg02_tv: in std_logic;
90 
    reg03_td: in std_logic_vector(31 downto 0);
91 
    reg03_tv: in std_logic;
92 
    reg04_td: in std_logic_vector(31 downto 0);
93 
    reg04_tv: in std_logic;
94 
    reg05_td: in std_logic_vector(31 downto 0);
95 
    reg05_tv: in std_logic;
96 
    reg06_td: in std_logic_vector(31 downto 0);
97 
    reg06_tv: in std_logic;
98 
    reg07_td: in std_logic_vector(31 downto 0);
99 
    reg07_tv: in std_logic;
100 
    reg08_td: in std_logic_vector(31 downto 0);
101 
    reg08_tv: in std_logic;
102 
    reg09_td: in std_logic_vector(31 downto 0);
103 
    reg09_tv: in std_logic;
104 
    reg10_td: in std_logic_vector(31 downto 0);
105 
    reg10_tv: in std_logic;
106 
    reg11_td: in std_logic_vector(31 downto 0);
107 
    reg11_tv: in std_logic;
108 
    reg12_td: in std_logic_vector(31 downto 0);
109 
    reg12_tv: in std_logic;
110 
    reg13_td: in std_logic_vector(31 downto 0);
111 
    reg13_tv: in std_logic;
112 
    reg14_td: in std_logic_vector(31 downto 0);
113 
    reg14_tv: in std_logic;
114 
    rst_i: in std_logic;
115 
    user_logic_cw_ce: in std_logic := '1';
116 
    user_logic_cw_clk: in std_logic;
117 
    bram_rd_addr: out std_logic_vector(11 downto 0);
118 
    bram_wr_addr: out std_logic_vector(11 downto 0);
119 
    bram_wr_din: out std_logic_vector(63 downto 0);
120 
    bram_wr_en: out std_logic_vector(7 downto 0);
121 
    fifo_rd_en: out std_logic;
122 
    fifo_wr_din: out std_logic_vector(71 downto 0);
123 
    fifo_wr_en: out std_logic;
124 
    reg01_rd: out std_logic_vector(31 downto 0);
125 
    reg01_rv: out std_logic;
126 
    reg02_rd: out std_logic_vector(31 downto 0);
127 
    reg02_rv: out std_logic;
128 
    reg03_rd: out std_logic_vector(31 downto 0);
129 
    reg03_rv: out std_logic;
130 
    reg04_rd: out std_logic_vector(31 downto 0);
131 
    reg04_rv: out std_logic;
132 
    reg05_rd: out std_logic_vector(31 downto 0);
133 
    reg05_rv: out std_logic;
134 
    reg06_rd: out std_logic_vector(31 downto 0);
135 
    reg06_rv: out std_logic;
136 
    reg07_rd: out std_logic_vector(31 downto 0);
137 
    reg07_rv: out std_logic;
138 
    reg08_rd: out std_logic_vector(31 downto 0);
139 
    reg08_rv: out std_logic;
140 
    reg09_rd: out std_logic_vector(31 downto 0);
141 
    reg09_rv: out std_logic;
142 
    reg10_rd: out std_logic_vector(31 downto 0);
143 
    reg10_rv: out std_logic;
144 
    reg11_rd: out std_logic_vector(31 downto 0);
145 
    reg11_rv: out std_logic;
146 
    reg12_rd: out std_logic_vector(31 downto 0);
147 
    reg12_rv: out std_logic;
148 
    reg13_rd: out std_logic_vector(31 downto 0);
149 
    reg13_rv: out std_logic;
150 
    reg14_rd: out std_logic_vector(31 downto 0);
151 
    reg14_rv: out std_logic;
152 
    rst_o: out std_logic;
153 
    user_int_1o: out std_logic;
154 
    user_int_2o: out std_logic;
155 
    user_int_3o: out std_logic
156 
  );
157 
end component;
158 
 
159 
 
160 
-- -----------------------------------------------------------------------
161 
--- COMPONENT Declaration: v6_pcie_v1_6 x4                                                                        ---
162 
--- OSS: Ricordarsi di matchare POWER_SAVE - VENDOR_ID e DEVICE_ID     ---
163 
--- OSS: For POWER_SAVE error correct bit[4] and install ISE12 Patch!! ---
164 
-- -----------------------------------------------------------------------
165 
 
166 
--S component v6_pcie_v1_7_x1
167 
   component v6_pcie_v1_7_x4
168 
   generic (
169 
         PL_FAST_TRAIN  : boolean
170 
         );
171 
   port (
172 
    ---------------------------------------------------------
173 
    -- 1. PCI Express (pci_exp) Interface
174 
    ---------------------------------------------------------
175 
 
176 
    -- Tx
177 
    pci_exp_txn                    : out STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
178 
    pci_exp_txp                    : out STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
179 
 
180 
    -- Rx
181 
    pci_exp_rxn                    : in  STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
182 
    pci_exp_rxp                    : in  STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
183 
 
184 
    ---------------------------------------------------------
185 
    -- 2. Transaction (TRN) Interface
186 
    ---------------------------------------------------------
187 
 
188 
    -- Common
189 
    trn_clk                        : out STD_LOGIC;
190 
    trn_reset_n                    : out STD_LOGIC;
191 
    trn_lnk_up_n                   : out STD_LOGIC;
192 
 
193 
    -- Tx
194 
    trn_tsof_n                     : in  STD_LOGIC;
195 
    trn_teof_n                     : in  STD_LOGIC;
196 
    trn_td                         : in  STD_LOGIC_vector (64-1 downto 0);
197 
    trn_trem_n                     : in  STD_LOGIC;
198 
    trn_tsrc_rdy_n                 : in  STD_LOGIC;
199 
    trn_tsrc_dsc_n                 : in  STD_LOGIC;
200 
    trn_tbuf_av                    : out STD_LOGIC_vector (6-1 downto 0);
201 
    trn_terrfwd_n                  : in  STD_LOGIC;
202 
 
203 
    trn_tcfg_req_n                 : out STD_LOGIC;
204 
    trn_terr_drop_n                : out STD_LOGIC;
205 
    trn_tdst_rdy_n                 : out STD_LOGIC;
206 
    trn_tcfg_gnt_n                 : in  STD_LOGIC;
207 
    trn_tstr_n                     : in  STD_LOGIC;
208 
 
209 
    -- Rx
210 
    trn_rd                         : out STD_LOGIC_vector (64-1 downto 0);
211 
    trn_rrem_n                     : out STD_LOGIC;
212 
    trn_rsof_n                     : out STD_LOGIC;
213 
    trn_reof_n                     : out STD_LOGIC;
214 
    trn_rsrc_rdy_n                 : out STD_LOGIC;
215 
    trn_rsrc_dsc_n                 : out STD_LOGIC;
216 
    trn_rerrfwd_n                  : out STD_LOGIC;
217 
    trn_rbar_hit_n                 : out STD_LOGIC_vector (7-1 downto 0);
218 
    trn_rdst_rdy_n                 : in  STD_LOGIC;
219 
    trn_rnp_ok_n                   : in  STD_LOGIC;
220 
 
221 
    -- Flow Control
222 
    trn_fc_cpld                    : out STD_LOGIC_vector (12-1 downto 0);
223 
    trn_fc_cplh                    : out STD_LOGIC_vector (8-1 downto 0);
224 
    trn_fc_npd                     : out STD_LOGIC_vector (12-1 downto 0);
225 
    trn_fc_nph                     : out STD_LOGIC_vector (8-1 downto 0);
226 
    trn_fc_pd                      : out STD_LOGIC_vector (12-1 downto 0);
227 
    trn_fc_ph                      : out STD_LOGIC_vector (8-1 downto 0);
228 
    trn_fc_sel                     : in  STD_LOGIC_vector (3-1 downto 0);
229 
 
230 
 
231 
    ---------------------------------------------------------
232 
    -- 3. Configuration (CFG) Interface
233 
    ---------------------------------------------------------
234 
 
235 
    cfg_do                         : out STD_LOGIC_vector (32-1 downto 0);
236 
    cfg_rd_wr_done_n               : out STD_LOGIC;
237 
    cfg_di                         : in  STD_LOGIC_vector (32-1 downto 0);
238 
    cfg_byte_en_n                  : in  STD_LOGIC_vector (4-1 downto 0);
239 
    cfg_dwaddr                     : in  STD_LOGIC_vector (10-1 downto 0);
240 
    cfg_wr_en_n                    : in  STD_LOGIC;
241 
    cfg_rd_en_n                    : in  STD_LOGIC;
242 
 
243 
    cfg_err_cor_n                  : in  STD_LOGIC;
244 
    cfg_err_ur_n                   : in  STD_LOGIC;
245 
    cfg_err_ecrc_n                 : in  STD_LOGIC;
246 
    cfg_err_cpl_timeout_n          : in  STD_LOGIC;
247 
    cfg_err_cpl_abort_n            : in  STD_LOGIC;
248 
    cfg_err_cpl_unexpect_n         : in  STD_LOGIC;
249 
    cfg_err_posted_n               : in  STD_LOGIC;
250 
    cfg_err_locked_n               : in  STD_LOGIC;
251 
    cfg_err_tlp_cpl_header         : in  STD_LOGIC_vector (48-1 downto 0);
252 
    cfg_err_cpl_rdy_n              : out STD_LOGIC;
253 
    cfg_interrupt_n                : in  STD_LOGIC;
254 
    cfg_interrupt_rdy_n            : out STD_LOGIC;
255 
    cfg_interrupt_assert_n         : in  STD_LOGIC;
256 
    cfg_interrupt_di               : in  STD_LOGIC_vector (8-1 downto 0);
257 
    cfg_interrupt_do               : out STD_LOGIC_vector (8-1 downto 0);
258 
    cfg_interrupt_mmenable         : out STD_LOGIC_vector (3-1 downto 0);
259 
    cfg_interrupt_msienable        : out STD_LOGIC;
260 
    cfg_interrupt_msixenable       : out STD_LOGIC;
261 
    cfg_interrupt_msixfm           : out STD_LOGIC;
262 
    cfg_turnoff_ok_n               : in  STD_LOGIC;
263 
    cfg_to_turnoff_n               : out STD_LOGIC;
264 
    cfg_trn_pending_n              : in  STD_LOGIC;
265 
    cfg_pm_wake_n                  : in  STD_LOGIC;
266 
    cfg_bus_number                 : out STD_LOGIC_vector (8-1 downto 0);
267 
    cfg_device_number              : out STD_LOGIC_vector (5-1 downto 0);
268 
    cfg_function_number            : out STD_LOGIC_vector (3-1 downto 0);
269 
    cfg_status                     : out STD_LOGIC_vector (16-1 downto 0);
270 
    cfg_command                    : out STD_LOGIC_vector (16-1 downto 0);
271 
    cfg_dstatus                    : out STD_LOGIC_vector (16-1 downto 0);
272 
    cfg_dcommand                   : out STD_LOGIC_vector (16-1 downto 0);
273 
    cfg_lstatus                    : out STD_LOGIC_vector (16-1 downto 0);
274 
    cfg_lcommand                   : out STD_LOGIC_vector (16-1 downto 0);
275 
    cfg_dcommand2                  : out STD_LOGIC_vector (16-1 downto 0);
276 
    cfg_pcie_link_state_n          : out STD_LOGIC_vector (3-1 downto 0);
277 
    cfg_dsn                        : in  STD_LOGIC_vector (64-1 downto 0);
278 
    cfg_pmcsr_pme_en               : out STD_LOGIC;
279 
    cfg_pmcsr_pme_status           : out STD_LOGIC;
280 
    cfg_pmcsr_powerstate           : out STD_LOGIC_vector (2-1 downto 0);
281 
--S v1.3 --> 1.6    lnk_clk_en     : out STD_LOGIC;
282 
--       lnk_clk_en                                               : out STD_LOGIC;
283 
 
284 
    ---------------------------------------------------------
285 
    -- 4. Physical Layer Control and Status (PL) Interface
286 
    ---------------------------------------------------------
287 
 
288 
    pl_initial_link_width          : out STD_LOGIC_vector (3-1 downto 0);
289 
    pl_lane_reversal_mode          : out STD_LOGIC_vector (2-1 downto 0);
290 
    pl_link_gen2_capable           : out STD_LOGIC;
291 
    pl_link_partner_gen2_supported : out STD_LOGIC;
292 
    pl_link_upcfg_capable          : out STD_LOGIC;
293 
    pl_ltssm_state                 : out STD_LOGIC_vector (6-1 downto 0);
294 
    pl_received_hot_rst            : out STD_LOGIC;
295 
    pl_sel_link_rate               : out STD_LOGIC;
296 
    pl_sel_link_width              : out STD_LOGIC_vector (2-1 downto 0);
297 
    pl_directed_link_auton         : in  STD_LOGIC;
298 
    pl_directed_link_change        : in  STD_LOGIC_vector (2-1 downto 0);
299 
    pl_directed_link_speed         : in  STD_LOGIC;
300 
    pl_directed_link_width         : in  STD_LOGIC_vector (2-1 downto 0);
301 
    pl_upstream_prefer_deemph      : in  STD_LOGIC;
302 
 
303 
 
304 
    ---------------------------------------------------------
305 
    -- 5. System  (SYS) Interface
306 
    ---------------------------------------------------------
307 
 
308 
    sys_clk                        : in  STD_LOGIC;
309 
    sys_reset_n                    : in  STD_LOGIC
310 
  );
311 
 end component;
312 
 
313 
 
314 
 
315 
 
316 
 
317 
     signal fifo_reset_done              : std_logic;
318 
     signal pio_reading_status           : std_logic;
319 
 
320 
 
321 
-- -----------------------------------------------------------------------
322 
--  DDR SDRAM control module
323 
-- -----------------------------------------------------------------------
324 
 
325 
   COMPONENT bram_DDRs_Control_loopback
326 
   GENERIC (
327 
             C_ASYNFIFO_WIDTH  :  integer ;
328 
             P_SIMULATION      :  boolean
329 
            );
330 
   PORT (
331 
 
332 
      DDR_wr_sof               : IN    std_logic;
333 
      DDR_wr_eof               : IN    std_logic;
334 
      DDR_wr_v                 : IN    std_logic;
335 
      DDR_wr_FA                : IN    std_logic;
336 
      DDR_wr_Shift             : IN    std_logic;
337 
      DDR_wr_Mask              : IN    std_logic_vector(2-1 downto 0);
338 
      DDR_wr_din               : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
339 
      DDR_wr_full              : OUT   std_logic;
340 
 
341 
      DDR_rdc_sof              : IN    std_logic;
342 
      DDR_rdc_eof              : IN    std_logic;
343 
      DDR_rdc_v                : IN    std_logic;
344 
      DDR_rdc_FA               : IN    std_logic;
345 
      DDR_rdc_Shift            : IN    std_logic;
346 
      DDR_rdc_din              : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
347 
      DDR_rdc_full             : OUT   std_logic;
348 
 
349 
      -- DDR payload FIFO Read Port
350 
      DDR_FIFO_RdEn            : IN    std_logic;
351 
      DDR_FIFO_Empty           : OUT   std_logic;
352 
      DDR_FIFO_RdQout          : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
353 
 
354 
      -- Common interface
355 
      DDR_Ready                : OUT   std_logic;
356 
      DDR_Blinker              : OUT   std_logic;
357 
      mem_clk                  : IN    std_logic;
358 
      trn_clk                  : IN    std_logic;
359 
                Sim_Zeichen              : OUT   std_logic;
360 
      trn_reset_n              : IN    std_logic
361 
    );
362 
   END COMPONENT;
363 
 
364 
 
365 
   COMPONENT bram_DDRs_Control
366 
   GENERIC (
367 
             C_ASYNFIFO_WIDTH  :  integer ;
368 
             P_SIMULATION      :  boolean
369 
            );
370 
   PORT (
371 
 
372 
                --USER Logic Interface
373 
                user_wr_weA              : IN    std_logic_vector(7 downto 0);
374 
                user_wr_addrA            : IN    std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
375 
                user_wr_dinA             : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
376 
                user_rd_addrB            : IN    std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
377 
                user_rd_doutB            : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
378 
                user_rd_clk              : IN    std_logic;
379 
                user_wr_clk              : IN    std_logic;
380 
 
381 
      -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
382 
      DDR_wr_sof               : IN    std_logic;
383 
      DDR_wr_eof               : IN    std_logic;
384 
      DDR_wr_v                 : IN    std_logic;
385 
      DDR_wr_FA                : IN    std_logic;
386 
      DDR_wr_Shift             : IN    std_logic;
387 
      DDR_wr_Mask              : IN    std_logic_vector(2-1 downto 0);
388 
      DDR_wr_din               : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
389 
      DDR_wr_full              : OUT   std_logic;
390 
 
391 
      DDR_rdc_sof              : IN    std_logic;
392 
      DDR_rdc_eof              : IN    std_logic;
393 
      DDR_rdc_v                : IN    std_logic;
394 
      DDR_rdc_FA               : IN    std_logic;
395 
      DDR_rdc_Shift            : IN    std_logic;
396 
      DDR_rdc_din              : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
397 
      DDR_rdc_full             : OUT   std_logic;
398 
 
399 
      -- DDR payload FIFO Read Port
400 
      DDR_FIFO_RdEn            : IN    std_logic;
401 
      DDR_FIFO_Empty           : OUT   std_logic;
402 
      DDR_FIFO_RdQout          : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
403 
 
404 
      -- Common interface
405 
      DDR_Ready                : OUT   std_logic;
406 
      DDR_Blinker              : OUT   std_logic;
407 
      mem_clk                  : IN    std_logic;
408 
      trn_clk                  : IN    std_logic;
409 
                Sim_Zeichen              : OUT   std_logic;
410 
      trn_reset_n              : IN    std_logic
411 
    );
412 
   END COMPONENT;
413 
 
414 
 
415 
   signal    DDR_wr_sof               :  std_logic;
416 
   signal    DDR_wr_eof               :  std_logic;
417 
   signal    DDR_wr_v                 :  std_logic;
418 
   signal    DDR_wr_FA                :  std_logic;
419 
   signal    DDR_wr_Shift             :  std_logic;
420 
   signal    DDR_wr_Mask              :  std_logic_vector(2-1 downto 0);
421 
   signal    DDR_wr_din               :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
422 
   signal    DDR_wr_full              :  std_logic;
423 
 
424 
   signal    DDR_rdc_sof              :  std_logic;
425 
   signal    DDR_rdc_eof              :  std_logic;
426 
   signal    DDR_rdc_v                :  std_logic;
427 
   signal    DDR_rdc_FA               :  std_logic;
428 
   signal    DDR_rdc_Shift            :  std_logic;
429 
   signal    DDR_rdc_din              :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
430 
   signal    DDR_rdc_full             :  std_logic;
431 
 
432 
   signal    DDR_FIFO_RdEn            :  std_logic;
433 
   signal    DDR_FIFO_Empty           :  std_logic;
434 
   signal    DDR_FIFO_RdQout          :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
435 
 
436 
   signal    DDR_Ready                :  std_logic;
437 
   signal    DDR_Blinker              :  std_logic;
438 
 
439 
        signal  user_wr_weA              : std_logic_vector(7 downto 0) := (Others =>'0');
440 
        signal  user_wr_addrA            : std_logic_vector(C_PRAM_AWIDTH-1 downto 0) := (Others =>'0');
441 
        signal  user_wr_dinA             : std_logic_vector(C_DBUS_WIDTH-1 downto 0)  := (Others =>'0');
442 
        signal  user_rd_addrB            : std_logic_vector(C_PRAM_AWIDTH-1 downto 0) := (Others =>'0');
443 
        signal  user_rd_doutB            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
444 
 
445 
 
446 
   -- -----------------------------------------------------------------------
447 
   -- FIFO module
448 
   -- -----------------------------------------------------------------------
449 
 
450 
 
451 
   component eb_wrapper_loopback
452 
     port (
453 
           wr_clk      : IN  std_logic;
454 
           wr_en       : IN  std_logic;
455 
           din         : IN  std_logic_VECTOR(72-1 downto 0);
456 
           pfull       : OUT std_logic;
457 
           full        : OUT std_logic;
458 
 
459 
           rd_clk      : IN  std_logic;
460 
           rd_en       : IN  std_logic;
461 
           dout        : OUT std_logic_VECTOR(72-1 downto 0);
462 
           pempty      : OUT std_logic;
463 
           empty       : OUT std_logic;
464 
 
465 
           data_count  : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
466 
           rst         : IN  std_logic
467 
           );
468 
   end component;
469 
 
470 
 
471 
   component eb_wrapper
472 
     port (
473 
                         --FIFO PCIe-->USER
474 
                         H2B_wr_clk        : IN  std_logic;
475 
          H2B_wr_en         : IN  std_logic;
476 
          H2B_wr_din        : IN  std_logic_VECTOR(72-1 downto 0);
477 
          H2B_wr_pfull      : OUT std_logic;
478 
          H2B_wr_full       : OUT std_logic;
479 
          H2B_wr_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
480 
          H2B_rd_clk        : IN  std_logic;
481 
          H2B_rd_en         : IN  std_logic;
482 
          H2B_rd_dout       : OUT std_logic_VECTOR(72-1 downto 0);
483 
          H2B_rd_pempty     : OUT std_logic;
484 
          H2B_rd_empty      : OUT std_logic;
485 
          H2B_rd_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
486 
                         H2B_rd_valid      : OUT std_logic;
487 
                         --FIFO USER-->PCIe
488 
          B2H_wr_clk        : IN  std_logic;
489 
          B2H_wr_en         : IN  std_logic;
490 
          B2H_wr_din        : IN  std_logic_VECTOR(72-1 downto 0);
491 
          B2H_wr_pfull      : OUT std_logic;
492 
          B2H_wr_full       : OUT std_logic;
493 
          B2H_wr_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
494 
          B2H_rd_clk        : IN  std_logic;
495 
          B2H_rd_en         : IN  std_logic;
496 
          B2H_rd_dout       : OUT std_logic_VECTOR(72-1 downto 0);
497 
          B2H_rd_pempty     : OUT std_logic;
498 
          B2H_rd_empty      : OUT std_logic;
499 
          B2H_rd_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
500 
                         B2H_rd_valid            : OUT std_logic;
501 
          --RESET from PCIe
502 
                         rst               : IN  std_logic
503 
          );
504 
   end component;
505 
 
506 
 
507 
   signal  eb_wclk            :  std_logic;
508 
   signal  eb_we              :  std_logic;
509 
   signal  eb_wsof            :  std_logic;
510 
   signal  eb_weof            :  std_logic;
511 
   signal  eb_din             :  std_logic_VECTOR(72-1 downto 0);
512 
   signal  eb_pfull           :  std_logic;
513 
   signal  eb_full            :  std_logic;
514 
   signal  eb_rclk            :  std_logic;
515 
   signal  eb_re              :  std_logic;
516 
   signal  eb_dout            :  std_logic_VECTOR(72-1 downto 0);
517 
   signal  eb_pempty          :  std_logic;
518 
   signal  eb_empty           :  std_logic;
519 
   signal  eb_valid           :  std_logic;
520 
   signal  eb_rst             :  std_logic;
521 
 
522 
   signal  eb_data_count      :  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
523 
   signal  H2B_wr_data_count  :  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
524 
   signal  B2H_rd_data_count  :  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
525 
 
526 
 
527 
   signal  pio_read_status    :  std_logic;
528 
   signal  eb_FIFO_ow         :  std_logic;
529 
 
530 
   signal  eb_FIFO_Status     :  std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
531 
   signal  H2B_FIFO_Status    :  std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
532 
   signal  B2H_FIFO_Status    :  std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
533 
 
534 
   signal  eb_we_up           :  std_logic;
535 
   signal  eb_din_up          :  std_logic_VECTOR(72-1 downto 0);
536 
 
537 
   signal  tab_sel            : STD_LOGIC;
538 
 
539 
        signal   user_rd_en         : std_logic := '0';
540 
        signal   user_rd_dout       : std_logic_VECTOR(72-1 downto 0);
541 
        signal   user_rd_pempty     : std_logic;
542 
        signal   user_rd_empty      : std_logic;
543 
        signal   user_rd_data_count : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
544 
        signal   user_wr_data_count : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
545 
        signal   user_wr_en         : std_logic := '0';
546 
        signal   user_wr_din        : std_logic_VECTOR(72-1 downto 0) := (Others =>'0');
547 
        signal   user_wr_pfull      : std_logic;
548 
        signal   user_wr_full       : std_logic;
549 
        signal   user_rd_valid      : std_logic;
550 
 
551 
 
552 
 
553 
------------- COMPONENT Declaration: tlpControl   ------
554 
--
555 
 component tlpControl
556 
   port (
557 
        --  Test pin, emulating DDR data flow discontinuity
558 
        mbuf_UserFull                : IN  std_logic;
559 
        trn_Blinker                  : OUT std_logic;
560 
 
561 
 
562 
 
563 
--S     SIMONE: Wanxau UserLogic Signals, not Used
564 
        -- DCB protocol interface
565 
        protocol_link_act            : IN  std_logic_vector(2-1 downto 0);
566 
        protocol_rst                 : OUT std_logic;
567 
        -- Fabric side: CTL Rx
568 
        ctl_rv                       : OUT std_logic;
569 
        ctl_rd                       : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
570 
        -- Fabric side: CTL Tx
571 
        ctl_ttake                    : OUT std_logic;
572 
        ctl_tv                       : IN  std_logic;
573 
        ctl_td                       : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
574 
        ctl_tstop                    : OUT std_logic;
575 
        ctl_reset                    : OUT std_logic;
576 
        ctl_status                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
577 
        -- Fabric side: DLM Rx
578 
        dlm_rv                       : OUT std_logic;
579 
        dlm_rd                       : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
580 
        -- Fabric side: DLM Tx
581 
        dlm_tv                       : IN  std_logic;
582 
        dlm_td                       : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
583 
        Link_Buf_full                : IN  std_logic;
584 
        -- Data generator table write
585 
        tab_we                       : OUT std_logic_vector(2-1 downto 0);
586 
        tab_wa                       : OUT std_logic_vector(12-1 downto 0);
587 
        tab_wd                       : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
588 
        -- Data generator control
589 
        DG_is_Running                : IN  std_logic;
590 
        DG_Reset                     : OUT std_logic;
591 
        DG_Mask                      : OUT std_logic;
592 
--S     SIMONE: Wanxau UserLogic Signals, not Used
593 
 
594 
 
595 
        -- Interrupter triggers
596 
        DAQ_irq                      : IN  std_logic;
597 
        CTL_irq                      : IN  std_logic;
598 
        DLM_irq                      : IN  std_logic;
599 
 
600 
 
601 
        -- SIMONE Register: PC-->FPGA
602 
        reg01_tv                   : OUT std_logic;
603 
        reg01_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
604 
        reg02_tv                   : OUT std_logic;
605 
        reg02_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
606 
        reg03_tv                   : OUT std_logic;
607 
        reg03_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
608 
        reg04_tv                   : OUT std_logic;
609 
        reg04_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
610 
        reg05_tv                   : OUT std_logic;
611 
        reg05_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
612 
        reg06_tv                   : OUT std_logic;
613 
        reg06_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
614 
        reg07_tv                   : OUT std_logic;
615 
        reg07_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
616 
        reg08_tv                   : OUT std_logic;
617 
        reg08_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
618 
        reg09_tv                   : OUT std_logic;
619 
        reg09_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
620 
        reg10_tv                   : OUT std_logic;
621 
        reg10_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
622 
        reg11_tv                   : OUT std_logic;
623 
        reg11_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
624 
        reg12_tv                   : OUT std_logic;
625 
        reg12_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
626 
        reg13_tv                   : OUT std_logic;
627 
        reg13_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
628 
        reg14_tv                   : OUT std_logic;
629 
        reg14_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
630 
 
631 
        -- SIMONE Register: FPGA-->PC
632 
        reg01_rv                   : IN  std_logic;
633 
        reg01_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
634 
        reg02_rv                   : IN  std_logic;
635 
        reg02_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
636 
        reg03_rv                   : IN  std_logic;
637 
        reg03_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
638 
        reg04_rv                   : IN  std_logic;
639 
        reg04_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
640 
        reg05_rv                   : IN  std_logic;
641 
        reg05_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
642 
        reg06_rv                   : IN  std_logic;
643 
        reg06_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
644 
        reg07_rv                   : IN  std_logic;
645 
        reg07_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
646 
        reg08_rv                   : IN  std_logic;
647 
        reg08_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
648 
        reg09_rv                   : IN  std_logic;
649 
        reg09_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
650 
        reg10_rv                   : IN  std_logic;
651 
        reg10_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
652 
        reg11_rv                   : IN  std_logic;
653 
        reg11_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
654 
        reg12_rv                   : IN  std_logic;
655 
        reg12_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
656 
        reg13_rv                   : IN  std_logic;
657 
        reg13_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
658 
        reg14_rv                   : IN  std_logic;
659 
        reg14_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
660 
 
661 
                  --SIMONE debug signals
662 
                 debug_in_1i                                      : OUT std_logic_vector(31 downto 0);
663 
                 debug_in_2i                                      : OUT std_logic_vector(31 downto 0);
664 
                 debug_in_3i                                      : OUT std_logic_vector(31 downto 0);
665 
                 debug_in_4i                                      : OUT std_logic_vector(31 downto 0);
666 
 
667 
 
668 
        -- Event Buffer FIFO interface
669 
        eb_FIFO_we                   : OUT std_logic;
670 
        eb_FIFO_wsof                 : OUT std_logic;
671 
        eb_FIFO_weof                 : OUT std_logic;
672 
        eb_FIFO_din                  : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
673 
 
674 
        eb_FIFO_re                   : OUT std_logic;
675 
        eb_FIFO_empty                : IN  std_logic;
676 
        eb_FIFO_qout                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
677 
        eb_FIFO_data_count           : IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
678 
 
679 
        eb_FIFO_ow                   : IN  std_logic;
680 
 
681 
        pio_reading_status           : OUT std_logic;
682 
        eb_FIFO_Status               : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
683 
        eb_FIFO_Rst                  : OUT std_logic;
684 
 
685 
                  H2B_FIFO_Status                        : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
686 
                  B2H_FIFO_Status                        : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
687 
 
688 
        -- Debugging signals
689 
        DMA_us_Done                  : OUT std_logic;
690 
        DMA_us_Busy                  : OUT std_logic;
691 
        DMA_us_Busy_LED              : OUT std_logic;
692 
        DMA_ds_Done                  : OUT std_logic;
693 
        DMA_ds_Busy                  : OUT std_logic;
694 
        DMA_ds_Busy_LED              : OUT std_logic;
695 
 
696 
        -- DDR control interface
697 
        DDR_Ready                    : IN    std_logic;
698 
 
699 
        DDR_wr_sof                   : OUT   std_logic;
700 
        DDR_wr_eof                   : OUT   std_logic;
701 
        DDR_wr_v                     : OUT   std_logic;
702 
        DDR_wr_FA                    : OUT   std_logic;
703 
        DDR_wr_Shift                 : OUT   std_logic;
704 
        DDR_wr_Mask                  : OUT   std_logic_vector(2-1 downto 0);
705 
        DDR_wr_din                   : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
706 
        DDR_wr_full                  : IN    std_logic;
707 
 
708 
        DDR_rdc_sof                  : OUT   std_logic;
709 
        DDR_rdc_eof                  : OUT   std_logic;
710 
        DDR_rdc_v                    : OUT   std_logic;
711 
        DDR_rdc_FA                   : OUT   std_logic;
712 
        DDR_rdc_Shift                : OUT   std_logic;
713 
        DDR_rdc_din                  : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
714 
        DDR_rdc_full                 : IN    std_logic;
715 
 
716 
        -- DDR payload FIFO Read Port
717 
        DDR_FIFO_RdEn                : OUT std_logic;
718 
        DDR_FIFO_Empty               : IN  std_logic;
719 
        DDR_FIFO_RdQout              : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
720 
 
721 
        -- Transaction layer interface
722 
        trn_lnk_up_n                 : IN  std_logic;
723 
        trn_rsrc_dsc_n               : IN  std_logic;
724 
        trn_rnp_ok_n                 : OUT std_logic;
725 
        trn_tsrc_dsc_n               : OUT std_logic;
726 
        trn_tdst_dsc_n               : IN  std_logic;
727 
        trn_tbuf_av                  : IN  std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
728 
        trn_terrfwd_n                : OUT std_logic;
729 
 
730 
        trn_clk                      : IN  std_logic;
731 
        trn_reset_n                  : IN  std_logic;
732 
        trn_rsrc_rdy_n               : IN  std_logic;
733 
        trn_tdst_rdy_n               : IN  std_logic;
734 
        trn_rsof_n                   : IN  std_logic;
735 
        trn_reof_n                   : IN  std_logic;
736 
        trn_rerrfwd_n                : IN  std_logic;
737 
        trn_rrem_n                   : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
738 
        trn_rd                       : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
739 
 
740 
        cfg_dcommand                 : IN  std_logic_vector(15 downto 0);
741 
        pcie_link_width              : IN  std_logic_vector( 5 downto 0);
742 
        localId                      : IN  std_logic_vector(15 downto 0);
743 
 
744 
        cfg_interrupt_n              : OUT std_logic;
745 
        cfg_interrupt_rdy_n          : IN  std_logic;
746 
        cfg_interrupt_mmenable       : IN  std_logic_vector(2 downto 0);
747 
        cfg_interrupt_msienable      : IN  std_logic;
748 
        cfg_interrupt_di             : OUT std_logic_vector(7 downto 0);
749 
        cfg_interrupt_do             : IN  std_logic_vector(7 downto 0);
750 
        cfg_interrupt_assert_n       : OUT std_logic;
751 
 
752 
        Format_Shower                : OUT   std_logic;
753 
 
754 
        trn_rbar_hit_n               : IN  std_logic_vector(6 downto 0);
755 
        trn_tsrc_rdy_n               : OUT std_logic;
756 
        trn_rdst_rdy_n               : OUT std_logic;
757 
        trn_tsof_n                   : OUT std_logic;
758 
        trn_teof_n                   : OUT std_logic;
759 
        trn_trem_n                   : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
760 
        trn_td                       : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
761 
        );
762 
 end component;
763 
 
764 
 signal   Format_Shower              : std_logic;
765 
 
766 
 
767 
 
768 
 
769 
  -- TRN Layer signals
770 
 
771 
  signal trn_terr_drop_n                 : std_logic;
772 
  signal trn_tcfg_gnt_n                  : std_logic;
773 
  signal trn_tstr_n                      : std_logic;
774 
  signal trn_fc_cpld                     : STD_LOGIC_vector (12-1 downto 0);
775 
  signal trn_fc_cplh                     : STD_LOGIC_vector (8-1 downto 0);
776 
  signal trn_fc_npd                      : STD_LOGIC_vector (12-1 downto 0);
777 
  signal trn_fc_nph                      : STD_LOGIC_vector (8-1 downto 0);
778 
  signal trn_fc_pd                       : STD_LOGIC_vector (12-1 downto 0);
779 
  signal trn_fc_ph                       : STD_LOGIC_vector (8-1 downto 0);
780 
  signal trn_fc_sel                      : STD_LOGIC_vector (3-1 downto 0);
781 
 
782 
  signal cfg_interrupt_msixenable        : std_logic;
783 
  signal cfg_interrupt_msixfm            : std_logic;
784 
  signal cfg_dcommand2                   : std_logic_vector (16-1 downto 0);
785 
  signal trn_tcfg_req_n                  : std_logic;
786 
 
787 
  signal  pl_initial_link_width          : STD_LOGIC_vector (3-1 downto 0);
788 
  signal  pl_lane_reversal_mode          : STD_LOGIC_vector (2-1 downto 0);
789 
  signal  pl_link_gen2_capable           : STD_LOGIC;
790 
  signal  pl_link_partner_gen2_supported : STD_LOGIC;
791 
  signal  pl_link_upcfg_capable          : STD_LOGIC;
792 
  signal  pl_ltssm_state                 : STD_LOGIC_vector (6-1 downto 0);
793 
  signal  pl_received_hot_rst            : STD_LOGIC;
794 
  signal  pl_sel_link_rate               : STD_LOGIC;
795 
  signal  pl_sel_link_width              : STD_LOGIC_vector (2-1 downto 0);
796 
  signal  pl_directed_link_auton         : STD_LOGIC;
797 
  signal  pl_directed_link_change        : STD_LOGIC_vector (2-1 downto 0);
798 
  signal  pl_directed_link_speed         : STD_LOGIC;
799 
  signal  pl_directed_link_width         : STD_LOGIC_vector (2-1 downto 0);
800 
  signal  pl_upstream_prefer_deemph      : STD_LOGIC;
801 
 
802 
  signal  trn_reset_n_int1       : STD_LOGIC;
803 
  signal  trn_lnk_up_n_int1      : STD_LOGIC;
804 
 
805 
  signal trn_clk                     : std_logic;
806 
  signal trn_reset_n                 : std_logic;
807 
  signal trn_lnk_up_n                : std_logic;
808 
  signal trn_td                      : std_logic_vector(63 downto 0);
809 
  signal trn_trem_n                  : std_logic_vector(7 downto 0);
810 
  signal trn_tsof_n                  : std_logic;
811 
  signal trn_teof_n                  : std_logic;
812 
  signal trn_tsrc_rdy_n              : std_logic;
813 
  signal trn_tdst_rdy_n              : std_logic;
814 
  signal trn_tdst_dsc_n              : std_logic;
815 
  signal trn_tsrc_dsc_n              : std_logic;
816 
  signal trn_terrfwd_n               : std_logic;
817 
  signal trn_tbuf_av                 : std_logic_vector(5 downto 0);
818 
  signal trn_rd                      : std_logic_vector(63 downto 0);
819 
  signal trn_rrem_n                  : std_logic_vector(7 downto 0);
820 
  signal trn_rsof_n                  : std_logic;
821 
  signal trn_reof_n                  : std_logic;
822 
  signal trn_rsrc_rdy_n              : std_logic;
823 
  signal trn_rsrc_dsc_n              : std_logic;
824 
  signal trn_rdst_rdy_n              : std_logic;
825 
  signal trn_rerrfwd_n               : std_logic;
826 
  signal trn_rnp_ok_n                : std_logic;
827 
  signal trn_rbar_hit_n              : std_logic_vector(6 downto 0);
828 
  signal trn_rfc_nph_av              : std_logic_vector(7 downto 0);
829 
  signal trn_rfc_npd_av              : std_logic_vector(11 downto 0);
830 
  signal trn_rfc_ph_av               : std_logic_vector(7 downto 0);
831 
  signal trn_rfc_pd_av               : std_logic_vector(11 downto 0);
832 
  signal trn_rfc_cplh_av             : std_logic_vector(7 downto 0);
833 
  signal trn_rfc_cpld_av             : std_logic_vector(11 downto 0);
834 
  signal trn_rcpl_streaming_n        : std_logic;
835 
  signal cfg_do                      : std_logic_vector(31 downto 0);
836 
  signal cfg_rd_wr_done_n            : std_logic;
837 
  signal cfg_di                      : std_logic_vector(31 downto 0);
838 
  signal cfg_byte_en_n               : std_logic_vector(3 downto 0);
839 
  signal cfg_dwaddr                  : std_logic_vector(9 downto 0);
840 
  signal cfg_wr_en_n                 : std_logic;
841 
  signal cfg_rd_en_n                 : std_logic;
842 
  signal cfg_err_cor_n               : std_logic;
843 
  signal cfg_err_ur_n                : std_logic;
844 
  signal cfg_err_cpl_rdy_n           : std_logic;
845 
  signal cfg_err_ecrc_n              : std_logic;
846 
  signal cfg_err_cpl_timeout_n       : std_logic;
847 
  signal cfg_err_cpl_abort_n         : std_logic;
848 
  signal cfg_err_cpl_unexpect_n      : std_logic;
849 
  signal cfg_err_posted_n            : std_logic;
850 
  signal cfg_err_locked_n            : std_logic;
851 
  signal cfg_err_tlp_cpl_header      : std_logic_vector(47 downto 0);
852 
  signal cfg_interrupt_n             : std_logic;
853 
  signal cfg_interrupt_rdy_n         : std_logic;
854 
  signal cfg_interrupt_mmenable      : std_logic_vector(2 downto 0);
855 
  signal cfg_interrupt_msienable     : std_logic;
856 
  signal cfg_interrupt_di            : std_logic_vector(7 downto 0);
857 
  signal cfg_interrupt_do            : std_logic_vector(7 downto 0);
858 
  signal cfg_interrupt_assert_n      : std_logic;
859 
  signal cfg_turnoff_ok_n            : std_logic;
860 
  signal cfg_to_turnoff_n            : std_logic;
861 
  signal cfg_pm_wake_n               : std_logic;
862 
  signal cfg_pcie_link_state_n       : std_logic_vector(2 downto 0);
863 
  signal cfg_trn_pending_n           : std_logic;
864 
  signal cfg_bus_number              : std_logic_vector(7 downto 0);
865 
  signal cfg_device_number           : std_logic_vector(4 downto 0);
866 
  signal cfg_function_number         : std_logic_vector(2 downto 0);
867 
  signal cfg_dsn                     : std_logic_vector(63 downto 0);
868 
  signal cfg_status                  : std_logic_vector(15 downto 0);
869 
  signal cfg_command                 : std_logic_vector(15 downto 0);
870 
  signal cfg_dstatus                 : std_logic_vector(15 downto 0);
871 
  signal cfg_dcommand                : std_logic_vector(15 downto 0);
872 
  signal cfg_lstatus                 : std_logic_vector(15 downto 0);
873 
  signal cfg_lcommand                : std_logic_vector(15 downto 0);
874 
  signal fast_train_simulation_only  : std_logic;
875 
  signal two_plm_auto_config         : std_logic_vector(1 downto 0);
876 
  signal sys_clk_c                   : std_logic;
877 
  signal sys_reset_n_c               : std_logic;
878 
  signal reset_n                     : std_logic;
879 
 
880 
  signal localId                     : std_logic_vector(15 downto 0);
881 
  signal pcie_link_width             : std_logic_vector( 5 downto 0);
882 
 
883 
  signal synclk2out                  : std_logic;
884 
 
885 
  signal Sim_Zeichen                 : std_logic;
886 
  --
887 
  signal   trn_Blinker               : std_logic;
888 
 
889 
 
890 
 
891 
        signal   DAQ_irq            : std_logic := '0';
892 
        signal   CTL_irq            : std_logic := '0';
893 
        signal   DLM_irq            : std_logic := '0';
894 
 
895 
 
896 
 
897 
--S     SIMONE: Wanxau UserLogic Signals, not Used
898 
        signal   protocol_link_act  : std_logic_vector(2-1 downto 0) := (OTHERS=>'0');
899 
        signal   protocol_rst       : std_logic;
900 
        signal   daq_rstop          : std_logic;
901 
        signal   ctl_rv             : std_logic;
902 
        signal   ctl_rd             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
903 
        signal   ctl_ttake          : std_logic;
904 
        signal   ctl_tv             : std_logic := '0';
905 
        signal   ctl_td             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
906 
        signal   ctl_tstop          : std_logic;
907 
        signal   ctl_reset          : std_logic;
908 
        signal   ctl_status         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
909 
        signal   dlm_tv             : std_logic;
910 
        signal   dlm_td             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
911 
        signal   dlm_rv             : std_logic := '0';
912 
        signal   dlm_rd             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
913 
   signal   tab_we             : std_logic_vector(2-1 downto 0);
914 
   signal   tab_wa             : std_logic_vector(12-1 downto 0);
915 
   signal   tab_wd             : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
916 
   signal   dg_running         : std_logic := '0';
917 
   signal   dg_rst             : STD_LOGIC;
918 
   signal   DG_Mask            : STD_LOGIC;
919 
--S     SIMONE: Wanxau UserLogic Signals, not Used
920 
 
921 
 
922 
 
923 
        -- SIMONE Register: PC-->FPGA
924 
   signal  reg01_tv            : std_logic;
925 
   signal  reg01_td            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
926 
   signal  reg02_tv            : std_logic;
927 
   signal  reg02_td            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
928 
   signal  reg03_tv            : std_logic;
929 
   signal  reg03_td            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
930 
   signal  reg04_tv            : std_logic;
931 
   signal  reg04_td            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
932 
   signal  reg05_tv            : std_logic;
933 
   signal  reg05_td            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
934 
   signal  reg06_tv            : std_logic;
935 
   signal  reg06_td            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
936 
   signal  reg07_tv            : std_logic;
937 
   signal  reg07_td            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
938 
   signal  reg08_tv            : std_logic;
939 
   signal  reg08_td            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
940 
   signal  reg09_tv            : std_logic;
941 
   signal  reg09_td            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
942 
   signal  reg10_tv            : std_logic;
943 
   signal  reg10_td            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
944 
   signal  reg11_tv            : std_logic;
945 
   signal  reg11_td            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
946 
   signal  reg12_tv            : std_logic;
947 
   signal  reg12_td            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
948 
   signal  reg13_tv            : std_logic;
949 
   signal  reg13_td            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
950 
   signal  reg14_tv            : std_logic;
951 
   signal  reg14_td            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
952 
 
953 
        -- SIMONE Register: FPGA-->PC
954 
   signal  reg01_rv            : std_logic := '0';
955 
   signal  reg01_rd            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
956 
   signal  reg02_rv            : std_logic := '0';
957 
   signal  reg02_rd            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
958 
   signal  reg03_rv            : std_logic := '0';
959 
   signal  reg03_rd            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
960 
   signal  reg04_rv            : std_logic := '0';
961 
   signal  reg04_rd            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
962 
   signal  reg05_rv            : std_logic := '0';
963 
   signal  reg05_rd            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
964 
   signal  reg06_rv            : std_logic := '0';
965 
   signal  reg06_rd            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
966 
   signal  reg07_rv            : std_logic := '0';
967 
   signal  reg07_rd            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
968 
   signal  reg08_rv            : std_logic := '0';
969 
   signal  reg08_rd            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
970 
   signal  reg09_rv            : std_logic := '0';
971 
   signal  reg09_rd            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
972 
   signal  reg10_rv            : std_logic := '0';
973 
   signal  reg10_rd            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
974 
   signal  reg11_rv            : std_logic := '0';
975 
   signal  reg11_rd            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
976 
   signal  reg12_rv            : std_logic := '0';
977 
   signal  reg12_rd            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
978 
   signal  reg13_rv            : std_logic := '0';
979 
   signal  reg13_rd            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
980 
   signal  reg14_rv            : std_logic := '0';
981 
   signal  reg14_rd            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
982 
 
983 
   signal  debug_in_1i                   : std_logic_vector(31 downto 0);
984 
   signal  debug_in_2i                   : std_logic_vector(31 downto 0);
985 
   signal  debug_in_3i                   : std_logic_vector(31 downto 0);
986 
   signal  debug_in_4i                   : std_logic_vector(31 downto 0);
987 
 
988 
        signal  user_rst_o          : std_logic;
989 
 
990 
        signal  clk_200MHz          : std_logic;
991 
 
992 
        signal  DMA_Host2Board_Busy : std_logic;
993 
        signal  DMA_Host2Board_Done : std_logic;
994 
 
995 
        signal  DMA_us_Busy         : std_logic;
996 
        signal  DMA_us_Done         : std_logic;
997 
        signal  DMA_ds_Done         : std_logic;
998 
        signal  DMA_ds_Busy         : std_logic;
999 
 
1000 
 
1001 
begin
1002 
 
1003 
 
1004 
   LoopBack_Off_UserLogic:  if not USE_LOOPBACK_TEST generate
1005 
 
1006 
--S SIMONE: My Custom User Logic!!
1007 
  pcie_userlogic_00_x0: PCIe_UserLogic_00
1008 
    port map (
1009 
                inout_logic_cw_ce   => '1',
1010 
                inout_logic_cw_clk  => trn_clk,
1011 
                user_logic_cw_ce    => '1',
1012 
                user_logic_cw_clk   => clk_200MHz,
1013 
      fifo_rd_count  => user_rd_data_count,
1014 
      fifo_rd_dout   => user_rd_dout      ,
1015 
      fifo_rd_empty  => user_rd_empty     ,
1016 
      fifo_rd_pempty => user_rd_pempty    ,
1017 
      fifo_wr_full   => user_wr_full      ,
1018 
      fifo_wr_pfull  => user_wr_pfull     ,
1019 
      fifo_rd_en                => user_rd_en        ,
1020 
      fifo_wr_din       => user_wr_din       ,
1021 
      fifo_wr_en                => user_wr_en        ,
1022 
      fifo_rd_valid     => user_rd_valid     ,
1023 
      fifo_wr_count  => user_wr_data_count,
1024 
      bram_rd_addr      => user_rd_addrB     ,
1025 
      bram_wr_addr      => user_wr_addrA     ,
1026 
      bram_wr_din       => user_wr_dinA      ,
1027 
      bram_wr_en                => user_wr_weA       ,
1028 
      bram_rd_dout   => user_rd_doutB     ,
1029 
                DMA_Host2Board_Busy => DMA_Host2Board_Busy,
1030 
                DMA_Host2Board_Done => DMA_Host2Board_Done,
1031 
                reg01_td                => reg01_td,
1032 
      reg01_tv          => reg01_tv,
1033 
      reg02_td          => reg02_td,
1034 
      reg02_tv          => reg02_tv,
1035 
      reg03_td          => reg03_td,
1036 
      reg03_tv          => reg03_tv,
1037 
      reg04_td          => reg04_td,
1038 
      reg04_tv          => reg04_tv,
1039 
      reg05_td          => reg05_td,
1040 
      reg05_tv          => reg05_tv,
1041 
      reg06_td          => reg06_td,
1042 
      reg06_tv          => reg06_tv,
1043 
      reg07_td          => reg07_td,
1044 
      reg07_tv          => reg07_tv,
1045 
      reg08_td          => reg08_td,
1046 
      reg08_tv          => reg08_tv,
1047 
      reg09_td          => reg09_td,
1048 
      reg09_tv          => reg09_tv,
1049 
      reg10_td          => reg10_td,
1050 
      reg10_tv          => reg10_tv,
1051 
      reg11_td          => reg11_td,
1052 
      reg11_tv          => reg11_tv,
1053 
      reg12_td          => reg12_td,
1054 
      reg12_tv          => reg12_tv,
1055 
      reg13_td          => reg13_td,
1056 
      reg13_tv          => reg13_tv,
1057 
      reg14_td          => reg14_td,
1058 
      reg14_tv          => reg14_tv,
1059 
      reg01_rd          => reg01_rd,
1060 
      reg01_rv          => reg01_rv,
1061 
      reg02_rd          => reg02_rd,
1062 
      reg02_rv          => reg02_rv,
1063 
      reg03_rd          => reg03_rd,
1064 
      reg03_rv          => reg03_rv,
1065 
      reg04_rd          => reg04_rd,
1066 
      reg04_rv          => reg04_rv,
1067 
      reg05_rd          => reg05_rd,
1068 
      reg05_rv          => reg05_rv,
1069 
      reg06_rd          => reg06_rd,
1070 
      reg06_rv          => reg06_rv,
1071 
      reg07_rd          => reg07_rd,
1072 
      reg07_rv          => reg07_rv,
1073 
      reg08_rd          => reg08_rd,
1074 
      reg08_rv          => reg08_rv,
1075 
      reg09_rd          => reg09_rd,
1076 
      reg09_rv          => reg09_rv,
1077 
      reg10_rd          => reg10_rd,
1078 
      reg10_rv          => reg10_rv,
1079 
      reg11_rd          => reg11_rd,
1080 
      reg11_rv          => reg11_rv,
1081 
      reg12_rd          => reg12_rd,
1082 
      reg12_rv          => reg12_rv,
1083 
      reg13_rd          => reg13_rd,
1084 
      reg13_rv          => reg13_rv,
1085 
      reg14_rd          => reg14_rd,
1086 
      reg14_rv          => reg14_rv,
1087 
                user_int_1o    => CTL_irq,
1088 
                user_int_2o    => DAQ_irq,
1089 
                user_int_3o    => DLM_irq,
1090 
      debug_in_1i    => debug_in_1i,
1091 
      debug_in_2i    => debug_in_2i,
1092 
      debug_in_3i    => debug_in_3i,
1093 
      debug_in_4i    => debug_in_4i,
1094 
      rst_i                     => trn_reset_n,
1095 
      rst_o                     => user_rst_o
1096 
    );
1097 
 
1098 
   end generate;
1099 
 
1100 
        DMA_Host2Board_Busy <= '0'; --DMA_ds_Busy;
1101 
        DMA_Host2Board_Done <= DMA_ds_Done;
1102 
   LEDs_IO_pin(5) <= DMA_ds_Done;
1103 
        LEDs_IO_pin(7) <= DMA_us_Done;
1104 
 
1105 
 
1106 
 
1107 
   sys_reset_n_ibuf : IBUF
1108 
      port map (
1109 
                 O      =>  sys_reset_n_c,
1110 
                 I      =>  sys_reset_n
1111 
                );
1112 
 
1113 
   refclk_ibuf : IBUFDS_GTXE1
1114 
      port map (
1115 
                 O      =>  sys_clk_c,
1116 
                 ODIV2  =>  open,
1117 
                 I      =>  sys_clk_p,
1118 
                 IB     =>  sys_clk_n,
1119 
                 CEB    =>  '0'
1120 
                );
1121 
 
1122 
   userclk_ibuf : IBUFDS
1123 
      port map (
1124 
                 O  => clk_200MHz,
1125 
                 I  => userclk_200MHz_p,
1126 
                 IB => userclk_200MHz_n
1127 
                );
1128 
 
1129 
 
1130 
 
1131 
   cfg_err_cor_n              <= '1';
1132 
   cfg_err_ur_n               <= '1';
1133 
   cfg_err_ecrc_n             <= '1';
1134 
   cfg_err_cpl_timeout_n      <= '1';
1135 
   cfg_err_cpl_abort_n        <= '1';
1136 
   cfg_err_cpl_unexpect_n     <= '1';
1137 
   cfg_err_posted_n           <= '0';
1138 
   cfg_err_locked_n           <= '0';
1139 
   cfg_err_tlp_cpl_header     <= (OTHERS=>'0');
1140 
   cfg_trn_pending_n          <= '1';
1141 
   cfg_pm_wake_n              <= '1';
1142 
 
1143 
 
1144 
--
1145 
   trn_fc_sel                 <= (OTHERS=>'0');
1146 
 
1147 
   pl_directed_link_auton     <= '0';
1148 
   pl_directed_link_change    <= (OTHERS=>'0');
1149 
   pl_directed_link_speed     <= '0';
1150 
   pl_directed_link_width     <= (OTHERS=>'0');
1151 
   pl_upstream_prefer_deemph  <= '0';
1152 
 
1153 
   trn_tcfg_gnt_n             <= '0';
1154 
   trn_tstr_n                 <= '0';  -- '1';
1155 
 
1156 
--
1157 
 
1158 
   trn_tdst_dsc_n             <= '1';
1159 
 
1160 
--
1161 
   cfg_di                     <= (OTHERS=>'0');
1162 
   cfg_dwaddr                 <= (OTHERS=>'1');
1163 
   cfg_byte_en_n              <= (OTHERS=>'1');
1164 
   cfg_wr_en_n                <= '1';
1165 
   cfg_rd_en_n                <= '1';
1166 
   cfg_dsn      <= X"00000001" &  X"01" & X"000A35";   -- //this is taken from GUI -
1167 
 
1168 
   cfg_turnoff_ok_n           <= '0';
1169 
 
1170 
 
1171 
   localId                    <= cfg_bus_number & cfg_device_number & cfg_function_number;
1172 
 
1173 
   pcie_link_width            <= cfg_lstatus(9 downto 4);
1174 
 
1175 
 
1176 
 
1177 
   trn_lnk_up_n_int_i: FDCP
1178 
     generic map (
1179 
                 INIT  => '1'
1180 
             )
1181 
     port map (
1182 
               Q     =>  trn_lnk_up_n,
1183 
               D     =>  trn_lnk_up_n_int1,
1184 
               C     =>  trn_clk,
1185 
               CLR   =>  '0',
1186 
               PRE   =>  '0'
1187 
              );
1188 
 
1189 
 
1190 
   trn_reset_n_i: FDCP
1191 
     generic map (
1192 
                 INIT  => '1'
1193 
              )
1194 
     port map (
1195 
               Q     =>  trn_reset_n,
1196 
               D     =>  trn_reset_n_int1,
1197 
               C     =>  trn_clk,
1198 
               CLR   =>  '0',
1199 
               PRE   =>  '0'
1200 
              );
1201 
 
1202 
 
1203 
-- --------------------------------------------------------------
1204 
-- --------------------------------------------------------------
1205 
 
1206 
make4Lanes: if pcieLanes = 4 generate
1207 
--S pcieCore : v6_pcie_v1_7_x1
1208 
    pcieCore : v6_pcie_v1_7_x4
1209 
    generic map (
1210 
                 PL_FAST_TRAIN  => FALSE
1211 
             )
1212 
    port map (
1213 
 
1214 
      ---------------------------------------------------------
1215 
      -- 1. PCI Express (pci_exp) Interface
1216 
      ---------------------------------------------------------
1217 
 
1218 
      -- Tx
1219 
      pci_exp_txp       =>     pci_exp_txp           ,
1220 
      pci_exp_txn       =>     pci_exp_txn           ,
1221 
 
1222 
      -- Rx
1223 
      pci_exp_rxp       =>     pci_exp_rxp           ,
1224 
      pci_exp_rxn       =>     pci_exp_rxn           ,
1225 
 
1226 
      ---------------------------------------------------------
1227 
      -- 2. Transaction (TRN) Interface
1228 
      ---------------------------------------------------------
1229 
 
1230 
      -- Common
1231 
      trn_clk           =>     trn_clk               ,
1232 
      trn_reset_n       =>     trn_reset_n_int1      ,
1233 
      trn_lnk_up_n      =>     trn_lnk_up_n_int1     ,
1234 
 
1235 
      -- Tx
1236 
      trn_tbuf_av       =>     trn_tbuf_av           ,
1237 
      trn_tcfg_req_n    =>     trn_tcfg_req_n        ,
1238 
      trn_terr_drop_n   =>     trn_terr_drop_n       ,
1239 
      trn_tdst_rdy_n    =>     trn_tdst_rdy_n        ,
1240 
      trn_td            =>     trn_td                ,
1241 
      trn_trem_n        =>     trn_trem_n(0)         ,
1242 
      trn_tsof_n        =>     trn_tsof_n            ,
1243 
      trn_teof_n        =>     trn_teof_n            ,
1244 
      trn_tsrc_rdy_n    =>     trn_tsrc_rdy_n        ,
1245 
      trn_tsrc_dsc_n    =>     trn_tsrc_dsc_n        ,
1246 
      trn_terrfwd_n     =>     trn_terrfwd_n         ,
1247 
      trn_tcfg_gnt_n    =>     trn_tcfg_gnt_n        ,
1248 
      trn_tstr_n        =>     trn_tstr_n            ,
1249 
 
1250 
      -- Rx
1251 
      trn_rd            =>     trn_rd                ,
1252 
      trn_rrem_n        =>     trn_rrem_n(0)         ,
1253 
      trn_rsof_n        =>     trn_rsof_n            ,
1254 
      trn_reof_n        =>     trn_reof_n            ,
1255 
      trn_rsrc_rdy_n    =>     trn_rsrc_rdy_n        ,
1256 
      trn_rsrc_dsc_n    =>     trn_rsrc_dsc_n        ,
1257 
      trn_rerrfwd_n     =>     trn_rerrfwd_n         ,
1258 
      trn_rbar_hit_n    =>     trn_rbar_hit_n        ,
1259 
      trn_rdst_rdy_n    =>     trn_rdst_rdy_n        ,
1260 
      trn_rnp_ok_n      =>     trn_rnp_ok_n          ,
1261 
 
1262 
      -- Flow Control
1263 
      trn_fc_cpld       =>     trn_fc_cpld           ,
1264 
      trn_fc_cplh       =>     trn_fc_cplh           ,
1265 
      trn_fc_npd        =>     trn_fc_npd            ,
1266 
      trn_fc_nph        =>     trn_fc_nph            ,
1267 
      trn_fc_pd         =>     trn_fc_pd             ,
1268 
      trn_fc_ph         =>     trn_fc_ph             ,
1269 
      trn_fc_sel        =>     trn_fc_sel            ,
1270 
 
1271 
 
1272 
      ---------------------------------------------------------
1273 
      -- 3. Configuration (CFG) Interface
1274 
      ---------------------------------------------------------
1275 
 
1276 
      cfg_do                   =>     cfg_do                     ,
1277 
      cfg_rd_wr_done_n         =>     cfg_rd_wr_done_n           ,
1278 
      cfg_di                   =>     cfg_di                     ,
1279 
      cfg_byte_en_n            =>     cfg_byte_en_n              ,
1280 
      cfg_dwaddr               =>     cfg_dwaddr                 ,
1281 
      cfg_wr_en_n              =>     cfg_wr_en_n                ,
1282 
      cfg_rd_en_n              =>     cfg_rd_en_n                ,
1283 
 
1284 
      cfg_err_cor_n            =>     cfg_err_cor_n              ,
1285 
      cfg_err_ur_n             =>     cfg_err_ur_n               ,
1286 
      cfg_err_ecrc_n           =>     cfg_err_ecrc_n             ,
1287 
      cfg_err_cpl_timeout_n    =>     cfg_err_cpl_timeout_n      ,
1288 
      cfg_err_cpl_abort_n      =>     cfg_err_cpl_abort_n        ,
1289 
      cfg_err_cpl_unexpect_n   =>     cfg_err_cpl_unexpect_n     ,
1290 
      cfg_err_posted_n         =>     cfg_err_posted_n           ,
1291 
      cfg_err_locked_n         =>     cfg_err_locked_n           ,
1292 
      cfg_err_tlp_cpl_header   =>     cfg_err_tlp_cpl_header     ,
1293 
      cfg_err_cpl_rdy_n        =>     cfg_err_cpl_rdy_n          ,
1294 
      cfg_interrupt_n          =>     cfg_interrupt_n            ,
1295 
      cfg_interrupt_rdy_n      =>     cfg_interrupt_rdy_n        ,
1296 
      cfg_interrupt_assert_n   =>     cfg_interrupt_assert_n     ,
1297 
      cfg_interrupt_di         =>     cfg_interrupt_di           ,
1298 
      cfg_interrupt_do         =>     cfg_interrupt_do           ,
1299 
      cfg_interrupt_mmenable   =>     cfg_interrupt_mmenable     ,
1300 
      cfg_interrupt_msienable  =>     cfg_interrupt_msienable    ,
1301 
      cfg_interrupt_msixenable =>     cfg_interrupt_msixenable   ,
1302 
      cfg_interrupt_msixfm     =>     cfg_interrupt_msixfm       ,
1303 
      cfg_turnoff_ok_n         =>     cfg_turnoff_ok_n           ,
1304 
      cfg_to_turnoff_n         =>     cfg_to_turnoff_n           ,
1305 
      cfg_trn_pending_n        =>     cfg_trn_pending_n          ,
1306 
      cfg_pm_wake_n            =>     cfg_pm_wake_n              ,
1307 
      cfg_bus_number           =>     cfg_bus_number             ,
1308 
      cfg_device_number        =>     cfg_device_number          ,
1309 
      cfg_function_number      =>     cfg_function_number        ,
1310 
      cfg_status               =>     cfg_status                 ,
1311 
      cfg_command              =>     cfg_command                ,
1312 
      cfg_dstatus              =>     cfg_dstatus                ,
1313 
      cfg_dcommand             =>     cfg_dcommand               ,
1314 
      cfg_lstatus              =>     cfg_lstatus                ,
1315 
      cfg_lcommand             =>     cfg_lcommand               ,
1316 
      cfg_dcommand2            =>     cfg_dcommand2              ,
1317 
      cfg_pcie_link_state_n    =>     cfg_pcie_link_state_n      ,
1318 
      cfg_dsn                  =>     cfg_dsn                    ,
1319 
 
1320 
      ---------------------------------------------------------
1321 
      -- 4. Physical Layer Control and Status (PL) Interface
1322 
      ---------------------------------------------------------
1323 
 
1324 
      pl_initial_link_width            =>     pl_initial_link_width           ,
1325 
      pl_lane_reversal_mode            =>     pl_lane_reversal_mode           ,
1326 
      pl_link_gen2_capable             =>     pl_link_gen2_capable            ,
1327 
      pl_link_partner_gen2_supported   =>     pl_link_partner_gen2_supported  ,
1328 
      pl_link_upcfg_capable            =>     pl_link_upcfg_capable           ,
1329 
      pl_ltssm_state                   =>     pl_ltssm_state                  ,
1330 
      pl_received_hot_rst              =>     pl_received_hot_rst             ,
1331 
      pl_sel_link_rate                 =>     pl_sel_link_rate                ,
1332 
      pl_sel_link_width                =>     pl_sel_link_width               ,
1333 
      pl_directed_link_auton           =>     pl_directed_link_auton          ,
1334 
      pl_directed_link_change          =>     pl_directed_link_change         ,
1335 
      pl_directed_link_speed           =>     pl_directed_link_speed          ,
1336 
      pl_directed_link_width           =>     pl_directed_link_width          ,
1337 
      pl_upstream_prefer_deemph        =>     pl_upstream_prefer_deemph       ,
1338 
 
1339 
      ---------------------------------------------------------
1340 
      -- 5. System  (SYS) Interface
1341 
      ---------------------------------------------------------
1342 
 
1343 
      sys_clk                          =>     sys_clk_c     ,
1344 
      sys_reset_n                      =>     sys_reset_n_c
1345 
 
1346 
);
1347 
 
1348 
 end generate;
1349 
 
1350 
 
1351 
-- ---------------------------------------------------------------
1352 
-- tlp control module
1353 
-- ---------------------------------------------------------------
1354 
 
1355 
   trn_rrem_n(7 downto 1) <= X"0" & trn_rrem_n(0) & trn_rrem_n(0) & trn_rrem_n(0);
1356 
 
1357 
   theTlpControl:
1358 
   tlpControl
1359 
   port map (
1360 
 
1361 
           mbuf_UserFull               => '0'                 ,
1362 
           trn_Blinker                 => trn_Blinker         ,
1363 
 
1364 
           -- Interrupter triggers
1365 
           DAQ_irq                     =>  DAQ_irq            ,  -- IN  std_logic;
1366 
           CTL_irq                     =>  CTL_irq            ,  -- IN  std_logic;
1367 
           DLM_irq                     =>  DLM_irq            ,  -- IN  std_logic;
1368 
 
1369 
 
1370 
--S     SIMONE: Wanxau UserLogic Signals, not Used
1371 
           -- DCB protocol interface
1372 
           protocol_link_act           =>  protocol_link_act  ,  -- IN  std_logic_vector(2-1 downto 0);
1373 
           protocol_rst                =>  protocol_rst       ,  -- OUT std_logic;
1374 
           Link_Buf_Full               =>  daq_rstop          ,  -- IN  std_logic;
1375 
           -- Fabric side: CTL Rx
1376 
           ctl_rv                      =>  ctl_rv             ,  -- OUT std_logic;
1377 
           ctl_rd                      =>  ctl_rd             ,  -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1378 
           -- Fabric side: CTL Tx
1379 
           ctl_ttake                   =>  ctl_ttake          ,  -- OUT std_logic;
1380 
           ctl_tv                      =>  ctl_tv             ,  -- IN  std_logic;
1381 
           ctl_td                      =>  ctl_td             ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1382 
           ctl_tstop                   =>  ctl_tstop          ,  -- OUT std_logic;
1383 
           ctl_reset                   =>  ctl_reset          ,  -- OUT std_logic;
1384 
           ctl_status                  =>  ctl_status         ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1385 
           -- Fabric side: DLM Rx
1386 
           dlm_rv                      =>  dlm_rv             ,  -- OUT std_logic;
1387 
           dlm_rd                      =>  dlm_rd             ,  -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1388 
           -- Fabric side: DLM Tx
1389 
           dlm_tv                      =>  dlm_tv             ,  -- IN  std_logic;
1390 
           dlm_td                      =>  dlm_td             ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1391 
           tab_we                      =>  tab_we             ,  -- OUT std_logic_vector(2-1 downto 0);
1392 
           tab_wa                      =>  tab_wa             ,  -- OUT std_logic_vector(12-1 downto 0);
1393 
           tab_wd                      =>  tab_wd             ,  -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1394 
           DG_is_Running               =>  dg_running         ,  -- IN  std_logic;
1395 
           DG_Reset                    =>  dg_rst             ,  -- OUT   STD_LOGIC;
1396 
           DG_Mask                     =>  dg_mask            ,  -- OUT   STD_LOGIC
1397 
--S     SIMONE: Wanxau UserLogic Signals, not Used
1398 
 
1399 
 
1400 
           -- SIMONE Register: PC-->FPGA
1401 
           reg01_tv                     => reg01_tv,
1402 
           reg01_td                     => reg01_td,
1403 
           reg02_tv                     => reg02_tv,
1404 
           reg02_td                     => reg02_td,
1405 
           reg03_tv                     => reg03_tv,
1406 
           reg03_td                     => reg03_td,
1407 
           reg04_tv                     => reg04_tv,
1408 
           reg04_td                     => reg04_td,
1409 
           reg05_tv                     => reg05_tv,
1410 
           reg05_td                     => reg05_td,
1411 
           reg06_tv                     => reg06_tv,
1412 
           reg06_td                     => reg06_td,
1413 
           reg07_tv                     => reg07_tv,
1414 
           reg07_td                     => reg07_td,
1415 
           reg08_tv                     => reg08_tv,
1416 
           reg08_td                     => reg08_td,
1417 
           reg09_tv                     => reg09_tv,
1418 
           reg09_td                     => reg09_td,
1419 
           reg10_tv                     => reg10_tv,
1420 
           reg10_td                     => reg10_td,
1421 
           reg11_tv                     => reg11_tv,
1422 
           reg11_td                     => reg11_td,
1423 
           reg12_tv                     => reg12_tv,
1424 
           reg12_td                     => reg12_td,
1425 
           reg13_tv                     => reg13_tv,
1426 
           reg13_td                     => reg13_td,
1427 
           reg14_tv                     => reg14_tv,
1428 
           reg14_td                     => reg14_td,
1429 
 
1430 
           -- SIMONE Register: FPGA-->PC
1431 
           reg01_rv                     => reg01_rv,
1432 
           reg01_rd                     => reg01_rd,
1433 
           reg02_rv                     => reg02_rv,
1434 
           reg02_rd                     => reg02_rd,
1435 
           reg03_rv                     => reg03_rv,
1436 
           reg03_rd                     => reg03_rd,
1437 
           reg04_rv                     => reg04_rv,
1438 
           reg04_rd                     => reg04_rd,
1439 
           reg05_rv                     => reg05_rv,
1440 
           reg05_rd                     => reg05_rd,
1441 
           reg06_rv                     => reg06_rv,
1442 
           reg06_rd                     => reg06_rd,
1443 
           reg07_rv                     => reg07_rv,
1444 
           reg07_rd                     => reg07_rd,
1445 
           reg08_rv                     => reg08_rv,
1446 
           reg08_rd                     => reg08_rd,
1447 
           reg09_rv                     => reg09_rv,
1448 
           reg09_rd                     => reg09_rd,
1449 
           reg10_rv                     => reg10_rv,
1450 
           reg10_rd                     => reg10_rd,
1451 
           reg11_rv                     => reg11_rv,
1452 
           reg11_rd                     => reg11_rd,
1453 
           reg12_rv                     => reg12_rv,
1454 
           reg12_rd                     => reg12_rd,
1455 
           reg13_rv                     => reg13_rv,
1456 
           reg13_rd                     => reg13_rd,
1457 
           reg14_rv                     => reg14_rv,
1458 
           reg14_rd                     => reg14_rd,
1459 
 
1460 
                          -- SIMONE debug signals
1461 
                          debug_in_1i                  => debug_in_1i,
1462 
                          debug_in_2i                  => debug_in_2i,
1463 
                          debug_in_3i                  => debug_in_3i,
1464 
                          debug_in_4i                  => debug_in_4i,
1465 
 
1466 
           -- Event Buffer FIFO interface
1467 
           eb_FIFO_we                  => eb_we               , --  OUT std_logic;
1468 
           eb_FIFO_wsof                => eb_wsof             , --  OUT std_logic;
1469 
           eb_FIFO_weof                => eb_weof             , --  OUT std_logic;
1470 
           eb_FIFO_din                 => eb_din(C_DBUS_WIDTH-1 downto 0) , --  OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1471 
 
1472 
           eb_FIFO_re                  => eb_re               , --  OUT std_logic;
1473 
           eb_FIFO_empty               => eb_empty            , --  IN  std_logic;
1474 
           eb_FIFO_qout                => eb_dout(C_DBUS_WIDTH-1 downto 0) , --  IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1475 
           eb_FIFO_data_count          => eb_data_count       , --  IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
1476 
 
1477 
           eb_FIFO_ow                  => eb_FIFO_ow          , --  IN  std_logic;
1478 
 
1479 
           pio_reading_status          => pio_reading_status  , --  OUT std_logic;
1480 
 
1481 
           eb_FIFO_Status              => eb_FIFO_Status      , --  IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1482 
           eb_FIFO_Rst                 => eb_rst              , --  OUT std_logic;
1483 
                          H2B_FIFO_Status                                       => H2B_FIFO_Status     ,
1484 
                          B2H_FIFO_Status                                       => B2H_FIFO_Status     ,
1485 
 
1486 
           -- Debugging signals
1487 
           DMA_us_Done                 => DMA_us_Done         , -- OUT std_logic;
1488 
           DMA_us_Busy                 => DMA_us_Busy         , -- OUT std_logic;
1489 
           DMA_us_Busy_LED             => LEDs_IO_pin(6)      , -- OUT std_logic;
1490 
           DMA_ds_Done                 => DMA_ds_Done         , -- OUT std_logic;
1491 
           DMA_ds_Busy                 => DMA_ds_Busy         , -- OUT std_logic;
1492 
           DMA_ds_Busy_LED             => LEDs_IO_pin(4)      , -- OUT std_logic;
1493 
 
1494 
           -------------------
1495 
           -- DDR Interface
1496 
           DDR_Ready                   => DDR_Ready           , --  IN    std_logic;
1497 
 
1498 
           DDR_wr_sof                  => DDR_wr_sof          , --  OUT   std_logic;
1499 
           DDR_wr_eof                  => DDR_wr_eof          , --  OUT   std_logic;
1500 
           DDR_wr_v                    => DDR_wr_v            , --  OUT   std_logic;
1501 
           DDR_wr_FA                   => DDR_wr_FA           , --  OUT   std_logic;
1502 
           DDR_wr_Shift                => DDR_wr_Shift        , --  OUT   std_logic;
1503 
           DDR_wr_Mask                 => DDR_wr_Mask         , --  OUT   std_logic_vector(2-1 downto 0);
1504 
           DDR_wr_din                  => DDR_wr_din          , --  OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1505 
           DDR_wr_full                 => DDR_wr_full         , --  IN    std_logic;
1506 
 
1507 
           DDR_rdc_sof                 => DDR_rdc_sof         , --  OUT   std_logic;
1508 
           DDR_rdc_eof                 => DDR_rdc_eof         , --  OUT   std_logic;
1509 
           DDR_rdc_v                   => DDR_rdc_v           , --  OUT   std_logic;
1510 
           DDR_rdc_FA                  => DDR_rdc_FA          , --  OUT   std_logic;
1511 
           DDR_rdc_Shift               => DDR_rdc_Shift       , --  OUT   std_logic;
1512 
           DDR_rdc_din                 => DDR_rdc_din         , --  OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1513 
           DDR_rdc_full                => DDR_rdc_full        , --  IN    std_logic;
1514 
 
1515 
           -- DDR payload FIFO Read Port
1516 
           DDR_FIFO_RdEn               => DDR_FIFO_RdEn      ,  -- OUT std_logic;
1517 
           DDR_FIFO_Empty              => DDR_FIFO_Empty     ,  -- IN  std_logic;
1518 
           DDR_FIFO_RdQout             => DDR_FIFO_RdQout    ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1519 
 
1520 
           -------------------
1521 
           -- Transaction Interface
1522 
           trn_lnk_up_n                => trn_lnk_up_n            ,
1523 
           trn_rsrc_dsc_n              => trn_rsrc_dsc_n          ,
1524 
           trn_rnp_ok_n                => trn_rnp_ok_n            ,
1525 
           trn_tsrc_dsc_n              => trn_tsrc_dsc_n          ,
1526 
           trn_tdst_dsc_n              => trn_tdst_dsc_n          ,
1527 
           trn_tbuf_av                 => trn_tbuf_av             ,
1528 
           trn_terrfwd_n               => trn_terrfwd_n           ,
1529 
 
1530 
           trn_clk                     => trn_clk                 ,
1531 
           trn_reset_n                 => trn_reset_n             ,
1532 
           trn_rsrc_rdy_n              => trn_rsrc_rdy_n          ,
1533 
           trn_tdst_rdy_n              => trn_tdst_rdy_n          ,
1534 
           trn_rsof_n                  => trn_rsof_n              ,
1535 
           trn_reof_n                  => trn_reof_n              ,
1536 
           trn_rerrfwd_n               => trn_rerrfwd_n           ,
1537 
           trn_rrem_n                  => trn_rrem_n              ,
1538 
           trn_rd                      => trn_rd                  ,
1539 
 
1540 
           cfg_interrupt_n             => cfg_interrupt_n         ,
1541 
           cfg_interrupt_rdy_n         => cfg_interrupt_rdy_n     ,
1542 
           cfg_interrupt_mmenable      => cfg_interrupt_mmenable  ,
1543 
           cfg_interrupt_msienable     => cfg_interrupt_msienable ,
1544 
           cfg_interrupt_di            => cfg_interrupt_di        ,
1545 
           cfg_interrupt_do            => cfg_interrupt_do        ,
1546 
           cfg_interrupt_assert_n      => cfg_interrupt_assert_n  ,
1547 
 
1548 
           trn_rbar_hit_n              => trn_rbar_hit_n          ,
1549 
           trn_tsrc_rdy_n              => trn_tsrc_rdy_n          ,
1550 
           trn_rdst_rdy_n              => trn_rdst_rdy_n          ,
1551 
           trn_tsof_n                  => trn_tsof_n              ,
1552 
           trn_teof_n                  => trn_teof_n              ,
1553 
           trn_trem_n                  => trn_trem_n              ,
1554 
           trn_td                      => trn_td                  ,
1555 
 
1556 
           Format_Shower               => Format_Shower           ,
1557 
 
1558 
           cfg_dcommand                => cfg_dcommand            ,
1559 
           pcie_link_width             => pcie_link_width         ,
1560 
           localId                     => localId
1561 
           );
1562 
 
1563 
 
1564 
  -- -----------------------------------------------------------------------
1565 
  --  DDR SDRAM: control module USER LOGIC (2 BRAM Module:
1566 
  -- -----------------------------------------------------------------------
1567 
 
1568 
 
1569 
   LoopBack_BRAM_Off:  if not USE_LOOPBACK_TEST generate
1570 
 
1571 
   DDRs_ctrl_module:
1572 
   bram_DDRs_Control
1573 
   GENERIC MAP (
1574 
                C_ASYNFIFO_WIDTH    => 72 ,
1575 
                P_SIMULATION        => FALSE
1576 
               )
1577 
   PORT MAP(
1578 
 
1579 
      user_wr_weA             =>  user_wr_weA   ,
1580 
      user_wr_addrA           =>  user_wr_addrA ,
1581 
      user_wr_dinA            =>  user_wr_dinA  ,
1582 
      user_rd_addrB           =>  user_rd_addrB ,
1583 
      user_rd_doutB           =>  user_rd_doutB ,
1584 
      user_rd_clk             =>  clk_200MHz    ,
1585 
      user_wr_clk             =>  clk_200MHz    ,
1586 
      -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1587 
      DDR_wr_sof               => DDR_wr_sof          , --  IN    std_logic;
1588 
      DDR_wr_eof               => DDR_wr_eof          , --  IN    std_logic;
1589 
      DDR_wr_v                 => DDR_wr_v            , --  IN    std_logic;
1590 
      DDR_wr_FA                => DDR_wr_FA           , --  IN    std_logic;
1591 
      DDR_wr_Shift             => DDR_wr_Shift        , --  IN    std_logic;
1592 
      DDR_wr_Mask              => DDR_wr_Mask         , --  IN    std_logic_vector(2-1 downto 0);
1593 
      DDR_wr_din               => DDR_wr_din          , --  IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1594 
      DDR_wr_full              => DDR_wr_full         , --  OUT   std_logic;
1595 
 
1596 
      DDR_rdc_sof              => DDR_rdc_sof         , --  IN    std_logic;
1597 
      DDR_rdc_eof              => DDR_rdc_eof         , --  IN    std_logic;
1598 
      DDR_rdc_v                => DDR_rdc_v           , --  IN    std_logic;
1599 
      DDR_rdc_FA               => DDR_rdc_FA          , --  IN    std_logic;
1600 
      DDR_rdc_Shift            => DDR_rdc_Shift       , --  IN    std_logic;
1601 
      DDR_rdc_din              => DDR_rdc_din         , --  IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1602 
      DDR_rdc_full             => DDR_rdc_full        , --  OUT   std_logic;
1603 
 
1604 
      -- DDR payload FIFO Read Port
1605 
      DDR_FIFO_RdEn            => DDR_FIFO_RdEn       ,  -- IN    std_logic;
1606 
      DDR_FIFO_Empty           => DDR_FIFO_Empty      ,  -- OUT   std_logic;
1607 
      DDR_FIFO_RdQout          => DDR_FIFO_RdQout     ,  -- OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1608 
 
1609 
      -- Common interface
1610 
      DDR_Ready                => DDR_Ready           , --  OUT   std_logic;
1611 
      DDR_Blinker              => DDR_Blinker         , --  OUT   std_logic;
1612 
      mem_clk                  => trn_clk             , --  IN
1613 
      trn_clk                  => trn_clk             , --  IN    std_logic;
1614 
                Sim_Zeichen              => Sim_Zeichen         , --  OUT   std_logic;
1615 
      trn_reset_n              => trn_reset_n           --  IN    std_logic
1616 
    );
1617 
 
1618 
        end generate;
1619 
 
1620 
 
1621 
 
1622 
   LoopBack_BRAM_On:  if USE_LOOPBACK_TEST generate
1623 
 
1624 
 
1625 
   DDRs_ctrl_module:
1626 
   bram_DDRs_Control_loopback
1627 
   GENERIC MAP (
1628 
                C_ASYNFIFO_WIDTH    => 72 ,
1629 
                P_SIMULATION        => FALSE
1630 
               )
1631 
   PORT MAP(
1632 
 
1633 
      -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1634 
      DDR_wr_sof               => DDR_wr_sof          , --  IN    std_logic;
1635 
      DDR_wr_eof               => DDR_wr_eof          , --  IN    std_logic;
1636 
      DDR_wr_v                 => DDR_wr_v            , --  IN    std_logic;
1637 
      DDR_wr_FA                => DDR_wr_FA           , --  IN    std_logic;
1638 
      DDR_wr_Shift             => DDR_wr_Shift        , --  IN    std_logic;
1639 
      DDR_wr_Mask              => DDR_wr_Mask         , --  IN    std_logic_vector(2-1 downto 0);
1640 
      DDR_wr_din               => DDR_wr_din          , --  IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1641 
      DDR_wr_full              => DDR_wr_full         , --  OUT   std_logic;
1642 
 
1643 
      DDR_rdc_sof              => DDR_rdc_sof         , --  IN    std_logic;
1644 
      DDR_rdc_eof              => DDR_rdc_eof         , --  IN    std_logic;
1645 
      DDR_rdc_v                => DDR_rdc_v           , --  IN    std_logic;
1646 
      DDR_rdc_FA               => DDR_rdc_FA          , --  IN    std_logic;
1647 
      DDR_rdc_Shift            => DDR_rdc_Shift       , --  IN    std_logic;
1648 
      DDR_rdc_din              => DDR_rdc_din         , --  IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1649 
      DDR_rdc_full             => DDR_rdc_full        , --  OUT   std_logic;
1650 
 
1651 
      -- DDR payload FIFO Read Port
1652 
      DDR_FIFO_RdEn            => DDR_FIFO_RdEn       ,  -- IN    std_logic;
1653 
      DDR_FIFO_Empty           => DDR_FIFO_Empty      ,  -- OUT   std_logic;
1654 
      DDR_FIFO_RdQout          => DDR_FIFO_RdQout     ,  -- OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1655 
 
1656 
      -- Common interface
1657 
      DDR_Ready                => DDR_Ready           , --  OUT   std_logic;
1658 
      DDR_Blinker              => DDR_Blinker         , --  OUT   std_logic;
1659 
      mem_clk                  => trn_clk             , --  IN
1660 
      trn_clk                  => trn_clk             , --  IN    std_logic;
1661 
                Sim_Zeichen              => Sim_Zeichen         , --  OUT   std_logic;
1662 
      trn_reset_n              => trn_reset_n           --  IN    std_logic
1663 
    );
1664 
 
1665 
   end generate;
1666 
 
1667 
 
1668 
 
1669 
    LEDs_IO_pin(0)    <= trn_reset_n xor Format_Shower;
1670 
    LEDs_IO_pin(1)    <= trn_lnk_up_n  ;
1671 
    LEDs_IO_pin(2)    <= Format_Shower ;
1672 
    LEDs_IO_pin(3)    <= trn_Blinker   ;
1673 
 
1674 
 
1675 
 
1676 
    ------------------------ -----------------------
1677 
    -- Event Buffer wrapper (FIFO Module: H2B & B2H)
1678 
    ------------------------ -----------------------
1679 
 
1680 
   LoopBack_FIFO_Off:  if not USE_LOOPBACK_TEST generate
1681 
 
1682 
    queue_buffer0:
1683 
    eb_wrapper
1684 
      port map (
1685 
 
1686 
         H2B_wr_clk                     => trn_clk                              ,
1687 
         H2B_wr_en                      => eb_we                                        ,
1688 
         H2B_wr_din                     => eb_din                                       ,
1689 
         H2B_wr_pfull                   => eb_pfull                             ,
1690 
         H2B_wr_full                    => eb_full                              ,
1691 
         H2B_wr_data_count    => H2B_wr_data_count(C_EMU_FIFO_DC_WIDTH-1+1 downto 1) ,
1692 
 
1693 
         H2B_rd_clk           => clk_200MHz                     ,
1694 
                        H2B_rd_en            => user_rd_en              ,
1695 
         H2B_rd_dout          => user_rd_dout           ,
1696 
         H2B_rd_pempty        => user_rd_pempty         ,
1697 
         H2B_rd_empty         => user_rd_empty          ,
1698 
         H2B_rd_valid         => user_rd_valid          ,
1699 
         H2B_rd_data_count    => user_rd_data_count     ,
1700 
 
1701 
                        B2H_wr_clk           => clk_200MHz                      ,
1702 
         B2H_wr_en            => user_wr_en             ,
1703 
         B2H_wr_din           => user_wr_din            ,
1704 
         B2H_wr_pfull         => user_wr_pfull          ,
1705 
         B2H_wr_full          => user_wr_full           ,
1706 
         B2H_wr_data_count    => user_wr_data_count     ,
1707 
 
1708 
 
1709 
         B2H_rd_clk             => trn_clk                              ,
1710 
         B2H_rd_en              => eb_re                                ,
1711 
         B2H_rd_dout            => eb_dout                              ,
1712 
         B2H_rd_pempty          => eb_pempty                            ,
1713 
         B2H_rd_empty           => eb_empty                             ,
1714 
         B2H_rd_valid           => eb_valid                             ,
1715 
         B2H_rd_data_count      => B2H_rd_data_count(C_EMU_FIFO_DC_WIDTH-1+1 downto 1) ,
1716 
 
1717 
         rst                                    => eb_rst
1718 
         );
1719 
 
1720 
 
1721 
 
1722 
                --- 64 bits to 32 bits transformation ( --> Count * 2)---
1723 
      B2H_rd_data_count(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1)
1724 
                        <= C_ALL_ZEROS(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1);
1725 
      B2H_rd_data_count(0) <= '0';
1726 
 
1727 
      H2B_wr_data_count(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1)
1728 
                        <= C_ALL_ZEROS(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1);
1729 
      H2B_wr_data_count(0) <= '0';
1730 
 
1731 
 
1732 
                --- Hybrid FIFO Signal used by PCIe interface and Linux Driver
1733 
      eb_FIFO_ow      <= eb_we_up and eb_full;
1734 
      fifo_reset_done <= not eb_rst;
1735 
      eb_din(72-1 downto C_DBUS_WIDTH) <= (OTHERS=>'0');
1736 
                eb_data_count   <= B2H_rd_data_count;
1737 
 
1738 
                --- Hybrid FIFO Status used by PCIe interface and Linux Driver ---
1739 
                --- read: status ; write: reset H2B and B2H FIFO
1740 
      eb_FIFO_Status(C_DBUS_WIDTH-1 downto C_FIFO_DC_WIDTH+3)
1741 
                           <= (OTHERS=>'0');
1742 
      eb_FIFO_Status(C_FIFO_DC_WIDTH+2 downto 3)
1743 
                           <= B2H_rd_data_count(C_FIFO_DC_WIDTH downto 1);
1744 
      eb_FIFO_Status(2)    <= '0';
1745 
      eb_FIFO_Status(1)    <= eb_pfull;
1746 
      eb_FIFO_Status(0)    <= eb_empty and fifo_reset_done;
1747 
 
1748 
 
1749 
                --- Host2Board FIFO status used by user ---
1750 
                --- read: H2B status ; write: nothing
1751 
      H2B_FIFO_Status(C_DBUS_WIDTH-1 downto C_FIFO_DC_WIDTH+3)
1752 
                           <= (OTHERS=>'0');
1753 
      H2B_FIFO_Status(C_FIFO_DC_WIDTH+2 downto 3)
1754 
                           <= H2B_wr_data_count(C_FIFO_DC_WIDTH downto 1);
1755 
      H2B_FIFO_Status(2)    <= '0';
1756 
      H2B_FIFO_Status(1)    <= eb_pfull;
1757 
      H2B_FIFO_Status(0)    <= eb_full and fifo_reset_done;
1758 
 
1759 
 
1760 
                --- Board2Host FIFO status used by user ---
1761 
                --- read: B2H status ; write: nothing
1762 
      B2H_FIFO_Status(C_DBUS_WIDTH-1 downto C_FIFO_DC_WIDTH+3)
1763 
                           <= (OTHERS=>'0');
1764 
      B2H_FIFO_Status(C_FIFO_DC_WIDTH+2 downto 3)
1765 
                           <= B2H_rd_data_count(C_FIFO_DC_WIDTH downto 1);
1766 
      B2H_FIFO_Status(2)    <= eb_valid;
1767 
      B2H_FIFO_Status(1)    <= eb_pempty;
1768 
      B2H_FIFO_Status(0)    <= eb_empty and fifo_reset_done;
1769 
 
1770 
 
1771 
   end generate;
1772 
 
1773 
   LoopBack_FIFO_On:  if USE_LOOPBACK_TEST generate
1774 
 
1775 
     queue_buffer0:
1776 
     eb_wrapper_loopback
1777 
      port map (
1778 
         wr_clk     => trn_clk   ,  -- eb_wclk   ,
1779 
         wr_en      => eb_we  ,
1780 
         din        => eb_din ,
1781 
         pfull      => eb_pfull  ,
1782 
         full       => eb_full   ,
1783 
 
1784 
         rd_clk     => trn_clk   ,  -- eb_rclk   ,
1785 
         rd_en      => eb_re     ,
1786 
         dout       => eb_dout   ,
1787 
         pempty     => eb_pempty ,
1788 
         empty      => eb_empty  ,
1789 
 
1790 
         data_count => eb_data_count(C_EMU_FIFO_DC_WIDTH-1+1 downto 1) ,
1791 
         rst        => eb_rst
1792 
         );
1793 
 
1794 
     eb_data_count(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1)
1795 
                      <= C_ALL_ZEROS(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1);
1796 
     eb_data_count(0)<= '0';
1797 
     fifo_reset_done <= not eb_rst;
1798 
     eb_FIFO_ow           <= eb_we_up and eb_full;
1799 
     eb_din(72-1 downto C_DBUS_WIDTH)       <= (OTHERS=>'0');
1800 
 
1801 
     eb_FIFO_Status(C_DBUS_WIDTH-1 downto C_FIFO_DC_WIDTH+3)
1802 
                         <= (OTHERS=>'0');
1803 
     eb_FIFO_Status(C_FIFO_DC_WIDTH+2 downto 3)
1804 
                         <= eb_data_count(C_FIFO_DC_WIDTH downto 1);
1805 
     eb_FIFO_Status(2)    <= '0';
1806 
     eb_FIFO_Status(1)    <= eb_pfull;
1807 
     eb_FIFO_Status(0)    <= eb_empty and fifo_reset_done;
1808 
 
1809 
 
1810 
     H2B_FIFO_Status <= (OTHERS=>'0');
1811 
          H2B_FIFO_Status <= (OTHERS=>'0');
1812 
 
1813 
   end generate;
1814 
 
1815 
 
1816 
end Behavioral;

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