1 |
13 |
barabba |
set exename [info nameofexecutable]
|
2 |
|
|
set currenttclshell [file tail [ file rootname $exename ] ]
|
3 |
|
|
if { ! [string match "xtclsh" $currenttclshell] } {
|
4 |
|
|
error "ERROR: Please run xtclsh."
|
5 |
|
|
return
|
6 |
|
|
}
|
7 |
|
|
|
8 |
|
|
namespace eval ::xilinx::dsptool::iseproject {
|
9 |
|
|
|
10 |
|
|
namespace eval ise {}
|
11 |
|
|
namespace export \
|
12 |
|
|
VERBOSITY_QUIET VERBOSITY_ERROR VERBOSITY_WARNING \
|
13 |
|
|
VERBOSITY_INFORMATION VERBOSITY_DEBUG
|
14 |
|
|
|
15 |
|
|
set VERBOSITY_QUIET 0
|
16 |
|
|
set VERBOSITY_ERROR 1
|
17 |
|
|
set VERBOSITY_WARNING 2
|
18 |
|
|
set VERBOSITY_INFORMATION 3
|
19 |
|
|
set VERBOSITY_DEBUG 4
|
20 |
|
|
|
21 |
|
|
#-------------------------------------------------------------------------
|
22 |
|
|
# Checks for a required parameter.
|
23 |
|
|
#
|
24 |
|
|
# @param param Parameter name.
|
25 |
|
|
# @param postproc Post processor.
|
26 |
|
|
# @return the parameter value.
|
27 |
|
|
#-------------------------------------------------------------------------
|
28 |
|
|
proc required_parameter {param {postproc ""}} {
|
29 |
|
|
upvar $param p
|
30 |
|
|
if {![info exists p]} {
|
31 |
|
|
error "Required parameter \"[namespace tail $param]\" is not specified."
|
32 |
|
|
}
|
33 |
|
|
if {$postproc != ""} {
|
34 |
|
|
eval $postproc p
|
35 |
|
|
}
|
36 |
|
|
return $p
|
37 |
|
|
}
|
38 |
|
|
|
39 |
|
|
#-------------------------------------------------------------------------
|
40 |
|
|
# Checks for an optional parameter.
|
41 |
|
|
#
|
42 |
|
|
# @param param Parameter name.
|
43 |
|
|
# @param defval Default value of the parameter if unspecified.
|
44 |
|
|
# @param postproc Post processor.
|
45 |
|
|
# @return the parameter value.
|
46 |
|
|
#-------------------------------------------------------------------------
|
47 |
|
|
proc optional_parameter {param {defval ""} {postproc ""}} {
|
48 |
|
|
upvar $param p
|
49 |
|
|
if {![info exists p]} {
|
50 |
|
|
set p $defval
|
51 |
|
|
}
|
52 |
|
|
if {$postproc != ""} {
|
53 |
|
|
eval $postproc p
|
54 |
|
|
}
|
55 |
|
|
return $p
|
56 |
|
|
}
|
57 |
|
|
|
58 |
|
|
#-------------------------------------------------------------------------
|
59 |
|
|
# Deletes an existing empty parameter.
|
60 |
|
|
#
|
61 |
|
|
# @param param Parameter name.
|
62 |
|
|
#-------------------------------------------------------------------------
|
63 |
|
|
proc clear_empty_parameter {param} {
|
64 |
|
|
upvar $param p
|
65 |
|
|
if {[info exists p] && [expr { [string length $p] == 0 }]} {
|
66 |
|
|
unset p
|
67 |
|
|
}
|
68 |
|
|
}
|
69 |
|
|
|
70 |
|
|
#-------------------------------------------------------------------------
|
71 |
|
|
# Checks a Boolean flag.
|
72 |
|
|
#
|
73 |
|
|
# @param param Parameter name.
|
74 |
|
|
# @param defval Default value of the parameter if unspecified.
|
75 |
|
|
# @return 1 if the flag is specified and is true, or 0 othewise.
|
76 |
|
|
#-------------------------------------------------------------------------
|
77 |
|
|
proc check_flag {param {defval ""}} {
|
78 |
|
|
upvar $param p
|
79 |
|
|
return [expr { [info exists p] && $p }]
|
80 |
|
|
}
|
81 |
|
|
|
82 |
|
|
#-------------------------------------------------------------------------
|
83 |
|
|
# Tests if the current verbosity level is equal to or
|
84 |
|
|
# greater than the target verbosity level.
|
85 |
|
|
#
|
86 |
|
|
# @param level Target verbosity level.
|
87 |
|
|
# @return True if the current verbosity level is equal to or
|
88 |
|
|
# greater than the target verbosity level.
|
89 |
|
|
#-------------------------------------------------------------------------
|
90 |
|
|
proc meet_verbosity {level} {
|
91 |
|
|
set curr_level [subst $[namespace current]::$level]
|
92 |
|
|
return [expr { $param::_VERBOSITY >= $curr_level }]
|
93 |
|
|
}
|
94 |
|
|
|
95 |
|
|
#-------------------------------------------------------------------------
|
96 |
|
|
# Post processor to turn the given parameter to lower case.
|
97 |
|
|
#
|
98 |
|
|
# @param param Parameter name.
|
99 |
|
|
# @return the processed parameter value.
|
100 |
|
|
#-------------------------------------------------------------------------
|
101 |
|
|
proc lowercase_pp {param} {
|
102 |
|
|
upvar $param p
|
103 |
|
|
set p [string tolower $p]
|
104 |
|
|
return $p
|
105 |
|
|
}
|
106 |
|
|
|
107 |
|
|
#-------------------------------------------------------------------------
|
108 |
|
|
# Post processor for the SynthesisTool parameter.
|
109 |
|
|
#
|
110 |
|
|
# @param param Parameter name.
|
111 |
|
|
# @return the processed parameter value.
|
112 |
|
|
#-------------------------------------------------------------------------
|
113 |
|
|
proc synthesis_tool_pp {param} {
|
114 |
|
|
upvar $param p
|
115 |
|
|
switch [string tolower $p] {
|
116 |
|
|
"xst" {
|
117 |
|
|
set p "XST"
|
118 |
|
|
}
|
119 |
|
|
"synplify" {
|
120 |
|
|
set p "Synplify"
|
121 |
|
|
}
|
122 |
|
|
"synplify pro" {
|
123 |
|
|
set p "Synplify Pro"
|
124 |
|
|
}
|
125 |
|
|
default {
|
126 |
|
|
error "Invalid value for parameter \"SynthesisTool\": $p"
|
127 |
|
|
}
|
128 |
|
|
}
|
129 |
|
|
}
|
130 |
|
|
|
131 |
|
|
#-------------------------------------------------------------------------
|
132 |
|
|
# Post processor for the HDLLanguage parameter.
|
133 |
|
|
#
|
134 |
|
|
# @param param Parameter name.
|
135 |
|
|
# @return the processed parameter value.
|
136 |
|
|
#-------------------------------------------------------------------------
|
137 |
|
|
proc hdl_language_pp {param} {
|
138 |
|
|
upvar $param p
|
139 |
|
|
switch [string tolower $p] {
|
140 |
|
|
"vhdl" {
|
141 |
|
|
set p "VHDL"
|
142 |
|
|
}
|
143 |
|
|
"verilog" {
|
144 |
|
|
set p "Verilog"
|
145 |
|
|
}
|
146 |
|
|
default {
|
147 |
|
|
error "Invalid value for parameter \"HDLLanguage\": $p"
|
148 |
|
|
}
|
149 |
|
|
}
|
150 |
|
|
}
|
151 |
|
|
|
152 |
|
|
#-------------------------------------------------------------------------
|
153 |
|
|
# Dumps all variables of a given namespace. The current namespace is used
|
154 |
|
|
# if no namespace is specified.
|
155 |
|
|
#
|
156 |
|
|
# @param ns Target namespace.
|
157 |
|
|
#-------------------------------------------------------------------------
|
158 |
|
|
proc dump_variables {{ns ""}} {
|
159 |
|
|
if {$ns eq ""} {
|
160 |
|
|
set ns [namespace current]
|
161 |
|
|
}
|
162 |
|
|
foreach param [lsort [info vars $ns\::*]] {
|
163 |
|
|
upvar $param p
|
164 |
|
|
# TODO : print array, remove upvar
|
165 |
|
|
puts [namespace tail $param]\ =\ $p
|
166 |
|
|
}
|
167 |
|
|
}
|
168 |
|
|
|
169 |
|
|
#-------------------------------------------------------------------------
|
170 |
|
|
# Obtains a new unique command name for the given command.
|
171 |
|
|
#
|
172 |
|
|
# @param cmd Fully qualified command name.
|
173 |
|
|
# @return fully qualified name of the new command.
|
174 |
|
|
#-------------------------------------------------------------------------
|
175 |
|
|
proc unique_command_name {cmd} {
|
176 |
|
|
upvar _unique_command_id_ id
|
177 |
|
|
if {![info exists id]} {
|
178 |
|
|
set id 0
|
179 |
|
|
}
|
180 |
|
|
|
181 |
|
|
set ns [namespace qualifiers $cmd]
|
182 |
|
|
set old_name [namespace tail $cmd]
|
183 |
|
|
set new_name "$old_name\_$id\_"
|
184 |
|
|
set eval_ns [expr { $ns eq "" ? "::" : $ns }]
|
185 |
|
|
while { [lsearch [namespace eval $eval_ns {info proc}] $new_name] >= 0 } {
|
186 |
|
|
incr id
|
187 |
|
|
set new_name "$old_name\_$id\_"
|
188 |
|
|
}
|
189 |
|
|
|
190 |
|
|
return "$ns\::$new_name"
|
191 |
|
|
}
|
192 |
|
|
|
193 |
|
|
#-------------------------------------------------------------------------
|
194 |
|
|
# Decorates a command with the given decorator. Unless a new command name
|
195 |
|
|
# is specified, the original command is renamed and then replaced by
|
196 |
|
|
# the decorated command.
|
197 |
|
|
#
|
198 |
|
|
# @param decorator Fully qualified name of the decorator command.
|
199 |
|
|
# @param cmd Fully qualified name of the command to be
|
200 |
|
|
# decorated.
|
201 |
|
|
# @param new_cmd Fully qualified name of the new command.
|
202 |
|
|
#-------------------------------------------------------------------------
|
203 |
|
|
proc decorate_command {decorator cmd {new_cmd ""}} {
|
204 |
|
|
if {[expr {$new_cmd eq ""}] || [expr {$new_cmd eq $cmd}]} {
|
205 |
|
|
set new_cmd [unique_command_name $cmd]
|
206 |
|
|
set s "rename $cmd $new_cmd; \
|
207 |
|
|
proc $cmd {args} { \
|
208 |
|
|
return \[uplevel {$decorator} \[linsert \$args 0 {$cmd} {$new_cmd}\] \] \
|
209 |
|
|
};"
|
210 |
|
|
} else {
|
211 |
|
|
set s "proc $new_cmd {args} { \
|
212 |
|
|
return \[uplevel {$decorator} \[linsert \$args 0 {$new_cmd} {$cmd}\] \] \
|
213 |
|
|
};"
|
214 |
|
|
}
|
215 |
|
|
eval $s
|
216 |
|
|
}
|
217 |
|
|
|
218 |
|
|
#-------------------------------------------------------------------------
|
219 |
|
|
# Decorator that logs a given command without execution.
|
220 |
|
|
#
|
221 |
|
|
# @param invoked_cmd Invoked command.
|
222 |
|
|
# @param actual_cmd Actual command.
|
223 |
|
|
# @param args Additional argument list.
|
224 |
|
|
#-------------------------------------------------------------------------
|
225 |
|
|
proc log_command {invoked_cmd actual_cmd args} {
|
226 |
|
|
if [meet_verbosity VERBOSITY_INFORMATION] {
|
227 |
|
|
set cmd "[namespace qualifiers $actual_cmd][namespace tail $actual_cmd]"
|
228 |
|
|
puts "$cmd $args"
|
229 |
|
|
}
|
230 |
|
|
}
|
231 |
|
|
|
232 |
|
|
#-------------------------------------------------------------------------
|
233 |
|
|
# Decorator that executes a given command.
|
234 |
|
|
#
|
235 |
|
|
# @param invoked_cmd Invoked command.
|
236 |
|
|
# @param actual_cmd Actual command.
|
237 |
|
|
# @param args Additional argument list.
|
238 |
|
|
# @return the command result.
|
239 |
|
|
#-------------------------------------------------------------------------
|
240 |
|
|
proc run_command {invoked_cmd actual_cmd args} {
|
241 |
|
|
set cmd "[namespace qualifiers $actual_cmd][namespace tail $actual_cmd]"
|
242 |
|
|
if [meet_verbosity VERBOSITY_INFORMATION] {
|
243 |
|
|
puts "$cmd $args"
|
244 |
|
|
}
|
245 |
|
|
if [catch { uplevel $actual_cmd $args } result] {
|
246 |
|
|
error "Failed to execute command \"$cmd $args\".\n$result"
|
247 |
|
|
}
|
248 |
|
|
return $result
|
249 |
|
|
}
|
250 |
|
|
|
251 |
|
|
#-------------------------------------------------------------------------
|
252 |
|
|
# Decorates ISE commands with appropriate decorators.
|
253 |
|
|
#-------------------------------------------------------------------------
|
254 |
|
|
proc decorate_ise_commands {} {
|
255 |
|
|
upvar _ise_commands_already_decorated_ decorated
|
256 |
|
|
if [check_flag decorated] {
|
257 |
|
|
return
|
258 |
|
|
} else {
|
259 |
|
|
set decorated True
|
260 |
|
|
}
|
261 |
|
|
|
262 |
|
|
set ise_cmd_list {
|
263 |
|
|
::collection
|
264 |
|
|
::lib_vhdl
|
265 |
|
|
::object
|
266 |
|
|
::partition
|
267 |
|
|
::process
|
268 |
|
|
::project
|
269 |
|
|
::xfile
|
270 |
|
|
}
|
271 |
|
|
if [check_flag param::_DRY_RUN] {
|
272 |
|
|
set decorator [namespace current]::log_command
|
273 |
|
|
} else {
|
274 |
|
|
set decorator [namespace current]::run_command
|
275 |
|
|
}
|
276 |
|
|
foreach cmd $ise_cmd_list {
|
277 |
|
|
set new_cmd "[namespace current]::ise::[namespace tail $cmd]"
|
278 |
|
|
decorate_command $decorator $cmd $new_cmd
|
279 |
|
|
}
|
280 |
|
|
}
|
281 |
|
|
|
282 |
|
|
#-------------------------------------------------------------------------
|
283 |
|
|
# Handles an exception when evaluating the given script and displays an
|
284 |
|
|
# appropriate error message.
|
285 |
|
|
#
|
286 |
|
|
# @param script Script to evaluate.
|
287 |
|
|
# @param msg Message to display upon an exception.
|
288 |
|
|
# @param append_msg Specifies whether any returned error message is
|
289 |
|
|
# also displayed.
|
290 |
|
|
# @return 1 if the script is evaluated successfully, or 0 othewise.
|
291 |
|
|
#-------------------------------------------------------------------------
|
292 |
|
|
proc handle_exception {script {msg ""} {append_msg True}} {
|
293 |
|
|
if [catch { uplevel $script } result] {
|
294 |
|
|
if {$msg eq ""} {
|
295 |
|
|
set msg "An internal error occurred."
|
296 |
|
|
}
|
297 |
|
|
puts stderr "$msg"
|
298 |
|
|
if {$append_msg} {
|
299 |
|
|
puts stderr "\n$result"
|
300 |
|
|
}
|
301 |
|
|
return 0
|
302 |
|
|
}
|
303 |
|
|
return 1
|
304 |
|
|
}
|
305 |
|
|
|
306 |
|
|
#-------------------------------------------------------------------------
|
307 |
|
|
# Processes all project parameters.
|
308 |
|
|
#
|
309 |
|
|
# REQUIRED PARAMETERS
|
310 |
|
|
# ======================================================================
|
311 |
|
|
# Project
|
312 |
|
|
# ISE project name.
|
313 |
|
|
#
|
314 |
|
|
# Family
|
315 |
|
|
# Device family into which the design is implemented.
|
316 |
|
|
#
|
317 |
|
|
# Device
|
318 |
|
|
# Device into which the design is implemented.
|
319 |
|
|
#
|
320 |
|
|
# Package
|
321 |
|
|
# Package for the device being targeted.
|
322 |
|
|
#
|
323 |
|
|
# Speed
|
324 |
|
|
# Speed grade of the device being targeted.
|
325 |
|
|
#
|
326 |
|
|
# ProjectFiles
|
327 |
|
|
# Source files to be added in the project.
|
328 |
|
|
#
|
329 |
|
|
#
|
330 |
|
|
# OPTIONAL PARAMETERS
|
331 |
|
|
# ======================================================================
|
332 |
|
|
# (*) Notes:
|
333 |
|
|
# "::=" denotes the list of supported values for each parameter.
|
334 |
|
|
#
|
335 |
|
|
# ----------------------------------------------------------------------
|
336 |
|
|
#
|
337 |
|
|
# CompilationFlow
|
338 |
|
|
# Compilation flow.
|
339 |
|
|
#
|
340 |
|
|
# TopLevelModule
|
341 |
|
|
# Top-level module of the design.
|
342 |
|
|
#
|
343 |
|
|
# HDLLanguage
|
344 |
|
|
# Preferred language property controls the default setting for
|
345 |
|
|
# process properties that generate HDL output.
|
346 |
|
|
# ::= "VHDL" | "Verilog"
|
347 |
|
|
#
|
348 |
|
|
# SynthesisTool
|
349 |
|
|
# Synthesis tool used for the design.
|
350 |
|
|
# ::= "XST" | "Synplify" | "Synplify Pro"
|
351 |
|
|
#
|
352 |
|
|
# SynthesisConstraintsFile
|
353 |
|
|
# Synthesis constraints file. XCF for XST,
|
354 |
|
|
# SDC for Synplify/Synplify Pro.
|
355 |
|
|
#
|
356 |
|
|
# SynthesisRegisterBalancing
|
357 |
|
|
# Register balancing option of the Synthesis process.
|
358 |
|
|
#
|
359 |
|
|
# SynthesisRegisterDuplication
|
360 |
|
|
# Register duplication option of the Synthesis process.
|
361 |
|
|
#
|
362 |
|
|
# SynthesisRetiming
|
363 |
|
|
# Retiming option of the Synthesis process. Synplify Pro Only.
|
364 |
|
|
# ::= True | False
|
365 |
|
|
#
|
366 |
|
|
# WriteTimingConstraints
|
367 |
|
|
# Specifies whether or not to place timing constraints in the NGC
|
368 |
|
|
# file.
|
369 |
|
|
# ::= True | False
|
370 |
|
|
#
|
371 |
|
|
# WriteVendorConstraints
|
372 |
|
|
# Specifies whether or not to generate vendor constraints file.
|
373 |
|
|
# ::= True | False
|
374 |
|
|
#
|
375 |
|
|
# ReadCores
|
376 |
|
|
# Specifies whether or not black box cores are read for timing
|
377 |
|
|
# and area estimation in order to get better optimization of
|
378 |
|
|
# the rest of the design.
|
379 |
|
|
# ::= True | False
|
380 |
|
|
#
|
381 |
|
|
# InsertIOBuffers
|
382 |
|
|
# Specifies whether or not to infer input/output buffers on all
|
383 |
|
|
# top-level I/O ports of the design.
|
384 |
|
|
# ::= True | False
|
385 |
|
|
#
|
386 |
|
|
# BusDelimiter
|
387 |
|
|
# Specifies the delimiter type used to define the signal vectors in
|
388 |
|
|
# the resulting netlist.
|
389 |
|
|
# ::= "<>" | "[]" | "{}" | "()"
|
390 |
|
|
#
|
391 |
|
|
# HierarchySeparator
|
392 |
|
|
# Hierarchy separator character which will be used in name
|
393 |
|
|
# generation when the design hierarchy is flattened.
|
394 |
|
|
# ::= "/" | "_"
|
395 |
|
|
#
|
396 |
|
|
# KeepHierarchy
|
397 |
|
|
# Specifies whether or not the corresponding design unit should be
|
398 |
|
|
# preserved and not merged with the rest of the design.
|
399 |
|
|
# ::= "Yes" | "No" | "Soft"
|
400 |
|
|
#
|
401 |
|
|
# Frequency
|
402 |
|
|
# Global clock frequency for timing-driven synthesis.
|
403 |
|
|
#
|
404 |
|
|
# FanoutLimit
|
405 |
|
|
# Maximum limit of the fanout of nets.
|
406 |
|
|
#
|
407 |
|
|
# MapRegisterDuplication
|
408 |
|
|
# Register duplication option of the Map process.
|
409 |
|
|
#
|
410 |
|
|
# MapEffortLevel
|
411 |
|
|
# Effort level of the Map process.
|
412 |
|
|
#
|
413 |
|
|
# PAREffortLevel
|
414 |
|
|
# Effort level of the Place & Route process.
|
415 |
|
|
#
|
416 |
|
|
# BlockMemoryMapFile
|
417 |
|
|
# Block memory map (.bmm) file for the Data2MEM process.
|
418 |
|
|
#
|
419 |
|
|
# BlockMemoryContentFile
|
420 |
|
|
# Block memory content file for the Data2MEM process.
|
421 |
|
|
#
|
422 |
|
|
# Simulator
|
423 |
|
|
# Tool used for simulation.
|
424 |
|
|
#
|
425 |
|
|
# DesignInstance
|
426 |
|
|
# Design instance name.
|
427 |
|
|
#
|
428 |
|
|
# TestBenchModule
|
429 |
|
|
# Test-bench module.
|
430 |
|
|
#
|
431 |
|
|
# SimulationTime
|
432 |
|
|
# Simulation time.
|
433 |
|
|
#
|
434 |
|
|
# BehavioralSimulationCustomDoFile
|
435 |
|
|
# Custom Do file for the Behavioral Simulation process.
|
436 |
|
|
#
|
437 |
|
|
# PostTranslateSimulationCustomDoFile
|
438 |
|
|
# Custom Do file for the Post-Translate Simulation process.
|
439 |
|
|
#
|
440 |
|
|
# PostMapSimulationCustomDoFile
|
441 |
|
|
# Custom Do file for the Post-Map Simulation process.
|
442 |
|
|
#
|
443 |
|
|
# PostPARSimulationCustomDoFile
|
444 |
|
|
# Custom Do file for the Post-Place & Route Simulation process.
|
445 |
|
|
#
|
446 |
|
|
# ISimCustomProjectFile
|
447 |
|
|
# Custom project file for ISE Simulator.
|
448 |
|
|
#
|
449 |
|
|
# HasVerilogSource
|
450 |
|
|
# Indicate the project contains a Verilog source file.
|
451 |
|
|
#
|
452 |
|
|
# ImplementationStopView
|
453 |
|
|
#
|
454 |
|
|
# ProjectGenerator
|
455 |
|
|
#
|
456 |
|
|
#-------------------------------------------------------------------------
|
457 |
|
|
proc process_parameters {} {
|
458 |
|
|
optional_parameter param::_DRY_RUN False
|
459 |
|
|
optional_parameter param::_VERBOSITY $[namespace current]::VERBOSITY_ERROR
|
460 |
|
|
|
461 |
|
|
required_parameter param::Project
|
462 |
|
|
required_parameter param::Family lowercase_pp
|
463 |
|
|
required_parameter param::Device lowercase_pp
|
464 |
|
|
required_parameter param::Package lowercase_pp
|
465 |
|
|
required_parameter param::Speed
|
466 |
|
|
required_parameter param::ProjectFiles
|
467 |
|
|
|
468 |
|
|
optional_parameter param::CompilationFlow {general}
|
469 |
|
|
optional_parameter param::HDLLanguage {VHDL} hdl_language_pp
|
470 |
|
|
optional_parameter param::SynthesisTool {XST} synthesis_tool_pp
|
471 |
|
|
optional_parameter param::SynthesisRegisterBalancing {No}
|
472 |
|
|
optional_parameter param::SynthesisRegisterDuplication True
|
473 |
|
|
optional_parameter param::SynthesisRetiming True
|
474 |
|
|
optional_parameter param::WriteTimingConstraints False
|
475 |
|
|
optional_parameter param::WriteVendorConstraints False
|
476 |
|
|
optional_parameter param::ReadCores True
|
477 |
|
|
optional_parameter param::InsertIOBuffers True
|
478 |
|
|
set is_vhdl [expr { $param::HDLLanguage eq "VHDL" }]
|
479 |
|
|
optional_parameter param::BusDelimiter [expr { $is_vhdl ? {()} : {[]} }]
|
480 |
|
|
optional_parameter param::HierarchySeparator {/}
|
481 |
|
|
optional_parameter param::KeepHierarchy {No}
|
482 |
|
|
optional_parameter param::HasVerilogSource False
|
483 |
|
|
optional_parameter param::MapRegisterDuplication True
|
484 |
|
|
optional_parameter param::MapEffortLevel {High}
|
485 |
|
|
optional_parameter param::PAREffortLevel {High}
|
486 |
|
|
optional_parameter param::DesignInstance {sysgen_dut}
|
487 |
|
|
|
488 |
|
|
clear_empty_parameter param::TopLevelModule
|
489 |
|
|
clear_empty_parameter param::SynthesisConstraintsFile
|
490 |
|
|
clear_empty_parameter param::Frequency
|
491 |
|
|
clear_empty_parameter param::FanoutLimit
|
492 |
|
|
clear_empty_parameter param::BlockMemoryMapFile
|
493 |
|
|
clear_empty_parameter param::BlockMemoryContentFile
|
494 |
|
|
clear_empty_parameter param::Simulator
|
495 |
|
|
clear_empty_parameter param::TestBenchModule
|
496 |
|
|
clear_empty_parameter param::BehavioralSimulationCustomDoFile
|
497 |
|
|
clear_empty_parameter param::PostTranslateSimulationCustomDoFile
|
498 |
|
|
clear_empty_parameter param::PostMapSimulationCustomDoFile
|
499 |
|
|
clear_empty_parameter param::PostPARSimulationCustomDoFile
|
500 |
|
|
clear_empty_parameter param::ISimCustomProjectFile
|
501 |
|
|
clear_empty_parameter param::ProjectGenerator
|
502 |
|
|
clear_empty_parameter param::ImplementationStopView
|
503 |
|
|
}
|
504 |
|
|
|
505 |
|
|
#-------------------------------------------------------------------------
|
506 |
|
|
# Dumps all parameters.
|
507 |
|
|
#-------------------------------------------------------------------------
|
508 |
|
|
proc dump_parameters {} {
|
509 |
|
|
if [meet_verbosity VERBOSITY_DEBUG] {
|
510 |
|
|
dump_variables param
|
511 |
|
|
}
|
512 |
|
|
}
|
513 |
|
|
|
514 |
|
|
#-------------------------------------------------------------------------
|
515 |
|
|
# Adds source files to the project.
|
516 |
|
|
#-------------------------------------------------------------------------
|
517 |
|
|
proc add_project_files {} {
|
518 |
|
|
foreach p $param::ProjectFiles {
|
519 |
|
|
set filename [file normalize [lindex $p 0]]
|
520 |
|
|
set opts [lrange $p 1 end]
|
521 |
|
|
set nopts [llength $opts]
|
522 |
|
|
if {$nopts % 2 != 0} {
|
523 |
|
|
error "Parameter \"ProjectFiles\" contains an invalid value \"$p\"."
|
524 |
|
|
}
|
525 |
|
|
# Remember it if the project contains a Verilog source file.
|
526 |
|
|
if [string match -nocase "*.v" $filename] {
|
527 |
|
|
set param::HasVerilogSource True
|
528 |
|
|
}
|
529 |
|
|
set args [list ise::xfile add $filename]
|
530 |
|
|
for {set i 0} {$i < $nopts} {set i [expr {$i + 2}]} {
|
531 |
|
|
set key [lindex $opts $i]
|
532 |
|
|
set val [lindex $opts [expr {$i + 1}]]
|
533 |
|
|
switch -- $key {
|
534 |
|
|
"-lib" {
|
535 |
|
|
if {![info exists lib_list($val)]} {
|
536 |
|
|
set lib_list($val) True
|
537 |
|
|
ise::lib_vhdl new $val
|
538 |
|
|
}
|
539 |
|
|
lappend args "-lib_vhdl" $val
|
540 |
|
|
}
|
541 |
|
|
"-view" {
|
542 |
|
|
lappend args "-view" $val
|
543 |
|
|
}
|
544 |
|
|
default {
|
545 |
|
|
error "Parameter \"ProjectFiles\" contains an invalid value \"$p\". Unknown option \"$key\"."
|
546 |
|
|
}
|
547 |
|
|
}
|
548 |
|
|
}
|
549 |
|
|
eval $args
|
550 |
|
|
}
|
551 |
|
|
if [info exists param::TopLevelModule] {
|
552 |
|
|
ise::project set top "/$param::TopLevelModule"
|
553 |
|
|
}
|
554 |
|
|
}
|
555 |
|
|
|
556 |
|
|
#-------------------------------------------------------------------------
|
557 |
|
|
# Sets the general project settings.
|
558 |
|
|
#-------------------------------------------------------------------------
|
559 |
|
|
proc set_project_settings {} {
|
560 |
|
|
ise::project set family $param::Family
|
561 |
|
|
ise::project set device $param::Device
|
562 |
|
|
ise::project set package $param::Package
|
563 |
|
|
ise::project set speed $param::Speed
|
564 |
|
|
}
|
565 |
|
|
|
566 |
|
|
#-------------------------------------------------------------------------
|
567 |
|
|
# Sets the synthesis settings for XST.
|
568 |
|
|
#-------------------------------------------------------------------------
|
569 |
|
|
proc set_xst_synthesis_settings {} {
|
570 |
|
|
# XST specific properties
|
571 |
|
|
ise::project set {Synthesis Tool} {XST (VHDL/Verilog)}
|
572 |
|
|
ise::project set {Optimization Goal} {Speed}
|
573 |
|
|
ise::project set {Optimization Effort} {Normal} -process {Synthesize - XST}
|
574 |
|
|
ise::project set {Keep Hierarchy} $param::KeepHierarchy
|
575 |
|
|
ise::project set {Bus Delimiter} $param::BusDelimiter
|
576 |
|
|
ise::project set {Hierarchy Separator} $param::HierarchySeparator
|
577 |
|
|
set read_cores [project get {Read Cores}]
|
578 |
|
|
# TODO: Remove this check when ISE settles with the read core property value
|
579 |
|
|
if {[string equal -nocase $read_cores "true"] || [string equal -nocase $read_cores "false"]} {
|
580 |
|
|
ise::project set {Read Cores} $param::ReadCores
|
581 |
|
|
} else {
|
582 |
|
|
ise::project set {Read Cores} [ expr { $param::ReadCores ? "Yes" : "No" } ]
|
583 |
|
|
}
|
584 |
|
|
ise::project set {Add I/O Buffers} $param::InsertIOBuffers
|
585 |
|
|
# ise::project set {Optimize Instantiated Primitives} True
|
586 |
|
|
ise::project set {Register Balancing} $param::SynthesisRegisterBalancing
|
587 |
|
|
ise::project set {Register Duplication} $param::SynthesisRegisterDuplication -process {Synthesize - XST}
|
588 |
|
|
ise::project set {Write Timing Constraints} $param::WriteTimingConstraints
|
589 |
|
|
if [info exists param::SynthesisConstraintsFile] {
|
590 |
|
|
ise::project set {Use Synthesis Constraints File} True
|
591 |
|
|
ise::project set {Synthesis Constraints File} $param::SynthesisConstraintsFile
|
592 |
|
|
} else {
|
593 |
|
|
ise::project set {Use Synthesis Constraints File} False
|
594 |
|
|
}
|
595 |
|
|
if [info exists param::FanoutLimit] {
|
596 |
|
|
ise::project set {Max Fanout} $param::FanoutLimit
|
597 |
|
|
}
|
598 |
|
|
}
|
599 |
|
|
|
600 |
|
|
#-------------------------------------------------------------------------
|
601 |
|
|
# Sets the synthesis settings for Synplify/Synplify Pro.
|
602 |
|
|
#-------------------------------------------------------------------------
|
603 |
|
|
proc set_synplify_synthesis_settings {} {
|
604 |
|
|
set is_vhdl [expr { $param::HDLLanguage eq "VHDL" }]
|
605 |
|
|
|
606 |
|
|
switch $param::SynthesisTool {
|
607 |
|
|
"Synplify" {
|
608 |
|
|
if {$is_vhdl} {
|
609 |
|
|
ise::project set {Synthesis Tool} {Synplify (VHDL)}
|
610 |
|
|
} else {
|
611 |
|
|
ise::project set {Synthesis Tool} {Synplify (Verilog)}
|
612 |
|
|
}
|
613 |
|
|
}
|
614 |
|
|
"Synplify Pro" {
|
615 |
|
|
ise::project set {Synthesis Tool} {Synplify Pro (VHDL/Verilog)}
|
616 |
|
|
ise::project set {Retiming} $param::SynthesisRetiming -process {Synthesize - Synplify Pro}
|
617 |
|
|
}
|
618 |
|
|
}
|
619 |
|
|
|
620 |
|
|
# Synplify/Synplify Pro specific properties
|
621 |
|
|
ise::project set {Symbolic FSM Compiler} False
|
622 |
|
|
ise::project set {Pipelining} False
|
623 |
|
|
ise::project set {Resource Sharing} False
|
624 |
|
|
ise::project set {Disable I/O insertion} [ expr { $param::InsertIOBuffers ? False : True } ]
|
625 |
|
|
ise::project set {Auto Constrain} False
|
626 |
|
|
if [info exists param::SynthesisConstraintsFile] {
|
627 |
|
|
ise::project set {Constraint File Name} $param::SynthesisConstraintsFile
|
628 |
|
|
}
|
629 |
|
|
ise::project set {Write Vendor Constraint File} $param::WriteVendorConstraints
|
630 |
|
|
if [info exists param::Frequency] {
|
631 |
|
|
ise::project set {Frequency} $param::Frequency
|
632 |
|
|
}
|
633 |
|
|
if [info exists param::FanoutLimit] {
|
634 |
|
|
ise::project set {Fanout Guide} $param::FanoutLimit
|
635 |
|
|
}
|
636 |
|
|
}
|
637 |
|
|
|
638 |
|
|
#-------------------------------------------------------------------------
|
639 |
|
|
# Sets the synthesis settings.
|
640 |
|
|
#-------------------------------------------------------------------------
|
641 |
|
|
proc set_synthesis_settings {} {
|
642 |
|
|
ise::project set {Preferred Language} $param::HDLLanguage
|
643 |
|
|
|
644 |
|
|
switch -- $param::SynthesisTool {
|
645 |
|
|
"XST" {
|
646 |
|
|
set_xst_synthesis_settings
|
647 |
|
|
}
|
648 |
|
|
"Synplify" - "Synplify Pro" {
|
649 |
|
|
set_synplify_synthesis_settings
|
650 |
|
|
}
|
651 |
|
|
}
|
652 |
|
|
}
|
653 |
|
|
|
654 |
|
|
#-------------------------------------------------------------------------
|
655 |
|
|
# Sets the implementation settings.
|
656 |
|
|
#-------------------------------------------------------------------------
|
657 |
|
|
proc set_implementation_settings {} {
|
658 |
|
|
# Translate properties
|
659 |
|
|
ise::project set {Netlist Translation Type} {Timestamp}
|
660 |
|
|
ise::project set {Use LOC Constraints} True
|
661 |
|
|
if [info exists param::BlockMemoryMapFile] {
|
662 |
|
|
ise::project set {Other Ngdbuild Command Line Options} "-bm $param::BlockMemoryMapFile"
|
663 |
|
|
}
|
664 |
|
|
|
665 |
|
|
# Determine the type of value the "Map Register Duplication" property accepts
|
666 |
|
|
switch -- $param::Family {
|
667 |
|
|
"virtex" - "virtexe" - "spartan2" - "spartan2e" {
|
668 |
|
|
}
|
669 |
|
|
default {
|
670 |
|
|
set map_reg_dup [project get {Register Duplication} -process {Map}]
|
671 |
|
|
if {[string equal -nocase $map_reg_dup "true"] || [string equal -nocase $map_reg_dup "false"]} {
|
672 |
|
|
set map_reg_dup $param::MapRegisterDuplication
|
673 |
|
|
} elseif {[string equal -nocase $map_reg_dup "on"] || [string equal -nocase $map_reg_dup "off"]} {
|
674 |
|
|
set map_reg_dup [ expr { $param::MapRegisterDuplication ? "On" : "Off" } ]
|
675 |
|
|
} else {
|
676 |
|
|
set map_reg_dup [ expr { $param::MapRegisterDuplication ? "Yes" : "No" } ]
|
677 |
|
|
}
|
678 |
|
|
}
|
679 |
|
|
}
|
680 |
|
|
|
681 |
|
|
# Map properties
|
682 |
|
|
switch -glob -- $param::Family {
|
683 |
|
|
"*virtex4*" - "*spartan3*" {
|
684 |
|
|
ise::project set {Map Effort Level} $param::MapEffortLevel
|
685 |
|
|
ise::project set {Perform Timing-Driven Packing and Placement} True
|
686 |
|
|
ise::project set {Register Duplication} $map_reg_dup -process {Map}
|
687 |
|
|
}
|
688 |
|
|
"virtex" - "virtexe" - "spartan2" - "spartan2e" {
|
689 |
|
|
ise::project set {Perform Timing-Driven Packing} True
|
690 |
|
|
}
|
691 |
|
|
default {
|
692 |
|
|
ise::project set {Placer Effort Level} $param::MapEffortLevel
|
693 |
|
|
ise::project set {Register Duplication} $map_reg_dup -process {Map}
|
694 |
|
|
}
|
695 |
|
|
}
|
696 |
|
|
|
697 |
|
|
# Place & Route properties
|
698 |
|
|
ise::project set {Place & Route Effort Level (Overall)} $param::PAREffortLevel
|
699 |
|
|
}
|
700 |
|
|
|
701 |
|
|
#-------------------------------------------------------------------------
|
702 |
|
|
# Sets the configuration settings
|
703 |
|
|
#-------------------------------------------------------------------------
|
704 |
|
|
proc set_configuration_settings {} {
|
705 |
|
|
switch -- $param::CompilationFlow {
|
706 |
|
|
"hwcosim" {
|
707 |
|
|
ise::project set {FPGA Start-Up Clock} {JTAG Clock}
|
708 |
|
|
ise::project set {Drive Done Pin High} True
|
709 |
|
|
switch -- $param::Family {
|
710 |
|
|
"virtex2" - "virtex2p" - "virtex4" - "virtex5" {
|
711 |
|
|
ise::project set {Configuration Pin M0} {Pull Up}
|
712 |
|
|
ise::project set {Configuration Pin M1} {Pull Down}
|
713 |
|
|
ise::project set {Configuration Pin M2} {Pull Up}
|
714 |
|
|
}
|
715 |
|
|
}
|
716 |
|
|
}
|
717 |
|
|
}
|
718 |
|
|
if [info exists param::BlockMemoryContentFile] {
|
719 |
|
|
ise::project set {Other Bitgen Command Line Options} "-bd $param::BlockMemoryContentFile"
|
720 |
|
|
}
|
721 |
|
|
}
|
722 |
|
|
|
723 |
|
|
#-------------------------------------------------------------------------
|
724 |
|
|
# Sets the simulation settings
|
725 |
|
|
#-------------------------------------------------------------------------
|
726 |
|
|
proc set_simulation_settings {} {
|
727 |
|
|
set has_testbench [info exists param::TestBenchModule]
|
728 |
|
|
if {!$has_testbench} { return }
|
729 |
|
|
|
730 |
|
|
set has_simtime [info exists param::SimulationTime]
|
731 |
|
|
|
732 |
|
|
# ISE Simulator settings
|
733 |
|
|
ise::project set {Simulator} "ISim (VHDL/Verilog)"
|
734 |
|
|
|
735 |
|
|
set sim_proc_list {
|
736 |
|
|
{Simulate Behavioral Model}
|
737 |
|
|
{Simulate Post-Place & Route Model}
|
738 |
|
|
}
|
739 |
|
|
|
740 |
|
|
set top_level_modules [expr { $param::HasVerilogSource ? "$param::TestBenchModule glbl": $param::TestBenchModule }]
|
741 |
|
|
set has_isim_custom_prj_file [info exists param::ISimCustomProjectFile]
|
742 |
|
|
foreach {process} $sim_proc_list {
|
743 |
|
|
ise::project set {Specify Top Level Instance Names} $top_level_modules -process $process
|
744 |
|
|
if {$has_isim_custom_prj_file} {
|
745 |
|
|
ise::project set {Use Custom Project File} True -process $process
|
746 |
|
|
ise::project set {Custom Project Filename} $param::ISimCustomProjectFile -process $process
|
747 |
|
|
} else {
|
748 |
|
|
ise::project set {Use Custom Project File} False -process $process
|
749 |
|
|
}
|
750 |
|
|
ise::project set {Run for Specified Time} $has_simtime -process $process
|
751 |
|
|
if {$has_simtime} {
|
752 |
|
|
ise::project set {Simulation Run Time} $param::SimulationTime -process $process
|
753 |
|
|
}
|
754 |
|
|
if {$param::HasVerilogSource} {
|
755 |
|
|
ise::project set {Other Compiler Options} {-L unisims_ver -L simprims_ver -L xilinxcorelib_ver -L secureip} -process $process
|
756 |
|
|
}
|
757 |
|
|
}
|
758 |
|
|
|
759 |
|
|
ise::project set {ISim UUT Instance Name} $param::DesignInstance
|
760 |
|
|
|
761 |
|
|
if [info exists param::Simulator] {
|
762 |
|
|
switch [string tolower $param::Simulator] {
|
763 |
|
|
"isim" - "ise simulator" {
|
764 |
|
|
return
|
765 |
|
|
}
|
766 |
|
|
default {
|
767 |
|
|
ise::project set {Simulator} "$param::Simulator $param::HDLLanguage"
|
768 |
|
|
}
|
769 |
|
|
}
|
770 |
|
|
}
|
771 |
|
|
|
772 |
|
|
# Modelsim settings
|
773 |
|
|
set sim_proc_param_map {
|
774 |
|
|
{Simulate Behavioral Model} param::BehavioralSimulationCustomDoFile
|
775 |
|
|
{Simulate Post-Translate Model} param::PostTranslateSimulationCustomDoFile
|
776 |
|
|
{Simulate Post-Map Model} param::PostMapSimulationCustomDoFile
|
777 |
|
|
{Simulate Post-Place & Route Model} param::PostPARSimulationCustomDoFile
|
778 |
|
|
}
|
779 |
|
|
|
780 |
|
|
foreach {process param} $sim_proc_param_map {
|
781 |
|
|
if [info exists $param] {
|
782 |
|
|
ise::project set {Use Custom Do File} True -process $process
|
783 |
|
|
ise::project set {Custom Do File} [subst $$param] -process $process
|
784 |
|
|
ise::project set {Use Automatic Do File} False -process $process
|
785 |
|
|
}
|
786 |
|
|
}
|
787 |
|
|
|
788 |
|
|
if {$has_simtime} {
|
789 |
|
|
foreach {process param} $sim_proc_param_map {
|
790 |
|
|
ise::project set {Simulation Run Time} $param::SimulationTime -process $process
|
791 |
|
|
}
|
792 |
|
|
}
|
793 |
|
|
}
|
794 |
|
|
|
795 |
|
|
#-------------------------------------------------------------------------
|
796 |
|
|
# Sets the specific settings related to DSP Tools
|
797 |
|
|
#-------------------------------------------------------------------------
|
798 |
|
|
proc set_dsptools_specific_settings {} {
|
799 |
|
|
if [info exists param::ImplementationStopView] {
|
800 |
|
|
ise::project set {Implementation Stop View} $param::ImplementationStopView
|
801 |
|
|
}
|
802 |
|
|
if [info exists param::ProjectGenerator] {
|
803 |
|
|
ise::project set {Project Generator} $param::ProjectGenerator
|
804 |
|
|
}
|
805 |
|
|
}
|
806 |
|
|
|
807 |
|
|
#-------------------------------------------------------------------------
|
808 |
|
|
# Starts the project creation.
|
809 |
|
|
#-------------------------------------------------------------------------
|
810 |
|
|
proc start_project_creation {} {
|
811 |
|
|
file delete "$param::Project\.ise"
|
812 |
|
|
file delete "$param::Project\.xise"
|
813 |
|
|
file delete "$param::Project\.gise"
|
814 |
|
|
file delete "$param::Project\.sgp"
|
815 |
|
|
ise::project new $param::Project
|
816 |
|
|
}
|
817 |
|
|
|
818 |
|
|
#-------------------------------------------------------------------------
|
819 |
|
|
# Finishes the project creation.
|
820 |
|
|
#-------------------------------------------------------------------------
|
821 |
|
|
proc finish_project_creation {} {
|
822 |
|
|
ise::project close
|
823 |
|
|
}
|
824 |
|
|
|
825 |
|
|
#-------------------------------------------------------------------------
|
826 |
|
|
# Creates a new ISE project.
|
827 |
|
|
#-------------------------------------------------------------------------
|
828 |
|
|
proc create_ise_project {} {
|
829 |
|
|
start_project_creation
|
830 |
|
|
set_project_settings
|
831 |
|
|
add_project_files
|
832 |
|
|
set_dsptools_specific_settings
|
833 |
|
|
set_synthesis_settings
|
834 |
|
|
set_implementation_settings
|
835 |
|
|
set_configuration_settings
|
836 |
|
|
set_simulation_settings
|
837 |
|
|
finish_project_creation
|
838 |
|
|
}
|
839 |
|
|
|
840 |
|
|
#-------------------------------------------------------------------------
|
841 |
|
|
# Compiles an ISE project into a bitstream.
|
842 |
|
|
#-------------------------------------------------------------------------
|
843 |
|
|
proc compile_ise_project {} {
|
844 |
|
|
ise::project open $param::Project
|
845 |
|
|
ise::process run {Synthesize}
|
846 |
|
|
ise::process run {Translate}
|
847 |
|
|
ise::process run {Map}
|
848 |
|
|
ise::process run {Place & Route}
|
849 |
|
|
ise::process run {Generate Post-Place & Route Static Timing}
|
850 |
|
|
ise::process run {Generate Programming File}
|
851 |
|
|
ise::project close
|
852 |
|
|
}
|
853 |
|
|
|
854 |
|
|
#-------------------------------------------------------------------------
|
855 |
|
|
# Entry point for creating a new ISE project.
|
856 |
|
|
#-------------------------------------------------------------------------
|
857 |
|
|
proc create {} {
|
858 |
|
|
set status [handle_exception {
|
859 |
|
|
decorate_ise_commands
|
860 |
|
|
} "ERROR: An error occurred when loading ISE Tcl commands." False]
|
861 |
|
|
if {!$status} { return }
|
862 |
|
|
|
863 |
|
|
set status [handle_exception {
|
864 |
|
|
process_parameters
|
865 |
|
|
dump_parameters
|
866 |
|
|
} "ERROR: An error occurred when processing project parameters."]
|
867 |
|
|
if {!$status} { return }
|
868 |
|
|
|
869 |
|
|
set status [handle_exception {
|
870 |
|
|
create_ise_project
|
871 |
|
|
} "ERROR: An error occurred when creating the ISE project."]
|
872 |
|
|
if {!$status} { return }
|
873 |
|
|
}
|
874 |
|
|
|
875 |
|
|
}
|
876 |
|
|
# END namespace ::xilinx::dsptool::iseproject
|